2 * trampoline.S: Jump start slave processors on sparc64.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
7 #include <linux/init.h>
14 #include <asm/pstate.h>
16 #include <asm/pgtable.h>
17 #include <asm/spitfire.h>
18 #include <asm/processor.h>
19 #include <asm/thread_info.h>
21 #include <asm/hypervisor.h>
22 #include <asm/cpudata.h>
30 .asciz "SUNW,itlb-load"
33 .asciz "SUNW,dtlb-load"
35 #define TRAMP_STACK_SIZE 1024
38 .skip TRAMP_STACK_SIZE
41 .globl sparc64_cpu_startup, sparc64_cpu_startup_end
43 BRANCH_IF_SUN4V(g1, niagara_startup)
44 BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
45 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
47 ba,pt %xcc, spitfire_startup
51 /* Preserve OBP chosen DCU and DCR register settings. */
52 ba,pt %xcc, cheetah_generic_startup
56 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
59 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
60 or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
62 or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
63 stxa %g5, [%g0] ASI_DCU_CONTROL_REG
67 cheetah_generic_startup:
68 mov TSB_EXTENSION_P, %g3
69 stxa %g0, [%g3] ASI_DMMU
70 stxa %g0, [%g3] ASI_IMMU
73 mov TSB_EXTENSION_S, %g3
74 stxa %g0, [%g3] ASI_DMMU
77 mov TSB_EXTENSION_N, %g3
78 stxa %g0, [%g3] ASI_DMMU
79 stxa %g0, [%g3] ASI_IMMU
84 /* Disable STICK_INT interrupts. */
85 sethi %hi(0x80000000), %g5
89 ba,pt %xcc, startup_continue
93 mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
94 stxa %g1, [%g0] ASI_LSU_CONTROL
99 BRANCH_IF_SUN4V(g1, niagara_lock_tlb)
101 sethi %hi(0x80000000), %g2
103 wr %g2, 0, %tick_cmpr
105 /* Call OBP by hand to lock KERNBASE into i/d tlbs.
106 * We lock 'num_kernel_image_mappings' consequetive entries.
108 sethi %hi(prom_entry_lock), %g2
109 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1
113 sethi %hi(p1275buf), %g2
114 or %g2, %lo(p1275buf), %g2
115 ldx [%g2 + 0x10], %l2
116 add %l2, -(192 + 128), %sp
119 /* Setup the loop variables:
122 * %l5: Loop iterator, iterates from 0 to 'num_kernel_image_mappings'
123 * %l6: Number of TTE entries to map
124 * %l7: Highest TTE entry number, we count down
126 sethi %hi(KERNBASE), %l3
127 sethi %hi(kern_locked_tte_data), %l4
128 ldx [%l4 + %lo(kern_locked_tte_data)], %l4
130 sethi %hi(num_kernel_image_mappings), %l6
131 lduw [%l6 + %lo(num_kernel_image_mappings)], %l6
134 BRANCH_IF_ANY_CHEETAH(g1,g5,2f)
140 /* Lock into I-MMU */
141 sethi %hi(call_method), %g2
142 or %g2, %lo(call_method), %g2
143 stx %g2, [%sp + 2047 + 128 + 0x00]
145 stx %g2, [%sp + 2047 + 128 + 0x08]
147 stx %g2, [%sp + 2047 + 128 + 0x10]
148 sethi %hi(itlb_load), %g2
149 or %g2, %lo(itlb_load), %g2
150 stx %g2, [%sp + 2047 + 128 + 0x18]
151 sethi %hi(prom_mmu_ihandle_cache), %g2
152 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
153 stx %g2, [%sp + 2047 + 128 + 0x20]
155 /* Each TTE maps 4MB, convert index to offset. */
159 stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR
161 stx %g2, [%sp + 2047 + 128 + 0x30] ! TTE
163 /* TTE index is highest minus loop index. */
165 stx %g2, [%sp + 2047 + 128 + 0x38]
167 sethi %hi(p1275buf), %g2
168 or %g2, %lo(p1275buf), %g2
169 ldx [%g2 + 0x08], %o1
171 add %sp, (2047 + 128), %o0
173 /* Lock into D-MMU */
174 sethi %hi(call_method), %g2
175 or %g2, %lo(call_method), %g2
176 stx %g2, [%sp + 2047 + 128 + 0x00]
178 stx %g2, [%sp + 2047 + 128 + 0x08]
180 stx %g2, [%sp + 2047 + 128 + 0x10]
181 sethi %hi(dtlb_load), %g2
182 or %g2, %lo(dtlb_load), %g2
183 stx %g2, [%sp + 2047 + 128 + 0x18]
184 sethi %hi(prom_mmu_ihandle_cache), %g2
185 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
186 stx %g2, [%sp + 2047 + 128 + 0x20]
188 /* Each TTE maps 4MB, convert index to offset. */
192 stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR
194 stx %g2, [%sp + 2047 + 128 + 0x30] ! TTE
196 /* TTE index is highest minus loop index. */
198 stx %g2, [%sp + 2047 + 128 + 0x38]
200 sethi %hi(p1275buf), %g2
201 or %g2, %lo(p1275buf), %g2
202 ldx [%g2 + 0x08], %o1
204 add %sp, (2047 + 128), %o0
211 sethi %hi(prom_entry_lock), %g2
212 stb %g0, [%g2 + %lo(prom_entry_lock)]
214 ba,pt %xcc, after_lock_tlb
218 sethi %hi(KERNBASE), %l3
219 sethi %hi(kern_locked_tte_data), %l4
220 ldx [%l4 + %lo(kern_locked_tte_data)], %l4
222 sethi %hi(num_kernel_image_mappings), %l6
223 lduw [%l6 + %lo(num_kernel_image_mappings)], %l6
226 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
234 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
248 wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
253 mov PRIMARY_CONTEXT, %g7
255 661: stxa %g0, [%g7] ASI_DMMU
256 .section .sun4v_1insn_patch, "ax"
258 stxa %g0, [%g7] ASI_MMU
262 mov SECONDARY_CONTEXT, %g7
264 661: stxa %g0, [%g7] ASI_DMMU
265 .section .sun4v_1insn_patch, "ax"
267 stxa %g0, [%g7] ASI_MMU
272 /* Everything we do here, until we properly take over the
273 * trap table, must be done with extreme care. We cannot
274 * make any references to %g6 (current thread pointer),
275 * %g4 (current task pointer), or %g5 (base of current cpu's
276 * per-cpu area) until we properly take over the trap table
277 * from the firmware and hypervisor.
279 * Get onto temporary stack which is in the locked kernel image.
281 sethi %hi(tramp_stack), %g1
282 or %g1, %lo(tramp_stack), %g1
283 add %g1, TRAMP_STACK_SIZE, %g1
284 sub %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp
287 /* Put garbage in these registers to trap any access to them. */
292 call init_irqwork_curcpu
295 sethi %hi(tlb_type), %g3
296 lduw [%g3 + %lo(tlb_type)], %g2
301 call hard_smp_processor_id
304 call sun4v_register_mondo_queues
307 1: call init_cur_cpu_trap
310 /* Start using proper page size encodings in ctx register. */
311 sethi %hi(sparc64_kern_pri_context), %g3
312 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
313 mov PRIMARY_CONTEXT, %g1
315 661: stxa %g2, [%g1] ASI_DMMU
316 .section .sun4v_1insn_patch, "ax"
318 stxa %g2, [%g1] ASI_MMU
325 sethi %hi(prom_entry_lock), %g2
326 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1
330 /* As a hack, put &init_thread_union into %g6.
331 * prom_world() loads from here to restore the %asi
334 sethi %hi(init_thread_union), %g6
335 or %g6, %lo(init_thread_union), %g6
337 sethi %hi(is_sun4v), %o0
338 lduw [%o0 + %lo(is_sun4v)], %o0
342 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
343 add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
344 stxa %g2, [%g0] ASI_SCRATCHPAD
346 /* Compute physical address:
348 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
350 sethi %hi(KERNBASE), %g3
352 sethi %hi(kern_base), %g3
353 ldx [%g3 + %lo(kern_base)], %g3
355 sethi %hi(sparc64_ttable_tl0), %o0
357 set prom_set_trap_table_name, %g2
358 stx %g2, [%sp + 2047 + 128 + 0x00]
360 stx %g2, [%sp + 2047 + 128 + 0x08]
362 stx %g2, [%sp + 2047 + 128 + 0x10]
363 stx %o0, [%sp + 2047 + 128 + 0x18]
364 stx %o1, [%sp + 2047 + 128 + 0x20]
365 sethi %hi(p1275buf), %g2
366 or %g2, %lo(p1275buf), %g2
367 ldx [%g2 + 0x08], %o1
369 add %sp, (2047 + 128), %o0
374 2: sethi %hi(sparc64_ttable_tl0), %o0
375 set prom_set_trap_table_name, %g2
376 stx %g2, [%sp + 2047 + 128 + 0x00]
378 stx %g2, [%sp + 2047 + 128 + 0x08]
380 stx %g2, [%sp + 2047 + 128 + 0x10]
381 stx %o0, [%sp + 2047 + 128 + 0x18]
382 sethi %hi(p1275buf), %g2
383 or %g2, %lo(p1275buf), %g2
384 ldx [%g2 + 0x08], %o1
386 add %sp, (2047 + 128), %o0
388 3: sethi %hi(prom_entry_lock), %g2
389 stb %g0, [%g2 + %lo(prom_entry_lock)]
392 ldx [%g6 + TI_TASK], %g4
395 sllx %g5, THREAD_SHIFT, %g5
396 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
401 or %o1, PSTATE_IE, %o1
412 sparc64_cpu_startup_end: