Pileus Git - ~andy/linux/blob - arch/sparc/kernel/pcr.c

   1 /* pcr.c: Generic sparc64 performance counter infrastructure.
   2  *
   3  * Copyright (C) 2009 David S. Miller (davem@davemloft.net)
   4  */
   5 #include <linux/kernel.h>
   6 #include <linux/module.h>
   7 #include <linux/init.h>
   8 #include <linux/irq.h>
   9
  10 #include <linux/irq_work.h>
  11 #include <linux/ftrace.h>
  12
  13 #include <asm/pil.h>
  14 #include <asm/pcr.h>
  15 #include <asm/nmi.h>
  16
  17 /* This code is shared between various users of the performance
  18  * counters.  Users will be oprofile, pseudo-NMI watchdog, and the
  19  * perf_event support layer.
  20  */
  21
  22 #define PCR_SUN4U_ENABLE        (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE)
  23 #define PCR_N2_ENABLE           (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE | \
  24                                  PCR_N2_TOE_OV1 | \
  25                                  (2 << PCR_N2_SL1_SHIFT) | \
  26                                  (0xff << PCR_N2_MASK1_SHIFT))
  27
  28 u64 pcr_enable;
  29 unsigned int picl_shift;
  30
  31 /* Performance counter interrupts run unmasked at PIL level 15.
  32  * Therefore we can't do things like wakeups and other work
  33  * that expects IRQ disabling to be adhered to in locking etc.
  34  *
  35  * Therefore in such situations we defer the work by signalling
  36  * a lower level cpu IRQ.
  37  */
  38 void __irq_entry deferred_pcr_work_irq(int irq, struct pt_regs *regs)
  39 {
  40         struct pt_regs *old_regs;
  41
  42         clear_softint(1 << PIL_DEFERRED_PCR_WORK);
  43
  44         old_regs = set_irq_regs(regs);
  45         irq_enter();
  46 #ifdef CONFIG_IRQ_WORK
  47         irq_work_run();
  48 #endif
  49         irq_exit();
  50         set_irq_regs(old_regs);
  51 }
  52
  53 void arch_irq_work_raise(void)
  54 {
  55         set_softint(1 << PIL_DEFERRED_PCR_WORK);
  56 }
  57
  58 const struct pcr_ops *pcr_ops;
  59 EXPORT_SYMBOL_GPL(pcr_ops);
  60
  61 static u64 direct_pcr_read(void)
  62 {
  63         u64 val;
  64
  65         read_pcr(val);
  66         return val;
  67 }
  68
  69 static void direct_pcr_write(u64 val)
  70 {
  71         write_pcr(val);
  72 }
  73
  74 static const struct pcr_ops direct_pcr_ops = {
  75         .read   = direct_pcr_read,
  76         .write  = direct_pcr_write,
  77 };
  78
  79 static void n2_pcr_write(u64 val)
  80 {
  81         unsigned long ret;
  82
  83         if (val & PCR_N2_HTRACE) {
  84                 ret = sun4v_niagara2_setperf(HV_N2_PERF_SPARC_CTL, val);
  85                 if (ret != HV_EOK)
  86                         write_pcr(val);
  87         } else
  88                 write_pcr(val);
  89 }
  90
  91 static const struct pcr_ops n2_pcr_ops = {
  92         .read   = direct_pcr_read,
  93         .write  = n2_pcr_write,
  94 };
  95
  96 static unsigned long perf_hsvc_group;
  97 static unsigned long perf_hsvc_major;
  98 static unsigned long perf_hsvc_minor;
  99
 100 static int __init register_perf_hsvc(void)
 101 {
 102         if (tlb_type == hypervisor) {
 103                 switch (sun4v_chip_type) {
 104                 case SUN4V_CHIP_NIAGARA1:
 105                         perf_hsvc_group = HV_GRP_NIAG_PERF;
 106                         break;
 107
 108                 case SUN4V_CHIP_NIAGARA2:
 109                         perf_hsvc_group = HV_GRP_N2_CPU;
 110                         break;
 111
 112                 default:
 113                         return -ENODEV;
 114                 }
 115
 116
 117                 perf_hsvc_major = 1;
 118                 perf_hsvc_minor = 0;
 119                 if (sun4v_hvapi_register(perf_hsvc_group,
 120                                          perf_hsvc_major,
 121                                          &perf_hsvc_minor)) {
 122                         printk("perfmon: Could not register hvapi.\n");
 123                         return -ENODEV;
 124                 }
 125         }
 126         return 0;
 127 }
 128
 129 static void __init unregister_perf_hsvc(void)
 130 {
 131         if (tlb_type != hypervisor)
 132                 return;
 133         sun4v_hvapi_unregister(perf_hsvc_group);
 134 }
 135
 136 int __init pcr_arch_init(void)
 137 {
 138         int err = register_perf_hsvc();
 139
 140         if (err)
 141                 return err;
 142
 143         switch (tlb_type) {
 144         case hypervisor:
 145                 pcr_ops = &n2_pcr_ops;
 146                 pcr_enable = PCR_N2_ENABLE;
 147                 picl_shift = 2;
 148                 break;
 149
 150         case cheetah:
 151         case cheetah_plus:
 152                 pcr_ops = &direct_pcr_ops;
 153                 pcr_enable = PCR_SUN4U_ENABLE;
 154                 break;
 155
 156         case spitfire:
 157                 /* UltraSPARC-I/II and derivatives lack a profile
 158                  * counter overflow interrupt so we can't make use of
 159                  * their hardware currently.
 160                  */
 161                 /* fallthrough */
 162         default:
 163                 err = -ENODEV;
 164                 goto out_unregister;
 165         }
 166
 167         return nmi_init();
 168
 169 out_unregister:
 170         unregister_perf_hsvc();
 171         return err;
 172 }