2 * head.S: The initial boot code for the Sparc port of Linux.
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,1999 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 * Copyright (C) 1997 Michael A. Griffith (grif@acm.org)
10 * CompactPCI platform by Eric Brower, 1999.
13 #include <linux/version.h>
14 #include <linux/init.h>
18 #include <asm/contregs.h>
19 #include <asm/ptrace.h>
22 #include <asm/kdebug.h>
23 #include <asm/winmacro.h>
24 #include <asm/thread_info.h> /* TI_UWINMASK */
25 #include <asm/errno.h>
26 #include <asm/pgtsrmmu.h> /* SRMMU_PGDIR_SHIFT */
29 /* The following are used with the prom_vector node-ops to figure out
42 /* Tested on SS-5, SS-10 */
50 .asciz "Sparc-Linux sun4/sun4c or MMU-less not supported\n\n"
54 .asciz "Sparc-Linux sun4e support does not exist\n\n"
57 /* The trap-table - located in the __HEAD section */
58 #include "ttable_32.S"
62 /* This was the only reasonable way I could think of to properly align
63 * these page-table data structures.
66 swapper_pg_dir: .skip PAGE_SIZE
67 .globl empty_zero_page
68 empty_zero_page: .skip PAGE_SIZE
73 .global sparc_ramdisk_image
74 .global sparc_ramdisk_size
76 /* This stuff has to be in sync with SILO and other potential boot loaders
77 * Fields should be kept upward compatible and whenever any change is made,
78 * HdrS version should be incremented.
81 .word LINUX_VERSION_CODE
82 .half 0x0203 /* HdrS version */
97 /* Cool, here we go. Pick up the romvec pointer in %o0 and stash it in
98 * %g7 and at prom_vector_p. And also quickly check whether we are on
99 * a v0, v2, or v3 prom.
102 /* Ok, it's nice to know, as early as possible, if we
103 * are already mapped where we expect to be in virtual
104 * memory. The Solaris /boot elf format bootloader
105 * will peek into our elf header and load us where
106 * we want to be, otherwise we have to re-map.
108 * Some boot loaders don't place the jmp'rs address
109 * in %o7, so we do a pc-relative call to a local
110 * label, then see what %o7 has.
113 mov %o7, %g4 ! Save %o7
115 /* Jump to it, and pray... */
125 mov %g4, %o7 /* Previous %o7. */
127 mov %o0, %l0 ! stash away romvec
128 mov %o0, %g7 ! put it here too
129 mov %o1, %l1 ! stash away debug_vec too
131 /* Ok, let's check out our run time program counter. */
137 /* %l6 will hold the offset we have to subtract
138 * from absolute symbols in order to access areas
139 * in our own image. If already mapped this is
140 * just plain zero, else it is KERNBASE.
149 /* Copy over the Prom's level 14 clock handler. */
153 * preserve our linked/calculated instructions
157 sub %g1, %l6, %g1 ! translate to physical
158 sub %g3, %l6, %g3 ! translate to physical
165 andn %g1, 0xfff, %g1 ! proms trap table base
166 or %g0, (0x1e<<4), %g2 ! offset to lvl14 intr
173 std %g4, [%g3 + 0x8] ! Copy proms handler
175 /* DON'T TOUCH %l0 thru %l5 in these remapping routines,
176 * we need their values afterwards!
179 /* Now check whether we are already mapped, if we
180 * are we can skip all this garbage coming up.
184 be go_to_highmem ! this will be a nop then
187 /* Validate that we are in fact running on an
205 /* It looks like this is a machine we support.
206 * Now find out what MMU we are dealing with
207 * LEON - identified by the psr.impl field
208 * Viking - identified by the psr.impl field
209 * In all other cases a sun4m srmmu.
210 * We check that the MMU is enabled in all cases.
213 /* Check if this is a LEON CPU */
215 srl %g3, PSR_IMPL_SHIFT, %g3
216 and %g3, PSR_IMPL_SHIFTED_MASK, %g3
217 cmp %g3, PSR_IMPL_LEON
218 be leon_remap /* It is a LEON - jump */
221 /* Sanity-check, is MMU enabled */
222 lda [%g0] ASI_M_MMUREGS, %g1
227 /* Check for a viking (TI) module. */
232 /* Figure out what kind of viking we are on.
233 * We need to know if we have to play with the
234 * AC bit and disable traps or not.
237 /* I've only seen MicroSparc's on SparcClassics with this
241 lda [%g0] ASI_M_MMUREGS, %g3 ! peek in the control reg
244 bnz srmmu_not_viking ! is in mbus mode
247 rd %psr, %g3 ! DO NOT TOUCH %g3
248 andn %g3, PSR_ET, %g2
252 /* Get context table pointer, then convert to
253 * a physical address, which is 36 bits.
256 lda [%g4] ASI_M_MMUREGS, %g4
257 sll %g4, 0x4, %g4 ! We use this below
260 /* Set the AC bit in the Viking's MMU control reg. */
261 lda [%g0] ASI_M_MMUREGS, %g5 ! DO NOT TOUCH %g5
262 set 0x8000, %g6 ! AC bit mask
263 or %g5, %g6, %g6 ! Or it in...
264 sta %g6, [%g0] ASI_M_MMUREGS ! Close your eyes...
266 /* Grrr, why does it seem like every other load/store
267 * on the sun4m is in some ASI space...
268 * Fine with me, let's get the pointer to the level 1
269 * page table directory and fetch its entry.
271 lda [%g4] ASI_M_BYPASS, %o1 ! This is a level 1 ptr
272 srl %o1, 0x4, %o1 ! Clear low 4 bits
273 sll %o1, 0x8, %o1 ! Make physical
275 /* Ok, pull in the PTD. */
276 lda [%o1] ASI_M_BYPASS, %o2 ! This is the 0x0 16MB pgd
278 /* Calculate to KERNBASE entry. */
279 add %o1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %o3
281 /* Poke the entry into the calculated address. */
282 sta %o2, [%o3] ASI_M_BYPASS
284 /* I don't get it Sun, if you engineered all these
285 * boot loaders and the PROM (thank you for the debugging
286 * features btw) why did you not have them load kernel
287 * images up in high address space, since this is necessary
288 * for ABI compliance anyways? Does this low-mapping provide
289 * enhanced interoperability?
291 * "The PROM is the computer."
294 /* Ok, restore the MMU control register we saved in %g5 */
295 sta %g5, [%g0] ASI_M_MMUREGS ! POW... ouch
297 /* Turn traps back on. We saved it in %g3 earlier. */
298 wr %g3, 0x0, %psr ! tick tock, tick tock
300 /* Now we burn precious CPU cycles due to bad engineering. */
303 /* Wow, all that just to move a 32-bit value from one
304 * place to another... Jump to high memory.
310 /* This works on viking's in Mbus mode and all
311 * other MBUS modules. It is virtually the same as
312 * the above madness sans turning traps off and flipping
316 lda [%g1] ASI_M_MMUREGS, %g1 ! get ctx table ptr
317 sll %g1, 0x4, %g1 ! make physical addr
318 lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table
320 sll %g1, 0x8, %g1 ! make phys addr for l1 tbl
322 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0
323 add %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3
324 sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry
330 /* Sanity-check, is MMU enabled */
331 lda [%g0] ASI_LEON_MMUREGS, %g1
336 /* Same code as in the srmmu_not_viking case,
337 * with the LEON ASI for mmuregs
340 lda [%g1] ASI_LEON_MMUREGS, %g1 ! get ctx table ptr
341 sll %g1, 0x4, %g1 ! make physical addr
342 lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table
344 sll %g1, 0x8, %g1 ! make phys addr for l1 tbl
346 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0
347 add %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3
348 sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry
352 /* Now do a non-relative jump so that PC is in high-memory */
354 set execute_in_high_mem, %g1
358 /* The code above should be at beginning and we have to take care about
359 * short jumps, as branching to .init.text section from .text is usually
362 /* Acquire boot time privileged register values, this will help debugging.
363 * I figure out and store nwindows and nwindowsm1 later on.
366 mov %l0, %o0 ! put back romvec
367 mov %l1, %o1 ! and debug_vec
369 sethi %hi(prom_vector_p), %g1
370 st %o0, [%g1 + %lo(prom_vector_p)]
372 sethi %hi(linux_dbvec), %g1
373 st %o1, [%g1 + %lo(linux_dbvec)]
375 /* Check if this is a LEON CPU.
376 * Skip getprops call if it is
378 srl %g3, PSR_IMPL_SHIFT, %g3
379 and %g3, PSR_IMPL_SHIFTED_MASK, %g3
380 cmp %g3, PSR_IMPL_LEON
384 /* LEON CPU - set boot_cpu_id */
385 sethi %hi(boot_cpu_id), %g2 ! boot-cpu index
388 ldub [%g2 + %lo(boot_cpu_id)], %g1
389 cmp %g1, 0xff ! unset means first CPU
390 #ifdef CONFIG_SPARC_LEON
391 /* XXX Hack to allow build - remove ifdef later */
392 bne leon_smp_cpu_startup ! continue only with master
396 /* Get CPU-ID from most significant 4-bit of ASR17 */
400 /* Update boot_cpu_id only on boot cpu */
401 stub %g1, [%g2 + %lo(boot_cpu_id)]
406 /* Get the machine type via the mysterious romvec node operations. */
412 or %g0, %g0, %o0 ! next_node(0) = first_node
415 sethi %hi(cputypvar), %o1 ! First node has cpu-arch
416 or %o1, %lo(cputypvar), %o1
417 sethi %hi(cputypval), %o2 ! information, the string
418 or %o2, %lo(cputypval), %o2
419 ld [%l1], %l0 ! 'compatible' tells
420 ld [%l0 + 0xc], %l0 ! that we want 'sun4x' where
421 call %l0 ! x is one of 'm', 'd' or 'e'.
422 nop ! %o2 holds pointer
423 ! to a buf where above string
424 ! will get stored by the prom.
426 /* Check to cputype. We may be booted on a sun4u (64 bit box),
427 * and sun4d needs special treatment.
430 ldub [%o2 + 0x4], %l1
439 be no_sun4e_here ! Could be a sun4e.
441 b no_sun4u_here ! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :))
444 /* CPUID in bootbus can be found at PA 0xff0140000 */
445 #define SUN4D_BOOTBUS_CPUID 0xf0140000
448 /* Need to patch call to handler_irq */
449 set patch_handler_irq, %g4
450 set sun4d_handler_irq, %g5
451 sethi %hi(0x40000000), %g3 ! call
458 /* Get our CPU id out of bootbus */
459 set SUN4D_BOOTBUS_CPUID, %g3
460 lduba [%g3] ASI_M_CTL, %g3
463 sta %g4, [%g0] ASI_M_VIKING_TMP1
464 sethi %hi(boot_cpu_id), %g5
465 stb %g4, [%g5 + %lo(boot_cpu_id)]
468 /* Fall through to sun4m_init */
471 /* Ok, the PROM could have done funny things and apple cider could still
472 * be sitting in the fault status/address registers. Read them all to
473 * clear them so we don't get magic faults later on.
475 /* This sucks, apparently this makes Vikings call prom panic, will fix later */
478 srl %o1, PSR_IMPL_SHIFT, %o1 ! Get a type of the CPU
480 subcc %o1, PSR_IMPL_TI, %g0 ! TI: Viking or MicroSPARC
485 lda [%o0] ASI_M_MMUREGS, %g0
487 lda [%o0] ASI_M_MMUREGS, %g0
489 /* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */
495 lda [%o0] ASI_M_MMUREGS, %g0
497 lda [%o0] ASI_M_MMUREGS, %g0
503 /* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's
507 sethi %hi(cputyp), %o0
508 st %g4, [%o0 + %lo(cputyp)]
510 /* Turn on Supervisor, EnableFloating, and all the PIL bits.
511 * Also puts us in register window zero with traps off.
513 set (PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2
517 /* I want a kernel stack NOW! */
518 set init_thread_union, %g1
519 set (THREAD_SIZE - STACKFRAME_SZ), %g2
521 mov 0, %fp /* And for good luck */
523 /* Zero out our BSS section. */
524 set __bss_start , %o0 ! First address of BSS
525 set _end , %o1 ! Last address of BSS
533 /* If boot_cpu_id has not been setup by machine specific
534 * init-code above we default it to zero.
536 sethi %hi(boot_cpu_id), %g2
537 ldub [%g2 + %lo(boot_cpu_id)], %g3
542 stub %g3, [%g2 + %lo(boot_cpu_id)]
546 /* Initialize the uwinmask value for init task just in case.
547 * But first make current_set[boot_cpu_id] point to something useful.
549 set init_thread_union, %g6
557 st %g0, [%g6 + TI_UWINMASK]
559 /* Compute NWINDOWS and stash it away. Now uses %wim trick explained
560 * in the V8 manual. Ok, this method seems to work, Sparc is cool...
561 * No, it doesn't work, have to play the save/readCWP/restore trick.
564 wr %g0, 0x0, %wim ! so we do not get a trap
577 wr %g1, 0x0, %wim ! make window 1 invalid
584 /* Adjust our window handling routines to
585 * do things correctly on 7 window Sparcs.
588 #define PATCH_INSN(src, dest) \
594 /* Patch for window spills... */
595 PATCH_INSN(spnwin_patch1_7win, spnwin_patch1)
596 PATCH_INSN(spnwin_patch2_7win, spnwin_patch2)
597 PATCH_INSN(spnwin_patch3_7win, spnwin_patch3)
599 /* Patch for window fills... */
600 PATCH_INSN(fnwin_patch1_7win, fnwin_patch1)
601 PATCH_INSN(fnwin_patch2_7win, fnwin_patch2)
603 /* Patch for trap entry setup... */
604 PATCH_INSN(tsetup_7win_patch1, tsetup_patch1)
605 PATCH_INSN(tsetup_7win_patch2, tsetup_patch2)
606 PATCH_INSN(tsetup_7win_patch3, tsetup_patch3)
607 PATCH_INSN(tsetup_7win_patch4, tsetup_patch4)
608 PATCH_INSN(tsetup_7win_patch5, tsetup_patch5)
609 PATCH_INSN(tsetup_7win_patch6, tsetup_patch6)
611 /* Patch for returning from traps... */
612 PATCH_INSN(rtrap_7win_patch1, rtrap_patch1)
613 PATCH_INSN(rtrap_7win_patch2, rtrap_patch2)
614 PATCH_INSN(rtrap_7win_patch3, rtrap_patch3)
615 PATCH_INSN(rtrap_7win_patch4, rtrap_patch4)
616 PATCH_INSN(rtrap_7win_patch5, rtrap_patch5)
618 /* Patch for killing user windows from the register file. */
619 PATCH_INSN(kuw_patch1_7win, kuw_patch1)
621 /* Now patch the kernel window flush sequences.
622 * This saves 2 traps on every switch and fork.
625 set flush_patch_one, %g5
628 set flush_patch_two, %g5
631 set flush_patch_three, %g5
634 set flush_patch_four, %g5
637 set flush_patch_exception, %g5
640 set flush_patch_switch, %g5
645 sethi %hi(nwindows), %g4
646 st %g3, [%g4 + %lo(nwindows)] ! store final value
648 sethi %hi(nwindowsm1), %g4
649 st %g3, [%g4 + %lo(nwindowsm1)]
651 /* Here we go, start using Linux's trap table... */
656 /* Finally, turn on traps so that we can call c-code. */
664 /* First we call prom_init() to set up PROMLIB, then
665 * off to start_kernel().
668 sethi %hi(prom_vector_p), %g5
669 ld [%g5 + %lo(prom_vector_p)], %o0
676 /* We should not get here. */
682 set sun4e_notsup, %o0
706 .asciz "\n\rOn sun4u you have to use sparc64 kernel\n\rand not a sparc32 version\n\r\n\r"
713 .word 0, sun4u_1, 0, 1, 0, 1, 0, sun4u_2, 0
717 .word 0, sun4u_3, 0, 4, 0, 1, 0
719 .word 0, 0, sun4u_4, 0, sun4u_1, 0, 8, 0
723 .word 0, sun4u_5, 0, 3, 0, 1, 0
725 .word 0, 0, sun4u_6, 0, sun4u_6e - sun4u_6 - 1, 0
729 .word 0, sun4u_7, 0, 0, 0, 0
742 mov sun4u_r4 - sun4u_a1, %l3
758 ld [%l1 + (sun4u_r1 - sun4u_a1)], %o1
759 add %l1, (sun4u_a2 - sun4u_a1), %o0
761 st %o1, [%o0 + (sun4u_i2 - sun4u_a2)]
763 ld [%l1 + (sun4u_1 - sun4u_a1)], %o1
764 add %l1, (sun4u_a3 - sun4u_a1), %o0
766 st %o1, [%o0 + (sun4u_i3 - sun4u_a3)]
769 add %l1, (sun4u_a4 - sun4u_a1), %o0
774 call %o0 ! Get us out of here...
775 nop ! Apparently Solaris is better.
777 /* Ok, now we continue in the .data/.text sections */
783 * Fill up the prom vector, note in particular the kind first element,
784 * no joke. I don't need all of them in here as the entire prom vector
785 * gets initialized in c-code so all routines can use it.
791 /* We calculate the following at boot time, window fills/spills and trap entry
792 * code uses these to keep track of the register windows.
803 /* Boot time debugger vector value. We need this later on. */
821 .section ".fixup",#alloc,#execinstr
825 restore %g0, -EFAULT, %o0