Pileus Git - ~andy/linux/blob - arch/sh/kernel/traps_64.c

   1 /*
   2  * arch/sh/kernel/traps_64.c
   3  *
   4  * Copyright (C) 2000, 2001  Paolo Alberelli
   5  * Copyright (C) 2003, 2004  Paul Mundt
   6  * Copyright (C) 2003, 2004  Richard Curnow
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/sched.h>
  13 #include <linux/kernel.h>
  14 #include <linux/string.h>
  15 #include <linux/errno.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/timer.h>
  18 #include <linux/mm.h>
  19 #include <linux/smp.h>
  20 #include <linux/init.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/kallsyms.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysctl.h>
  26 #include <linux/module.h>
  27 #include <linux/perf_event.h>
  28 #include <asm/uaccess.h>
  29 #include <asm/io.h>
  30 #include <linux/atomic.h>
  31 #include <asm/processor.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/fpu.h>
  34
  35 #undef DEBUG_EXCEPTION
  36 #ifdef DEBUG_EXCEPTION
  37 /* implemented in ../lib/dbg.c */
  38 extern void show_excp_regs(char *fname, int trapnr, int signr,
  39                            struct pt_regs *regs);
  40 #else
  41 #define show_excp_regs(a, b, c, d)
  42 #endif
  43
  44 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
  45                 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk);
  46
  47 #define DO_ERROR(trapnr, signr, str, name, tsk) \
  48 asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
  49 { \
  50         do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \
  51 }
  52
  53 static DEFINE_SPINLOCK(die_lock);
  54
  55 void die(const char * str, struct pt_regs * regs, long err)
  56 {
  57         console_verbose();
  58         spin_lock_irq(&die_lock);
  59         printk("%s: %lx\n", str, (err & 0xffffff));
  60         show_regs(regs);
  61         spin_unlock_irq(&die_lock);
  62         do_exit(SIGSEGV);
  63 }
  64
  65 static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
  66 {
  67         if (!user_mode(regs))
  68                 die(str, regs, err);
  69 }
  70
  71 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
  72 {
  73         if (!user_mode(regs)) {
  74                 const struct exception_table_entry *fixup;
  75                 fixup = search_exception_tables(regs->pc);
  76                 if (fixup) {
  77                         regs->pc = fixup->fixup;
  78                         return;
  79                 }
  80                 die(str, regs, err);
  81         }
  82 }
  83
  84 DO_ERROR(13, SIGILL,  "illegal slot instruction", illegal_slot_inst, current)
  85 DO_ERROR(87, SIGSEGV, "address error (exec)", address_error_exec, current)
  86
  87
  88 /* Implement misaligned load/store handling for kernel (and optionally for user
  89    mode too).  Limitation : only SHmedia mode code is handled - there is no
  90    handling at all for misaligned accesses occurring in SHcompact code yet. */
  91
  92 static int misaligned_fixup(struct pt_regs *regs);
  93
  94 asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
  95 {
  96         if (misaligned_fixup(regs) < 0) {
  97                 do_unhandled_exception(7, SIGSEGV, "address error(load)",
  98                                 "do_address_error_load",
  99                                 error_code, regs, current);
 100         }
 101         return;
 102 }
 103
 104 asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
 105 {
 106         if (misaligned_fixup(regs) < 0) {
 107                 do_unhandled_exception(8, SIGSEGV, "address error(store)",
 108                                 "do_address_error_store",
 109                                 error_code, regs, current);
 110         }
 111         return;
 112 }
 113
 114 #if defined(CONFIG_SH64_ID2815_WORKAROUND)
 115
 116 #define OPCODE_INVALID      0
 117 #define OPCODE_USER_VALID   1
 118 #define OPCODE_PRIV_VALID   2
 119
 120 /* getcon/putcon - requires checking which control register is referenced. */
 121 #define OPCODE_CTRL_REG     3
 122
 123 /* Table of valid opcodes for SHmedia mode.
 124    Form a 10-bit value by concatenating the major/minor opcodes i.e.
 125    opcode[31:26,20:16].  The 6 MSBs of this value index into the following
 126    array.  The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
 127    LSBs==4'b0000 etc). */
 128 static unsigned long shmedia_opcode_table[64] = {
 129         0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
 130         0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
 131         0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
 132         0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
 133         0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
 134         0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
 135         0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
 136         0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
 137 };
 138
 139 void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
 140 {
 141         /* Workaround SH5-101 cut2 silicon defect #2815 :
 142            in some situations, inter-mode branches from SHcompact -> SHmedia
 143            which should take ITLBMISS or EXECPROT exceptions at the target
 144            falsely take RESINST at the target instead. */
 145
 146         unsigned long opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
 147         unsigned long pc, aligned_pc;
 148         int get_user_error;
 149         int trapnr = 12;
 150         int signr = SIGILL;
 151         char *exception_name = "reserved_instruction";
 152
 153         pc = regs->pc;
 154         if ((pc & 3) == 1) {
 155                 /* SHmedia : check for defect.  This requires executable vmas
 156                    to be readable too. */
 157                 aligned_pc = pc & ~3;
 158                 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
 159                         get_user_error = -EFAULT;
 160                 } else {
 161                         get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
 162                 }
 163                 if (get_user_error >= 0) {
 164                         unsigned long index, shift;
 165                         unsigned long major, minor, combined;
 166                         unsigned long reserved_field;
 167                         reserved_field = opcode & 0xf; /* These bits are currently reserved as zero in all valid opcodes */
 168                         major = (opcode >> 26) & 0x3f;
 169                         minor = (opcode >> 16) & 0xf;
 170                         combined = (major << 4) | minor;
 171                         index = major;
 172                         shift = minor << 1;
 173                         if (reserved_field == 0) {
 174                                 int opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
 175                                 switch (opcode_state) {
 176                                         case OPCODE_INVALID:
 177                                                 /* Trap. */
 178                                                 break;
 179                                         case OPCODE_USER_VALID:
 180                                                 /* Restart the instruction : the branch to the instruction will now be from an RTE
 181                                                    not from SHcompact so the silicon defect won't be triggered. */
 182                                                 return;
 183                                         case OPCODE_PRIV_VALID:
 184                                                 if (!user_mode(regs)) {
 185                                                         /* Should only ever get here if a module has
 186                                                            SHcompact code inside it.  If so, the same fix up is needed. */
 187                                                         return; /* same reason */
 188                                                 }
 189                                                 /* Otherwise, user mode trying to execute a privileged instruction -
 190                                                    fall through to trap. */
 191                                                 break;
 192                                         case OPCODE_CTRL_REG:
 193                                                 /* If in privileged mode, return as above. */
 194                                                 if (!user_mode(regs)) return;
 195                                                 /* In user mode ... */
 196                                                 if (combined == 0x9f) { /* GETCON */
 197                                                         unsigned long regno = (opcode >> 20) & 0x3f;
 198                                                         if (regno >= 62) {
 199                                                                 return;
 200                                                         }
 201                                                         /* Otherwise, reserved or privileged control register, => trap */
 202                                                 } else if (combined == 0x1bf) { /* PUTCON */
 203                                                         unsigned long regno = (opcode >> 4) & 0x3f;
 204                                                         if (regno >= 62) {
 205                                                                 return;
 206                                                         }
 207                                                         /* Otherwise, reserved or privileged control register, => trap */
 208                                                 } else {
 209                                                         /* Trap */
 210                                                 }
 211                                                 break;
 212                                         default:
 213                                                 /* Fall through to trap. */
 214                                                 break;
 215                                 }
 216                         }
 217                         /* fall through to normal resinst processing */
 218                 } else {
 219                         /* Error trying to read opcode.  This typically means a
 220                            real fault, not a RESINST any more.  So change the
 221                            codes. */
 222                         trapnr = 87;
 223                         exception_name = "address error (exec)";
 224                         signr = SIGSEGV;
 225                 }
 226         }
 227
 228         do_unhandled_exception(trapnr, signr, exception_name, "do_reserved_inst", error_code, regs, current);
 229 }
 230
 231 #else /* CONFIG_SH64_ID2815_WORKAROUND */
 232
 233 /* If the workaround isn't needed, this is just a straightforward reserved
 234    instruction */
 235 DO_ERROR(12, SIGILL,  "reserved instruction", reserved_inst, current)
 236
 237 #endif /* CONFIG_SH64_ID2815_WORKAROUND */
 238
 239 /* Called with interrupts disabled */
 240 asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
 241 {
 242         show_excp_regs(__func__, -1, -1, regs);
 243         die_if_kernel("exception", regs, ex);
 244 }
 245
 246 int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
 247 {
 248         /* Syscall debug */
 249         printk("System call ID error: [0x1#args:8 #syscall:16  0x%lx]\n", scId);
 250
 251         die_if_kernel("unknown trapa", regs, scId);
 252
 253         return -ENOSYS;
 254 }
 255
 256 void show_stack(struct task_struct *tsk, unsigned long *sp)
 257 {
 258 #ifdef CONFIG_KALLSYMS
 259         extern void sh64_unwind(struct pt_regs *regs);
 260         struct pt_regs *regs;
 261
 262         regs = tsk ? tsk->thread.kregs : NULL;
 263
 264         sh64_unwind(regs);
 265 #else
 266         printk(KERN_ERR "Can't backtrace on sh64 without CONFIG_KALLSYMS\n");
 267 #endif
 268 }
 269
 270 void show_task(unsigned long *sp)
 271 {
 272         show_stack(NULL, sp);
 273 }
 274
 275 void dump_stack(void)
 276 {
 277         show_task(NULL);
 278 }
 279 /* Needed by any user of WARN_ON in view of the defn in include/asm-sh/bug.h */
 280 EXPORT_SYMBOL(dump_stack);
 281
 282 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
 283                 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)
 284 {
 285         show_excp_regs(fn_name, trapnr, signr, regs);
 286
 287         if (user_mode(regs))
 288                 force_sig(signr, tsk);
 289
 290         die_if_no_fixup(str, regs, error_code);
 291 }
 292
 293 static int read_opcode(unsigned long long pc, unsigned long *result_opcode, int from_user_mode)
 294 {
 295         int get_user_error;
 296         unsigned long aligned_pc;
 297         unsigned long opcode;
 298
 299         if ((pc & 3) == 1) {
 300                 /* SHmedia */
 301                 aligned_pc = pc & ~3;
 302                 if (from_user_mode) {
 303                         if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
 304                                 get_user_error = -EFAULT;
 305                         } else {
 306                                 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
 307                                 *result_opcode = opcode;
 308                         }
 309                         return get_user_error;
 310                 } else {
 311                         /* If the fault was in the kernel, we can either read
 312                          * this directly, or if not, we fault.
 313                         */
 314                         *result_opcode = *(unsigned long *) aligned_pc;
 315                         return 0;
 316                 }
 317         } else if ((pc & 1) == 0) {
 318                 /* SHcompact */
 319                 /* TODO : provide handling for this.  We don't really support
 320                    user-mode SHcompact yet, and for a kernel fault, this would
 321                    have to come from a module built for SHcompact.  */
 322                 return -EFAULT;
 323         } else {
 324                 /* misaligned */
 325                 return -EFAULT;
 326         }
 327 }
 328
 329 static int address_is_sign_extended(__u64 a)
 330 {
 331         __u64 b;
 332 #if (NEFF == 32)
 333         b = (__u64)(__s64)(__s32)(a & 0xffffffffUL);
 334         return (b == a) ? 1 : 0;
 335 #else
 336 #error "Sign extend check only works for NEFF==32"
 337 #endif
 338 }
 339
 340 static int generate_and_check_address(struct pt_regs *regs,
 341                                       __u32 opcode,
 342                                       int displacement_not_indexed,
 343                                       int width_shift,
 344                                       __u64 *address)
 345 {
 346         /* return -1 for fault, 0 for OK */
 347
 348         __u64 base_address, addr;
 349         int basereg;
 350
 351         basereg = (opcode >> 20) & 0x3f;
 352         base_address = regs->regs[basereg];
 353         if (displacement_not_indexed) {
 354                 __s64 displacement;
 355                 displacement = (opcode >> 10) & 0x3ff;
 356                 displacement = ((displacement << 54) >> 54); /* sign extend */
 357                 addr = (__u64)((__s64)base_address + (displacement << width_shift));
 358         } else {
 359                 __u64 offset;
 360                 int offsetreg;
 361                 offsetreg = (opcode >> 10) & 0x3f;
 362                 offset = regs->regs[offsetreg];
 363                 addr = base_address + offset;
 364         }
 365
 366         /* Check sign extended */
 367         if (!address_is_sign_extended(addr)) {
 368                 return -1;
 369         }
 370
 371         /* Check accessible.  For misaligned access in the kernel, assume the
 372            address is always accessible (and if not, just fault when the
 373            load/store gets done.) */
 374         if (user_mode(regs)) {
 375                 if (addr >= TASK_SIZE) {
 376                         return -1;
 377                 }
 378                 /* Do access_ok check later - it depends on whether it's a load or a store. */
 379         }
 380
 381         *address = addr;
 382         return 0;
 383 }
 384
 385 static int user_mode_unaligned_fixup_count = 10;
 386 static int user_mode_unaligned_fixup_enable = 1;
 387 static int kernel_mode_unaligned_fixup_count = 32;
 388
 389 static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
 390 {
 391         unsigned short x;
 392         unsigned char *p, *q;
 393         p = (unsigned char *) (int) address;
 394         q = (unsigned char *) &x;
 395         q[0] = p[0];
 396         q[1] = p[1];
 397
 398         if (do_sign_extend) {
 399                 *result = (__u64)(__s64) *(short *) &x;
 400         } else {
 401                 *result = (__u64) x;
 402         }
 403 }
 404
 405 static void misaligned_kernel_word_store(__u64 address, __u64 value)
 406 {
 407         unsigned short x;
 408         unsigned char *p, *q;
 409         p = (unsigned char *) (int) address;
 410         q = (unsigned char *) &x;
 411
 412         x = (__u16) value;
 413         p[0] = q[0];
 414         p[1] = q[1];
 415 }
 416
 417 static int misaligned_load(struct pt_regs *regs,
 418                            __u32 opcode,
 419                            int displacement_not_indexed,
 420                            int width_shift,
 421                            int do_sign_extend)
 422 {
 423         /* Return -1 for a fault, 0 for OK */
 424         int error;
 425         int destreg;
 426         __u64 address;
 427
 428         error = generate_and_check_address(regs, opcode,
 429                         displacement_not_indexed, width_shift, &address);
 430         if (error < 0) {
 431                 return error;
 432         }
 433
 434         perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, address);
 435
 436         destreg = (opcode >> 4) & 0x3f;
 437         if (user_mode(regs)) {
 438                 __u64 buffer;
 439
 440                 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
 441                         return -1;
 442                 }
 443
 444                 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
 445                         return -1; /* fault */
 446                 }
 447                 switch (width_shift) {
 448                 case 1:
 449                         if (do_sign_extend) {
 450                                 regs->regs[destreg] = (__u64)(__s64) *(__s16 *) &buffer;
 451                         } else {
 452                                 regs->regs[destreg] = (__u64) *(__u16 *) &buffer;
 453                         }
 454                         break;
 455                 case 2:
 456                         regs->regs[destreg] = (__u64)(__s64) *(__s32 *) &buffer;
 457                         break;
 458                 case 3:
 459                         regs->regs[destreg] = buffer;
 460                         break;
 461                 default:
 462                         printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
 463                                 width_shift, (unsigned long) regs->pc);
 464                         break;
 465                 }
 466         } else {
 467                 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
 468                 __u64 lo, hi;
 469
 470                 switch (width_shift) {
 471                 case 1:
 472                         misaligned_kernel_word_load(address, do_sign_extend, &regs->regs[destreg]);
 473                         break;
 474                 case 2:
 475                         asm ("ldlo.l %1, 0, %0" : "=r" (lo) : "r" (address));
 476                         asm ("ldhi.l %1, 3, %0" : "=r" (hi) : "r" (address));
 477                         regs->regs[destreg] = lo | hi;
 478                         break;
 479                 case 3:
 480                         asm ("ldlo.q %1, 0, %0" : "=r" (lo) : "r" (address));
 481                         asm ("ldhi.q %1, 7, %0" : "=r" (hi) : "r" (address));
 482                         regs->regs[destreg] = lo | hi;
 483                         break;
 484
 485                 default:
 486                         printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
 487                                 width_shift, (unsigned long) regs->pc);
 488                         break;
 489                 }
 490         }
 491
 492         return 0;
 493
 494 }
 495
 496 static int misaligned_store(struct pt_regs *regs,
 497                             __u32 opcode,
 498                             int displacement_not_indexed,
 499                             int width_shift)
 500 {
 501         /* Return -1 for a fault, 0 for OK */
 502         int error;
 503         int srcreg;
 504         __u64 address;
 505
 506         error = generate_and_check_address(regs, opcode,
 507                         displacement_not_indexed, width_shift, &address);
 508         if (error < 0) {
 509                 return error;
 510         }
 511
 512         perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, address);
 513
 514         srcreg = (opcode >> 4) & 0x3f;
 515         if (user_mode(regs)) {
 516                 __u64 buffer;
 517
 518                 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
 519                         return -1;
 520                 }
 521
 522                 switch (width_shift) {
 523                 case 1:
 524                         *(__u16 *) &buffer = (__u16) regs->regs[srcreg];
 525                         break;
 526                 case 2:
 527                         *(__u32 *) &buffer = (__u32) regs->regs[srcreg];
 528                         break;
 529                 case 3:
 530                         buffer = regs->regs[srcreg];
 531                         break;
 532                 default:
 533                         printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
 534                                 width_shift, (unsigned long) regs->pc);
 535                         break;
 536                 }
 537
 538                 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
 539                         return -1; /* fault */
 540                 }
 541         } else {
 542                 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
 543                 __u64 val = regs->regs[srcreg];
 544
 545                 switch (width_shift) {
 546                 case 1:
 547                         misaligned_kernel_word_store(address, val);
 548                         break;
 549                 case 2:
 550                         asm ("stlo.l %1, 0, %0" : : "r" (val), "r" (address));
 551                         asm ("sthi.l %1, 3, %0" : : "r" (val), "r" (address));
 552                         break;
 553                 case 3:
 554                         asm ("stlo.q %1, 0, %0" : : "r" (val), "r" (address));
 555                         asm ("sthi.q %1, 7, %0" : : "r" (val), "r" (address));
 556                         break;
 557
 558                 default:
 559                         printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
 560                                 width_shift, (unsigned long) regs->pc);
 561                         break;
 562                 }
 563         }
 564
 565         return 0;
 566
 567 }
 568
 569 /* Never need to fix up misaligned FPU accesses within the kernel since that's a real
 570    error. */
 571 static int misaligned_fpu_load(struct pt_regs *regs,
 572                            __u32 opcode,
 573                            int displacement_not_indexed,
 574                            int width_shift,
 575                            int do_paired_load)
 576 {
 577         /* Return -1 for a fault, 0 for OK */
 578         int error;
 579         int destreg;
 580         __u64 address;
 581
 582         error = generate_and_check_address(regs, opcode,
 583                         displacement_not_indexed, width_shift, &address);
 584         if (error < 0) {
 585                 return error;
 586         }
 587
 588         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, address);
 589
 590         destreg = (opcode >> 4) & 0x3f;
 591         if (user_mode(regs)) {
 592                 __u64 buffer;
 593                 __u32 buflo, bufhi;
 594
 595                 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
 596                         return -1;
 597                 }
 598
 599                 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
 600                         return -1; /* fault */
 601                 }
 602                 /* 'current' may be the current owner of the FPU state, so
 603                    context switch the registers into memory so they can be
 604                    indexed by register number. */
 605                 if (last_task_used_math == current) {
 606                         enable_fpu();
 607                         save_fpu(current);
 608                         disable_fpu();
 609                         last_task_used_math = NULL;
 610                         regs->sr |= SR_FD;
 611                 }
 612
 613                 buflo = *(__u32*) &buffer;
 614                 bufhi = *(1 + (__u32*) &buffer);
 615
 616                 switch (width_shift) {
 617                 case 2:
 618                         current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
 619                         break;
 620                 case 3:
 621                         if (do_paired_load) {
 622                                 current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
 623                                 current->thread.xstate->hardfpu.fp_regs[destreg+1] = bufhi;
 624                         } else {
 625 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
 626                                 current->thread.xstate->hardfpu.fp_regs[destreg] = bufhi;
 627                                 current->thread.xstate->hardfpu.fp_regs[destreg+1] = buflo;
 628 #else
 629                                 current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
 630                                 current->thread.xstate->hardfpu.fp_regs[destreg+1] = bufhi;
 631 #endif
 632                         }
 633                         break;
 634                 default:
 635                         printk("Unexpected width_shift %d in misaligned_fpu_load, PC=%08lx\n",
 636                                 width_shift, (unsigned long) regs->pc);
 637                         break;
 638                 }
 639                 return 0;
 640         } else {
 641                 die ("Misaligned FPU load inside kernel", regs, 0);
 642                 return -1;
 643         }
 644
 645
 646 }
 647
 648 static int misaligned_fpu_store(struct pt_regs *regs,
 649                            __u32 opcode,
 650                            int displacement_not_indexed,
 651                            int width_shift,
 652                            int do_paired_load)
 653 {
 654         /* Return -1 for a fault, 0 for OK */
 655         int error;
 656         int srcreg;
 657         __u64 address;
 658
 659         error = generate_and_check_address(regs, opcode,
 660                         displacement_not_indexed, width_shift, &address);
 661         if (error < 0) {
 662                 return error;
 663         }
 664
 665         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, address);
 666
 667         srcreg = (opcode >> 4) & 0x3f;
 668         if (user_mode(regs)) {
 669                 __u64 buffer;
 670                 /* Initialise these to NaNs. */
 671                 __u32 buflo=0xffffffffUL, bufhi=0xffffffffUL;
 672
 673                 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
 674                         return -1;
 675                 }
 676
 677                 /* 'current' may be the current owner of the FPU state, so
 678                    context switch the registers into memory so they can be
 679                    indexed by register number. */
 680                 if (last_task_used_math == current) {
 681                         enable_fpu();
 682                         save_fpu(current);
 683                         disable_fpu();
 684                         last_task_used_math = NULL;
 685                         regs->sr |= SR_FD;
 686                 }
 687
 688                 switch (width_shift) {
 689                 case 2:
 690                         buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
 691                         break;
 692                 case 3:
 693                         if (do_paired_load) {
 694                                 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
 695                                 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
 696                         } else {
 697 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
 698                                 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg];
 699                                 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
 700 #else
 701                                 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
 702                                 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
 703 #endif
 704                         }
 705                         break;
 706                 default:
 707                         printk("Unexpected width_shift %d in misaligned_fpu_store, PC=%08lx\n",
 708                                 width_shift, (unsigned long) regs->pc);
 709                         break;
 710                 }
 711
 712                 *(__u32*) &buffer = buflo;
 713                 *(1 + (__u32*) &buffer) = bufhi;
 714                 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
 715                         return -1; /* fault */
 716                 }
 717                 return 0;
 718         } else {
 719                 die ("Misaligned FPU load inside kernel", regs, 0);
 720                 return -1;
 721         }
 722 }
 723
 724 static int misaligned_fixup(struct pt_regs *regs)
 725 {
 726         unsigned long opcode;
 727         int error;
 728         int major, minor;
 729
 730         if (!user_mode_unaligned_fixup_enable)
 731                 return -1;
 732
 733         error = read_opcode(regs->pc, &opcode, user_mode(regs));
 734         if (error < 0) {
 735                 return error;
 736         }
 737         major = (opcode >> 26) & 0x3f;
 738         minor = (opcode >> 16) & 0xf;
 739
 740         if (user_mode(regs) && (user_mode_unaligned_fixup_count > 0)) {
 741                 --user_mode_unaligned_fixup_count;
 742                 /* Only do 'count' worth of these reports, to remove a potential DoS against syslog */
 743                 printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
 744                        current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
 745         } else if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
 746                 --kernel_mode_unaligned_fixup_count;
 747                 if (in_interrupt()) {
 748                         printk("Fixing up unaligned kernelspace access in interrupt pc=0x%08x ins=0x%08lx\n",
 749                                (__u32)regs->pc, opcode);
 750                 } else {
 751                         printk("Fixing up unaligned kernelspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
 752                                current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
 753                 }
 754         }
 755
 756
 757         switch (major) {
 758                 case (0x84>>2): /* LD.W */
 759                         error = misaligned_load(regs, opcode, 1, 1, 1);
 760                         break;
 761                 case (0xb0>>2): /* LD.UW */
 762                         error = misaligned_load(regs, opcode, 1, 1, 0);
 763                         break;
 764                 case (0x88>>2): /* LD.L */
 765                         error = misaligned_load(regs, opcode, 1, 2, 1);
 766                         break;
 767                 case (0x8c>>2): /* LD.Q */
 768                         error = misaligned_load(regs, opcode, 1, 3, 0);
 769                         break;
 770
 771                 case (0xa4>>2): /* ST.W */
 772                         error = misaligned_store(regs, opcode, 1, 1);
 773                         break;
 774                 case (0xa8>>2): /* ST.L */
 775                         error = misaligned_store(regs, opcode, 1, 2);
 776                         break;
 777                 case (0xac>>2): /* ST.Q */
 778                         error = misaligned_store(regs, opcode, 1, 3);
 779                         break;
 780
 781                 case (0x40>>2): /* indexed loads */
 782                         switch (minor) {
 783                                 case 0x1: /* LDX.W */
 784                                         error = misaligned_load(regs, opcode, 0, 1, 1);
 785                                         break;
 786                                 case 0x5: /* LDX.UW */
 787                                         error = misaligned_load(regs, opcode, 0, 1, 0);
 788                                         break;
 789                                 case 0x2: /* LDX.L */
 790                                         error = misaligned_load(regs, opcode, 0, 2, 1);
 791                                         break;
 792                                 case 0x3: /* LDX.Q */
 793                                         error = misaligned_load(regs, opcode, 0, 3, 0);
 794                                         break;
 795                                 default:
 796                                         error = -1;
 797                                         break;
 798                         }
 799                         break;
 800
 801                 case (0x60>>2): /* indexed stores */
 802                         switch (minor) {
 803                                 case 0x1: /* STX.W */
 804                                         error = misaligned_store(regs, opcode, 0, 1);
 805                                         break;
 806                                 case 0x2: /* STX.L */
 807                                         error = misaligned_store(regs, opcode, 0, 2);
 808                                         break;
 809                                 case 0x3: /* STX.Q */
 810                                         error = misaligned_store(regs, opcode, 0, 3);
 811                                         break;
 812                                 default:
 813                                         error = -1;
 814                                         break;
 815                         }
 816                         break;
 817
 818                 case (0x94>>2): /* FLD.S */
 819                         error = misaligned_fpu_load(regs, opcode, 1, 2, 0);
 820                         break;
 821                 case (0x98>>2): /* FLD.P */
 822                         error = misaligned_fpu_load(regs, opcode, 1, 3, 1);
 823                         break;
 824                 case (0x9c>>2): /* FLD.D */
 825                         error = misaligned_fpu_load(regs, opcode, 1, 3, 0);
 826                         break;
 827                 case (0x1c>>2): /* floating indexed loads */
 828                         switch (minor) {
 829                         case 0x8: /* FLDX.S */
 830                                 error = misaligned_fpu_load(regs, opcode, 0, 2, 0);
 831                                 break;
 832                         case 0xd: /* FLDX.P */
 833                                 error = misaligned_fpu_load(regs, opcode, 0, 3, 1);
 834                                 break;
 835                         case 0x9: /* FLDX.D */
 836                                 error = misaligned_fpu_load(regs, opcode, 0, 3, 0);
 837                                 break;
 838                         default:
 839                                 error = -1;
 840                                 break;
 841                         }
 842                         break;
 843                 case (0xb4>>2): /* FLD.S */
 844                         error = misaligned_fpu_store(regs, opcode, 1, 2, 0);
 845                         break;
 846                 case (0xb8>>2): /* FLD.P */
 847                         error = misaligned_fpu_store(regs, opcode, 1, 3, 1);
 848                         break;
 849                 case (0xbc>>2): /* FLD.D */
 850                         error = misaligned_fpu_store(regs, opcode, 1, 3, 0);
 851                         break;
 852                 case (0x3c>>2): /* floating indexed stores */
 853                         switch (minor) {
 854                         case 0x8: /* FSTX.S */
 855                                 error = misaligned_fpu_store(regs, opcode, 0, 2, 0);
 856                                 break;
 857                         case 0xd: /* FSTX.P */
 858                                 error = misaligned_fpu_store(regs, opcode, 0, 3, 1);
 859                                 break;
 860                         case 0x9: /* FSTX.D */
 861                                 error = misaligned_fpu_store(regs, opcode, 0, 3, 0);
 862                                 break;
 863                         default:
 864                                 error = -1;
 865                                 break;
 866                         }
 867                         break;
 868
 869                 default:
 870                         /* Fault */
 871                         error = -1;
 872                         break;
 873         }
 874
 875         if (error < 0) {
 876                 return error;
 877         } else {
 878                 regs->pc += 4; /* Skip the instruction that's just been emulated */
 879                 return 0;
 880         }
 881
 882 }
 883
 884 static ctl_table unaligned_table[] = {
 885         {
 886                 .procname       = "kernel_reports",
 887                 .data           = &kernel_mode_unaligned_fixup_count,
 888                 .maxlen         = sizeof(int),
 889                 .mode           = 0644,
 890                 .proc_handler   = proc_dointvec
 891         },
 892         {
 893                 .procname       = "user_reports",
 894                 .data           = &user_mode_unaligned_fixup_count,
 895                 .maxlen         = sizeof(int),
 896                 .mode           = 0644,
 897                 .proc_handler   = proc_dointvec
 898         },
 899         {
 900                 .procname       = "user_enable",
 901                 .data           = &user_mode_unaligned_fixup_enable,
 902                 .maxlen         = sizeof(int),
 903                 .mode           = 0644,
 904                 .proc_handler   = proc_dointvec},
 905         {}
 906 };
 907
 908 static ctl_table unaligned_root[] = {
 909         {
 910                 .procname       = "unaligned_fixup",
 911                 .mode           = 0555,
 912                 .child          = unaligned_table
 913         },
 914         {}
 915 };
 916
 917 static ctl_table sh64_root[] = {
 918         {
 919                 .procname       = "sh64",
 920                 .mode           = 0555,
 921                 .child          = unaligned_root
 922         },
 923         {}
 924 };
 925 static struct ctl_table_header *sysctl_header;
 926 static int __init init_sysctl(void)
 927 {
 928         sysctl_header = register_sysctl_table(sh64_root);
 929         return 0;
 930 }
 931
 932 __initcall(init_sysctl);
 933
 934
 935 asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
 936 {
 937         u64 peek_real_address_q(u64 addr);
 938         u64 poke_real_address_q(u64 addr, u64 val);
 939         unsigned long long DM_EXP_CAUSE_PHY = 0x0c100010;
 940         unsigned long long exp_cause;
 941         /* It's not worth ioremapping the debug module registers for the amount
 942            of access we make to them - just go direct to their physical
 943            addresses. */
 944         exp_cause = peek_real_address_q(DM_EXP_CAUSE_PHY);
 945         if (exp_cause & ~4) {
 946                 printk("DM.EXP_CAUSE had unexpected bits set (=%08lx)\n",
 947                         (unsigned long)(exp_cause & 0xffffffff));
 948         }
 949         show_state();
 950         /* Clear all DEBUGINT causes */
 951         poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);
 952 }
 953
 954 void __cpuinit per_cpu_trap_init(void)
 955 {
 956         /* Nothing to do for now, VBR initialization later. */
 957 }