2 * Pinmuxed GPIO support for SuperH.
4 * Copyright (C) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/errno.h>
12 #include <linux/kernel.h>
13 #include <linux/list.h>
14 #include <linux/module.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
18 #include <linux/irq.h>
19 #include <linux/bitops.h>
20 #include <linux/gpio.h>
22 static struct pinmux_info *registered_gpio;
24 static struct pinmux_info *gpio_controller(unsigned gpio)
29 if (gpio < registered_gpio->first_gpio)
32 if (gpio > registered_gpio->last_gpio)
35 return registered_gpio;
38 static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
40 if (enum_id < r->begin)
49 static int gpio_read_reg(unsigned long reg, unsigned long reg_width,
50 unsigned long field_width, unsigned long in_pos)
52 unsigned long data, mask, pos;
55 mask = (1 << field_width) - 1;
56 pos = reg_width - ((in_pos + 1) * field_width);
59 pr_info("read_reg: addr = %lx, pos = %ld, "
60 "r_width = %ld, f_width = %ld\n",
61 reg, pos, reg_width, field_width);
76 return (data >> pos) & mask;
79 static void gpio_write_reg(unsigned long reg, unsigned long reg_width,
80 unsigned long field_width, unsigned long in_pos,
83 unsigned long mask, pos;
85 mask = (1 << field_width) - 1;
86 pos = reg_width - ((in_pos + 1) * field_width);
89 pr_info("write_reg addr = %lx, value = %ld, pos = %ld, "
90 "r_width = %ld, f_width = %ld\n",
91 reg, value, pos, reg_width, field_width);
94 mask = ~(mask << pos);
99 ctrl_outb((ctrl_inb(reg) & mask) | value, reg);
102 ctrl_outw((ctrl_inw(reg) & mask) | value, reg);
105 ctrl_outl((ctrl_inl(reg) & mask) | value, reg);
110 static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
112 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
113 struct pinmux_data_reg *data_reg;
116 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
121 data_reg = gpioc->data_regs + k;
123 if (!data_reg->reg_width)
126 for (n = 0; n < data_reg->reg_width; n++) {
127 if (data_reg->enum_ids[n] == gpiop->enum_id) {
128 gpiop->flags &= ~PINMUX_FLAG_DREG;
129 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
130 gpiop->flags &= ~PINMUX_FLAG_DBIT;
131 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
143 static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
144 struct pinmux_data_reg **drp, int *bitp)
146 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
149 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
152 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
153 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
154 *drp = gpioc->data_regs + k;
159 static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
160 struct pinmux_cfg_reg **crp, int *indexp,
161 unsigned long **cntp)
163 struct pinmux_cfg_reg *config_reg;
164 unsigned long r_width, f_width;
169 config_reg = gpioc->cfg_regs + k;
171 r_width = config_reg->reg_width;
172 f_width = config_reg->field_width;
176 for (n = 0; n < (r_width / f_width) * 1 << f_width; n++) {
177 if (config_reg->enum_ids[n] == enum_id) {
180 *cntp = &config_reg->cnt[n / (1 << f_width)];
190 static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
191 int pos, pinmux_enum_t *enum_idp)
193 pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
194 pinmux_enum_t *data = gpioc->gpio_data;
197 if (!enum_in_range(enum_id, &gpioc->data)) {
198 if (!enum_in_range(enum_id, &gpioc->mark)) {
199 pr_err("non data/mark enum_id for gpio %d\n", gpio);
205 *enum_idp = data[pos + 1];
209 for (k = 0; k < gpioc->gpio_data_size; k++) {
210 if (data[k] == enum_id) {
211 *enum_idp = data[k + 1];
216 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
220 static void write_config_reg(struct pinmux_info *gpioc,
221 struct pinmux_cfg_reg *crp,
224 unsigned long ncomb, pos, value;
226 ncomb = 1 << crp->field_width;
228 value = index % ncomb;
230 gpio_write_reg(crp->reg, crp->reg_width, crp->field_width, pos, value);
233 static int check_config_reg(struct pinmux_info *gpioc,
234 struct pinmux_cfg_reg *crp,
237 unsigned long ncomb, pos, value;
239 ncomb = 1 << crp->field_width;
241 value = index % ncomb;
243 if (gpio_read_reg(crp->reg, crp->reg_width,
244 crp->field_width, pos) == value)
250 enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
252 static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
253 int pinmux_type, int cfg_mode)
255 struct pinmux_cfg_reg *cr = NULL;
256 pinmux_enum_t enum_id;
257 struct pinmux_range *range;
258 int in_range, pos, index;
261 switch (pinmux_type) {
263 case PINMUX_TYPE_FUNCTION:
267 case PINMUX_TYPE_OUTPUT:
268 range = &gpioc->output;
271 case PINMUX_TYPE_INPUT:
272 range = &gpioc->input;
275 case PINMUX_TYPE_INPUT_PULLUP:
276 range = &gpioc->input_pu;
279 case PINMUX_TYPE_INPUT_PULLDOWN:
280 range = &gpioc->input_pd;
291 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
298 in_range = enum_in_range(enum_id, &gpioc->function);
299 if (!in_range && range) {
300 in_range = enum_in_range(enum_id, range);
302 if (in_range && enum_id == range->force)
309 if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
313 case GPIO_CFG_DRYRUN:
314 if (!*cntp || !check_config_reg(gpioc, cr, index))
319 write_config_reg(gpioc, cr, index);
334 static DEFINE_SPINLOCK(gpio_lock);
336 int __gpio_request(unsigned gpio)
338 struct pinmux_info *gpioc = gpio_controller(gpio);
339 struct pinmux_data_reg *dummy;
341 int i, ret, pinmux_type;
348 spin_lock_irqsave(&gpio_lock, flags);
350 if ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
353 /* setup pin function here if no data is associated with pin */
355 if (get_data_reg(gpioc, gpio, &dummy, &i) != 0)
356 pinmux_type = PINMUX_TYPE_FUNCTION;
358 pinmux_type = PINMUX_TYPE_GPIO;
360 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
361 if (pinmux_config_gpio(gpioc, gpio,
363 GPIO_CFG_DRYRUN) != 0)
366 if (pinmux_config_gpio(gpioc, gpio,
372 gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
373 gpioc->gpios[gpio].flags |= pinmux_type;
377 spin_unlock_irqrestore(&gpio_lock, flags);
381 EXPORT_SYMBOL(__gpio_request);
383 void gpio_free(unsigned gpio)
385 struct pinmux_info *gpioc = gpio_controller(gpio);
392 spin_lock_irqsave(&gpio_lock, flags);
394 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
395 pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
396 gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
397 gpioc->gpios[gpio].flags |= PINMUX_TYPE_NONE;
399 spin_unlock_irqrestore(&gpio_lock, flags);
401 EXPORT_SYMBOL(gpio_free);
403 static int pinmux_direction(struct pinmux_info *gpioc,
404 unsigned gpio, int new_pinmux_type)
412 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
414 switch (pinmux_type) {
415 case PINMUX_TYPE_GPIO:
417 case PINMUX_TYPE_OUTPUT:
418 case PINMUX_TYPE_INPUT:
419 case PINMUX_TYPE_INPUT_PULLUP:
420 case PINMUX_TYPE_INPUT_PULLDOWN:
421 pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
427 if (pinmux_config_gpio(gpioc, gpio,
429 GPIO_CFG_DRYRUN) != 0)
432 if (pinmux_config_gpio(gpioc, gpio,
437 gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
438 gpioc->gpios[gpio].flags |= new_pinmux_type;
445 int gpio_direction_input(unsigned gpio)
447 struct pinmux_info *gpioc = gpio_controller(gpio);
451 spin_lock_irqsave(&gpio_lock, flags);
452 ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_INPUT);
453 spin_unlock_irqrestore(&gpio_lock, flags);
457 EXPORT_SYMBOL(gpio_direction_input);
459 static void __gpio_set_value(struct pinmux_info *gpioc,
460 unsigned gpio, int value)
462 struct pinmux_data_reg *dr = NULL;
465 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
468 gpio_write_reg(dr->reg, dr->reg_width, 1, bit, !!value);
471 int gpio_direction_output(unsigned gpio, int value)
473 struct pinmux_info *gpioc = gpio_controller(gpio);
477 spin_lock_irqsave(&gpio_lock, flags);
478 __gpio_set_value(gpioc, gpio, value);
479 ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_OUTPUT);
480 spin_unlock_irqrestore(&gpio_lock, flags);
484 EXPORT_SYMBOL(gpio_direction_output);
486 static int __gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
488 struct pinmux_data_reg *dr = NULL;
491 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0) {
496 return gpio_read_reg(dr->reg, dr->reg_width, 1, bit);
499 int gpio_get_value(unsigned gpio)
501 return __gpio_get_value(gpio_controller(gpio), gpio);
503 EXPORT_SYMBOL(gpio_get_value);
505 void gpio_set_value(unsigned gpio, int value)
507 struct pinmux_info *gpioc = gpio_controller(gpio);
510 spin_lock_irqsave(&gpio_lock, flags);
511 __gpio_set_value(gpioc, gpio, value);
512 spin_unlock_irqrestore(&gpio_lock, flags);
514 EXPORT_SYMBOL(gpio_set_value);
516 int register_pinmux(struct pinmux_info *pip)
520 registered_gpio = pip;
521 pr_info("pinmux: %s handling gpio %d -> %d\n",
522 pip->name, pip->first_gpio, pip->last_gpio);
524 for (k = pip->first_gpio; k <= pip->last_gpio; k++)
525 setup_data_reg(pip, k);