Pileus Git - ~andy/linux/blob - arch/sh/kernel/cpu/sh4a/clock-sh7724.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
   3  *
   4  * SH7724 clock framework support
   5  *
   6  * Copyright (C) 2009 Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <linux/clkdev.h>
  26 #include <linux/sh_clk.h>
  27 #include <asm/clock.h>
  28 #include <cpu/sh7724.h>
  29
  30 /* SH7724 registers */
  31 #define FRQCRA          0xa4150000
  32 #define FRQCRB          0xa4150004
  33 #define VCLKCR          0xa4150048
  34 #define FCLKACR         0xa4150008
  35 #define FCLKBCR         0xa415000c
  36 #define IRDACLKCR       0xa4150018
  37 #define PLLCR           0xa4150024
  38 #define MSTPCR0         0xa4150030
  39 #define MSTPCR1         0xa4150034
  40 #define MSTPCR2         0xa4150038
  41 #define SPUCLKCR        0xa415003c
  42 #define FLLFRQ          0xa4150050
  43 #define LSTATS          0xa4150060
  44
  45 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
  46 static struct clk r_clk = {
  47         .rate           = 32768,
  48 };
  49
  50 /*
  51  * Default rate for the root input clock, reset this with clk_set_rate()
  52  * from the platform code.
  53  */
  54 static struct clk extal_clk = {
  55         .rate           = 33333333,
  56 };
  57
  58 /* The fll multiplies the 32khz r_clk, may be used instead of extal */
  59 static unsigned long fll_recalc(struct clk *clk)
  60 {
  61         unsigned long mult = 0;
  62         unsigned long div = 1;
  63
  64         if (__raw_readl(PLLCR) & 0x1000)
  65                 mult = __raw_readl(FLLFRQ) & 0x3ff;
  66
  67         if (__raw_readl(FLLFRQ) & 0x4000)
  68                 div = 2;
  69
  70         return (clk->parent->rate * mult) / div;
  71 }
  72
  73 static struct clk_ops fll_clk_ops = {
  74         .recalc         = fll_recalc,
  75 };
  76
  77 static struct clk fll_clk = {
  78         .ops            = &fll_clk_ops,
  79         .parent         = &r_clk,
  80         .flags          = CLK_ENABLE_ON_INIT,
  81 };
  82
  83 static unsigned long pll_recalc(struct clk *clk)
  84 {
  85         unsigned long mult = 1;
  86
  87         if (__raw_readl(PLLCR) & 0x4000)
  88                 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
  89
  90         return clk->parent->rate * mult;
  91 }
  92
  93 static struct clk_ops pll_clk_ops = {
  94         .recalc         = pll_recalc,
  95 };
  96
  97 static struct clk pll_clk = {
  98         .ops            = &pll_clk_ops,
  99         .flags          = CLK_ENABLE_ON_INIT,
 100 };
 101
 102 /* A fixed divide-by-3 block use by the div6 clocks */
 103 static unsigned long div3_recalc(struct clk *clk)
 104 {
 105         return clk->parent->rate / 3;
 106 }
 107
 108 static struct clk_ops div3_clk_ops = {
 109         .recalc         = div3_recalc,
 110 };
 111
 112 static struct clk div3_clk = {
 113         .ops            = &div3_clk_ops,
 114         .parent         = &pll_clk,
 115 };
 116
 117 /* External input clock (pin name: FSIMCKA/FSIMCKB ) */
 118 struct clk sh7724_fsimcka_clk = {
 119 };
 120
 121 struct clk sh7724_fsimckb_clk = {
 122 };
 123
 124 static struct clk *main_clks[] = {
 125         &r_clk,
 126         &extal_clk,
 127         &fll_clk,
 128         &pll_clk,
 129         &div3_clk,
 130         &sh7724_fsimcka_clk,
 131         &sh7724_fsimckb_clk,
 132 };
 133
 134 static void div4_kick(struct clk *clk)
 135 {
 136         unsigned long value;
 137
 138         /* set KICK bit in FRQCRA to update hardware setting */
 139         value = __raw_readl(FRQCRA);
 140         value |= (1 << 31);
 141         __raw_writel(value, FRQCRA);
 142 }
 143
 144 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
 145
 146 static struct clk_div_mult_table div4_div_mult_table = {
 147         .divisors = divisors,
 148         .nr_divisors = ARRAY_SIZE(divisors),
 149 };
 150
 151 static struct clk_div4_table div4_table = {
 152         .div_mult_table = &div4_div_mult_table,
 153         .kick = div4_kick,
 154 };
 155
 156 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
 157
 158 #define DIV4(_reg, _bit, _mask, _flags) \
 159   SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 160
 161 struct clk div4_clks[DIV4_NR] = {
 162         [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
 163         [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
 164         [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
 165         [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
 166         [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
 167 };
 168
 169 enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR };
 170
 171 static struct clk div6_clks[DIV6_NR] = {
 172         [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
 173         [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
 174         [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
 175 };
 176
 177 enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR };
 178
 179 /* Indices are important - they are the actual src selecting values */
 180 static struct clk *fclkacr_parent[] = {
 181         [0] = &div3_clk,
 182         [1] = NULL,
 183         [2] = &sh7724_fsimcka_clk,
 184         [3] = NULL,
 185 };
 186
 187 static struct clk *fclkbcr_parent[] = {
 188         [0] = &div3_clk,
 189         [1] = NULL,
 190         [2] = &sh7724_fsimckb_clk,
 191         [3] = NULL,
 192 };
 193
 194 static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
 195         [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0,
 196                                       fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
 197         [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0,
 198                                       fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
 199 };
 200
 201 static struct clk mstp_clks[HWBLK_NR] = {
 202         [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I],     MSTPCR0, 31, CLK_ENABLE_ON_INIT),
 203         [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I],      MSTPCR0, 30, CLK_ENABLE_ON_INIT),
 204         [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I],      MSTPCR0, 29, CLK_ENABLE_ON_INIT),
 205         [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR0, 28, CLK_ENABLE_ON_INIT),
 206         [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I],   MSTPCR0, 27, CLK_ENABLE_ON_INIT),
 207         [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH],    MSTPCR0, 26, CLK_ENABLE_ON_INIT),
 208         [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I],     MSTPCR0, 24, CLK_ENABLE_ON_INIT),
 209         [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR0, 22, CLK_ENABLE_ON_INIT),
 210         [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR0, 21, 0),
 211         [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
 212         [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR0, 19, 0),
 213         [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I],     MSTPCR0, 17, 0),
 214         [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR0, 15, 0),
 215         [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk,                 MSTPCR0, 14, 0),
 216         [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk,                MSTPCR0, 13, 0),
 217         [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR0, 12, 0),
 218         [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR0, 10, 0),
 219         [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P],   MSTPCR0, 9, 0),
 220         [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P],   MSTPCR0, 8, 0),
 221         [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P],   MSTPCR0, 7, 0),
 222         [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR0, 6, 0),
 223         [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR0, 5, 0),
 224         [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR0, 4, 0),
 225         [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR0, 2, 0),
 226         [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR0, 1, 0),
 227
 228         [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk,               MSTPCR1, 12, 0),
 229         [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk,                 MSTPCR1, 11, 0),
 230         [HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR1, 9, 0),
 231         [HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR1, 8, 0),
 232
 233         [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B],     MSTPCR2, 29, 0),
 234         [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR2, 28, 0),
 235         [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR2, 26, 0),
 236         [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B],     MSTPCR2, 25, 0),
 237         [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR2, 24, 0),
 238         [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 22, 0),
 239         [HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 21, 0),
 240         [HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 20, 0),
 241         [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B],     MSTPCR2, 19, 0),
 242         [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR2, 18, 0),
 243         [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR2, 17, 0),
 244         [HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 15, 0),
 245         [HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 13, 0),
 246         [HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 12, 0),
 247         [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0),
 248         [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B],     MSTPCR2, 9, 0),
 249         [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B],     MSTPCR2, 6, 0),
 250         [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B],     MSTPCR2, 5, 0),
 251         [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 4, 0),
 252         [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 3, 0),
 253         [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 2, 0),
 254         [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B],     MSTPCR2, 1, 0),
 255         [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 0, 0),
 256 };
 257
 258 static struct clk_lookup lookups[] = {
 259         /* main clocks */
 260         CLKDEV_CON_ID("rclk", &r_clk),
 261         CLKDEV_CON_ID("extal", &extal_clk),
 262         CLKDEV_CON_ID("fll_clk", &fll_clk),
 263         CLKDEV_CON_ID("pll_clk", &pll_clk),
 264         CLKDEV_CON_ID("div3_clk", &div3_clk),
 265
 266         /* DIV4 clocks */
 267         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 268         CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
 269         CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
 270         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 271         CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
 272
 273         /* DIV6 clocks */
 274         CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
 275         CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]),
 276         CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]),
 277         CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
 278         CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
 279
 280         /* MSTP clocks */
 281         CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
 282         CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
 283         CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
 284         CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
 285         CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
 286         CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
 287         CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
 288         CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
 289         CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
 290         CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
 291         CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
 292         CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
 293
 294         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU0]),
 295         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU0]),
 296         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU0]),
 297         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
 298
 299         CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
 300         CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
 301         CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),
 302
 303         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
 304         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
 305         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
 306         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
 307         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
 308         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
 309         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
 310         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
 311
 312         CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]),
 313         CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]),
 314         CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
 315         CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
 316         CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]),
 317         CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]),
 318         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[HWBLK_MMC]),
 319         CLKDEV_DEV_ID("sh-eth.0", &mstp_clks[HWBLK_ETHER]),
 320         CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
 321         CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
 322         CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
 323         CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
 324         CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
 325         CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
 326         CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
 327         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]),
 328         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]),
 329         CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
 330         CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[HWBLK_CEU1]),
 331         CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
 332         CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
 333         CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
 334         CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
 335         CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
 336         CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
 337         CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU0]),
 338         CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
 339         CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
 340         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
 341 };
 342
 343 int __init arch_clk_init(void)
 344 {
 345         int k, ret = 0;
 346
 347         /* autodetect extal or fll configuration */
 348         if (__raw_readl(PLLCR) & 0x1000)
 349                 pll_clk.parent = &fll_clk;
 350         else
 351                 pll_clk.parent = &extal_clk;
 352
 353         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 354                 ret = clk_register(main_clks[k]);
 355
 356         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 357
 358         if (!ret)
 359                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 360
 361         if (!ret)
 362                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 363
 364         if (!ret)
 365                 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
 366
 367         if (!ret)
 368                 ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
 369
 370         return ret;
 371 }