2 * Low-Level PCI Express Support for the SH7786
4 * Copyright (C) 2009 - 2010 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
16 #include "pcie-sh7786.h"
17 #include <asm/sizes.h>
19 struct sh7786_pcie_port {
20 struct pci_channel *hose;
26 static struct sh7786_pcie_port *sh7786_pcie_ports;
27 static unsigned int nr_ports;
29 static struct sh7786_pcie_hwops {
30 int (*core_init)(void);
31 int (*port_init_hw)(struct sh7786_pcie_port *port);
34 static struct resource sh7786_pci0_resources[] = {
38 .end = 0xfd000000 + SZ_8M - 1,
39 .flags = IORESOURCE_IO,
41 .name = "PCIe0 MEM 0",
43 .end = 0xc0000000 + SZ_512M - 1,
44 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
46 .name = "PCIe0 MEM 1",
48 .end = 0x10000000 + SZ_64M - 1,
49 .flags = IORESOURCE_MEM,
51 .name = "PCIe0 MEM 2",
53 .end = 0xfe100000 + SZ_1M - 1,
57 static struct resource sh7786_pci1_resources[] = {
61 .end = 0xfd800000 + SZ_8M - 1,
62 .flags = IORESOURCE_IO,
64 .name = "PCIe1 MEM 0",
66 .end = 0xa0000000 + SZ_512M - 1,
67 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
69 .name = "PCIe1 MEM 1",
71 .end = 0x30000000 + SZ_256M - 1,
72 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
74 .name = "PCIe1 MEM 2",
76 .end = 0xfe300000 + SZ_1M - 1,
80 static struct resource sh7786_pci2_resources[] = {
84 .end = 0xfc800000 + SZ_4M - 1,
86 .name = "PCIe2 MEM 0",
88 .end = 0x80000000 + SZ_512M - 1,
89 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
91 .name = "PCIe2 MEM 1",
93 .end = 0x20000000 + SZ_256M - 1,
94 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
96 .name = "PCIe2 MEM 2",
98 .end = 0xfcd00000 + SZ_1M - 1,
102 extern struct pci_ops sh7786_pci_ops;
104 #define DEFINE_CONTROLLER(start, idx) \
106 .pci_ops = &sh7786_pci_ops, \
107 .resources = sh7786_pci##idx##_resources, \
108 .nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \
114 static struct pci_channel sh7786_pci_channels[] = {
115 DEFINE_CONTROLLER(0xfe000000, 0),
116 DEFINE_CONTROLLER(0xfe200000, 1),
117 DEFINE_CONTROLLER(0xfcc00000, 2),
120 static int phy_wait_for_ack(struct pci_channel *chan)
122 unsigned int timeout = 100;
125 if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK))
134 static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
136 unsigned int timeout = 100;
139 if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask)
148 static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
149 unsigned int lane, unsigned int data)
151 unsigned long phyaddr;
153 phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +
154 ((addr & 0xff) << BITS_ADR);
157 pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
158 pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
160 phy_wait_for_ack(chan);
163 pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
164 pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
166 phy_wait_for_ack(chan);
169 static int phy_init(struct pci_channel *chan)
172 unsigned int timeout = 100;
175 ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
176 ctrl |= (1 << BITS_CKE);
177 pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
179 /* Initialize the phy */
180 phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
181 phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
182 phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00);
183 phy_write_reg(chan, 0x65, 0xf, 0x09070907);
184 phy_write_reg(chan, 0x66, 0xf, 0x00000010);
185 phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
186 phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
187 phy_write_reg(chan, 0xb0, 0xf, 0x00000610);
189 /* Deassert Standby */
190 phy_write_reg(chan, 0x67, 0x1, 0x00000400);
193 ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
194 ctrl &= ~(1 << BITS_CKE);
195 pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
198 if (pci_read_reg(chan, SH4A_PCIEPHYSR))
207 static void pcie_reset(struct sh7786_pcie_port *port)
209 struct pci_channel *chan = port->hose;
211 pci_write_reg(chan, 1, SH4A_PCIESRSTR);
212 pci_write_reg(chan, 0, SH4A_PCIETCTLR);
213 pci_write_reg(chan, 0, SH4A_PCIESRSTR);
214 pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
217 static int pcie_init(struct sh7786_pcie_port *port)
219 struct pci_channel *chan = port->hose;
225 /* Begin initialization */
228 /* Initialize as type1. */
229 data = pci_read_reg(chan, SH4A_PCIEPCICONF3);
230 data &= ~(0x7f << 16);
231 data |= PCI_HEADER_TYPE_BRIDGE << 16;
232 pci_write_reg(chan, data, SH4A_PCIEPCICONF3);
234 /* Initialize default capabilities. */
235 data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
236 data &= ~(PCI_EXP_FLAGS_TYPE << 16);
239 data |= PCI_EXP_TYPE_ENDPOINT << 20;
241 data |= PCI_EXP_TYPE_ROOT_PORT << 20;
243 data |= PCI_CAP_ID_EXP;
244 pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
246 /* Enable data link layer active state reporting */
247 pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);
249 /* Enable extended sync and ASPM L0s support */
250 data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
251 data &= ~PCI_EXP_LNKCTL_ASPMC;
252 data |= PCI_EXP_LNKCTL_ES | 1;
253 pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
255 /* Write out the physical slot number */
256 data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
257 data &= ~PCI_EXP_SLTCAP_PSN;
258 data |= (port->index + 1) << 19;
259 pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
261 /* Set the completion timer timeout to the maximum 32ms. */
262 data = pci_read_reg(chan, SH4A_PCIETLCTLR);
265 pci_write_reg(chan, data, SH4A_PCIETLCTLR);
268 * Set fast training sequences to the maximum 255,
269 * and enable MAC data scrambling.
271 data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
272 data &= ~PCIEMACCTLR_SCR_DIS;
273 data |= (0xff << 16);
274 pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
276 memphys = __pa(memory_start);
277 memsize = roundup_pow_of_two(memory_end - memory_start);
280 * If there's more than 512MB of memory, we need to roll over to
283 if (memsize > SZ_512M) {
284 __raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
285 __raw_writel(((memsize - SZ_512M) - SZ_256) | 1,
286 chan->reg_base + SH4A_PCIELAMR1);
290 * Otherwise just zero it out and disable it.
292 __raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
293 __raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
297 * LAR0/LAMR0 covers up to the first 512MB, which is enough to
298 * cover all of lowmem on most platforms.
300 __raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
301 __raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);
303 __raw_writel(memphys, chan->reg_base + SH4A_PCIEPCICONF4);
304 __raw_writel(0, chan->reg_base + SH4A_PCIEPCICONF5);
306 /* Finish initialization */
307 data = pci_read_reg(chan, SH4A_PCIETCTLR);
309 pci_write_reg(chan, data, SH4A_PCIETCTLR);
311 /* Enable DL_Active Interrupt generation */
312 data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
313 data |= PCIEDLINTENR_DLL_ACT_ENABLE;
314 pci_write_reg(chan, data, SH4A_PCIEDLINTENR);
316 /* Disable MAC data scrambling. */
317 data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
318 data |= PCIEMACCTLR_SCR_DIS | (0xff << 16);
319 pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
321 ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);
322 if (unlikely(ret != 0))
325 data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
326 data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
327 data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
328 (PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST) << 16;
329 pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
331 pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
332 pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);
336 data = pci_read_reg(chan, SH4A_PCIEMACSR);
337 printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
338 port->index, (data >> 20) & 0x3f);
341 for (i = 0; i < chan->nr_resources; i++) {
342 struct resource *res = chan->resources + i;
343 resource_size_t size;
346 pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(i));
348 size = resource_size(res);
351 * The PAMR mask is calculated in units of 256kB, which
352 * keeps things pretty simple.
354 __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
355 chan->reg_base + SH4A_PCIEPAMR(i));
357 pci_write_reg(chan, res->start, SH4A_PCIEPARL(i));
358 pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i));
360 enable_mask = MASK_PARE;
361 if (res->flags & IORESOURCE_IO)
362 enable_mask |= MASK_SPC;
364 pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(i));
370 int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
375 static int sh7786_pcie_core_init(void)
377 /* Return the number of ports */
378 return test_mode_pin(MODE_PIN12) ? 3 : 2;
381 static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
385 ret = phy_init(port->hose);
386 if (unlikely(ret < 0))
390 * Check if we are configured in endpoint or root complex mode,
391 * this is a fixed pin setting that applies to all PCIe ports.
393 port->endpoint = test_mode_pin(MODE_PIN11);
395 ret = pcie_init(port);
396 if (unlikely(ret < 0))
399 return register_pci_controller(port->hose);
402 static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
403 .core_init = sh7786_pcie_core_init,
404 .port_init_hw = sh7786_pcie_init_hw,
407 static int __init sh7786_pcie_init(void)
411 printk(KERN_NOTICE "PCI: Starting intialization.\n");
413 sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops;
415 nr_ports = sh7786_pcie_hwops->core_init();
416 BUG_ON(nr_ports > ARRAY_SIZE(sh7786_pci_channels));
418 if (unlikely(nr_ports == 0))
421 sh7786_pcie_ports = kzalloc(nr_ports * sizeof(struct sh7786_pcie_port),
423 if (unlikely(!sh7786_pcie_ports))
426 printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
428 for (i = 0; i < nr_ports; i++) {
429 struct sh7786_pcie_port *port = sh7786_pcie_ports + i;
432 port->hose = sh7786_pci_channels + i;
433 port->hose->io_map_base = port->hose->resources[0].start;
435 ret |= sh7786_pcie_hwops->port_init_hw(port);
443 arch_initcall(sh7786_pcie_init);