2 * Low-Level PCI Express Support for the SH7786
4 * Copyright (C) 2009 - 2010 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
16 #include "pcie-sh7786.h"
17 #include <asm/sizes.h>
19 struct sh7786_pcie_port {
20 struct pci_channel *hose;
26 static struct sh7786_pcie_port *sh7786_pcie_ports;
27 static unsigned int nr_ports;
29 static struct sh7786_pcie_hwops {
30 int (*core_init)(void);
31 int (*port_init_hw)(struct sh7786_pcie_port *port);
34 static struct resource sh7786_pci0_resources[] = {
38 .end = 0xfd000000 + SZ_8M - 1,
39 .flags = IORESOURCE_IO,
41 .name = "PCIe0 MEM 0",
43 .end = 0xc0000000 + SZ_512M - 1,
44 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
46 .name = "PCIe0 MEM 1",
48 .end = 0x10000000 + SZ_64M - 1,
49 .flags = IORESOURCE_MEM,
51 .name = "PCIe0 MEM 2",
53 .end = 0xfe100000 + SZ_1M - 1,
54 .flags = IORESOURCE_MEM,
58 static struct resource sh7786_pci1_resources[] = {
62 .end = 0xfd800000 + SZ_8M - 1,
63 .flags = IORESOURCE_IO,
65 .name = "PCIe1 MEM 0",
67 .end = 0xa0000000 + SZ_512M - 1,
68 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
70 .name = "PCIe1 MEM 1",
72 .end = 0x30000000 + SZ_256M - 1,
73 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
75 .name = "PCIe1 MEM 2",
77 .end = 0xfe300000 + SZ_1M - 1,
78 .flags = IORESOURCE_MEM,
82 static struct resource sh7786_pci2_resources[] = {
86 .end = 0xfc800000 + SZ_4M - 1,
87 .flags = IORESOURCE_IO,
89 .name = "PCIe2 MEM 0",
91 .end = 0x80000000 + SZ_512M - 1,
92 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
94 .name = "PCIe2 MEM 1",
96 .end = 0x20000000 + SZ_256M - 1,
97 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
99 .name = "PCIe2 MEM 2",
101 .end = 0xfcd00000 + SZ_1M - 1,
102 .flags = IORESOURCE_MEM,
106 extern struct pci_ops sh7786_pci_ops;
108 #define DEFINE_CONTROLLER(start, idx) \
110 .pci_ops = &sh7786_pci_ops, \
111 .resources = sh7786_pci##idx##_resources, \
112 .nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \
118 static struct pci_channel sh7786_pci_channels[] = {
119 DEFINE_CONTROLLER(0xfe000000, 0),
120 DEFINE_CONTROLLER(0xfe200000, 1),
121 DEFINE_CONTROLLER(0xfcc00000, 2),
124 static int phy_wait_for_ack(struct pci_channel *chan)
126 unsigned int timeout = 100;
129 if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK))
138 static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
140 unsigned int timeout = 100;
143 if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask)
152 static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
153 unsigned int lane, unsigned int data)
155 unsigned long phyaddr;
157 phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +
158 ((addr & 0xff) << BITS_ADR);
161 pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
162 pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
164 phy_wait_for_ack(chan);
167 pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
168 pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
170 phy_wait_for_ack(chan);
173 static int phy_init(struct pci_channel *chan)
176 unsigned int timeout = 100;
179 ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
180 ctrl |= (1 << BITS_CKE);
181 pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
183 /* Initialize the phy */
184 phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
185 phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
186 phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00);
187 phy_write_reg(chan, 0x65, 0xf, 0x09070907);
188 phy_write_reg(chan, 0x66, 0xf, 0x00000010);
189 phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
190 phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
191 phy_write_reg(chan, 0xb0, 0xf, 0x00000610);
193 /* Deassert Standby */
194 phy_write_reg(chan, 0x67, 0x1, 0x00000400);
197 ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
198 ctrl &= ~(1 << BITS_CKE);
199 pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
202 if (pci_read_reg(chan, SH4A_PCIEPHYSR))
211 static void pcie_reset(struct sh7786_pcie_port *port)
213 struct pci_channel *chan = port->hose;
215 pci_write_reg(chan, 1, SH4A_PCIESRSTR);
216 pci_write_reg(chan, 0, SH4A_PCIETCTLR);
217 pci_write_reg(chan, 0, SH4A_PCIESRSTR);
218 pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
221 static int pcie_init(struct sh7786_pcie_port *port)
223 struct pci_channel *chan = port->hose;
229 /* Begin initialization */
232 /* Initialize as type1. */
233 data = pci_read_reg(chan, SH4A_PCIEPCICONF3);
234 data &= ~(0x7f << 16);
235 data |= PCI_HEADER_TYPE_BRIDGE << 16;
236 pci_write_reg(chan, data, SH4A_PCIEPCICONF3);
238 /* Initialize default capabilities. */
239 data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
240 data &= ~(PCI_EXP_FLAGS_TYPE << 16);
243 data |= PCI_EXP_TYPE_ENDPOINT << 20;
245 data |= PCI_EXP_TYPE_ROOT_PORT << 20;
247 data |= PCI_CAP_ID_EXP;
248 pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
250 /* Enable data link layer active state reporting */
251 pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);
253 /* Enable extended sync and ASPM L0s support */
254 data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
255 data &= ~PCI_EXP_LNKCTL_ASPMC;
256 data |= PCI_EXP_LNKCTL_ES | 1;
257 pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
259 /* Write out the physical slot number */
260 data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
261 data &= ~PCI_EXP_SLTCAP_PSN;
262 data |= (port->index + 1) << 19;
263 pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
265 /* Set the completion timer timeout to the maximum 32ms. */
266 data = pci_read_reg(chan, SH4A_PCIETLCTLR);
269 pci_write_reg(chan, data, SH4A_PCIETLCTLR);
272 * Set fast training sequences to the maximum 255,
273 * and enable MAC data scrambling.
275 data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
276 data &= ~PCIEMACCTLR_SCR_DIS;
277 data |= (0xff << 16);
278 pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
280 memphys = __pa(memory_start);
281 memsize = roundup_pow_of_two(memory_end - memory_start);
284 * If there's more than 512MB of memory, we need to roll over to
287 if (memsize > SZ_512M) {
288 __raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
289 __raw_writel(((memsize - SZ_512M) - SZ_256) | 1,
290 chan->reg_base + SH4A_PCIELAMR1);
294 * Otherwise just zero it out and disable it.
296 __raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
297 __raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
301 * LAR0/LAMR0 covers up to the first 512MB, which is enough to
302 * cover all of lowmem on most platforms.
304 __raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
305 __raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);
307 __raw_writel(memphys, chan->reg_base + SH4A_PCIEPCICONF4);
308 __raw_writel(0, chan->reg_base + SH4A_PCIEPCICONF5);
310 /* Finish initialization */
311 data = pci_read_reg(chan, SH4A_PCIETCTLR);
313 pci_write_reg(chan, data, SH4A_PCIETCTLR);
315 /* Enable DL_Active Interrupt generation */
316 data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
317 data |= PCIEDLINTENR_DLL_ACT_ENABLE;
318 pci_write_reg(chan, data, SH4A_PCIEDLINTENR);
320 /* Disable MAC data scrambling. */
321 data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
322 data |= PCIEMACCTLR_SCR_DIS | (0xff << 16);
323 pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
325 ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);
326 if (unlikely(ret != 0))
329 data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
330 data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
331 data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
332 (PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST) << 16;
333 pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
335 pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
336 pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);
340 data = pci_read_reg(chan, SH4A_PCIEMACSR);
341 printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
342 port->index, (data >> 20) & 0x3f);
344 for (i = win = 0; i < chan->nr_resources; i++) {
345 struct resource *res = chan->resources + i;
346 resource_size_t size;
350 * We can't use the 32-bit mode windows in legacy 29-bit
351 * mode, so just skip them entirely.
353 if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
356 pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
358 size = resource_size(res);
361 * The PAMR mask is calculated in units of 256kB, which
362 * keeps things pretty simple.
364 __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
365 chan->reg_base + SH4A_PCIEPAMR(win));
367 pci_write_reg(chan, res->start, SH4A_PCIEPARL(win));
368 pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win));
370 enable_mask = MASK_PARE;
371 if (res->flags & IORESOURCE_IO)
372 enable_mask |= MASK_SPC;
374 pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win));
382 int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
387 static int sh7786_pcie_core_init(void)
389 /* Return the number of ports */
390 return test_mode_pin(MODE_PIN12) ? 3 : 2;
393 static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
397 ret = phy_init(port->hose);
398 if (unlikely(ret < 0))
402 * Check if we are configured in endpoint or root complex mode,
403 * this is a fixed pin setting that applies to all PCIe ports.
405 port->endpoint = test_mode_pin(MODE_PIN11);
407 ret = pcie_init(port);
408 if (unlikely(ret < 0))
411 return register_pci_controller(port->hose);
414 static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
415 .core_init = sh7786_pcie_core_init,
416 .port_init_hw = sh7786_pcie_init_hw,
419 static int __init sh7786_pcie_init(void)
423 printk(KERN_NOTICE "PCI: Starting intialization.\n");
425 sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops;
427 nr_ports = sh7786_pcie_hwops->core_init();
428 BUG_ON(nr_ports > ARRAY_SIZE(sh7786_pci_channels));
430 if (unlikely(nr_ports == 0))
433 sh7786_pcie_ports = kzalloc(nr_ports * sizeof(struct sh7786_pcie_port),
435 if (unlikely(!sh7786_pcie_ports))
438 printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
440 for (i = 0; i < nr_ports; i++) {
441 struct sh7786_pcie_port *port = sh7786_pcie_ports + i;
444 port->hose = sh7786_pci_channels + i;
445 port->hose->io_map_base = port->hose->resources[0].start;
447 ret |= sh7786_pcie_hwops->port_init_hw(port);
455 arch_initcall(sh7786_pcie_init);