2 * Freescale MPC85xx/MPC86xx RapidIO support
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
13 * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
16 * Copyright 2005 MontaVista Software, Inc.
17 * Matt Porter <mporter@kernel.crashing.org>
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/interrupt.h>
30 #include <linux/device.h>
31 #include <linux/rio.h>
32 #include <linux/rio_drv.h>
33 #include <linux/of_platform.h>
34 #include <linux/delay.h>
35 #include <linux/slab.h>
36 #include <linux/kfifo.h>
39 #include <asm/machdep.h>
40 #include <asm/uaccess.h>
42 #undef DEBUG_PW /* Port-Write debugging */
44 /* RapidIO definition irq, which read from OF-tree */
45 #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq)
46 #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq)
47 #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
48 #define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq)
50 #define RIO_ATMU_REGS_OFFSET 0x10c00
51 #define RIO_P_MSG_REGS_OFFSET 0x11000
52 #define RIO_S_MSG_REGS_OFFSET 0x13000
53 #define RIO_ESCSR 0x158
54 #define RIO_CCSR 0x15c
55 #define RIO_LTLEDCSR 0x0608
56 #define RIO_LTLEDCSR_IER 0x80000000
57 #define RIO_LTLEDCSR_PRT 0x01000000
58 #define RIO_LTLEECSR 0x060c
59 #define RIO_EPWISR 0x10010
60 #define RIO_ISR_AACR 0x10120
61 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
62 #define RIO_MAINT_WIN_SIZE 0x400000
63 #define RIO_DBELL_WIN_SIZE 0x1000
65 #define RIO_MSG_OMR_MUI 0x00000002
66 #define RIO_MSG_OSR_TE 0x00000080
67 #define RIO_MSG_OSR_QOI 0x00000020
68 #define RIO_MSG_OSR_QFI 0x00000010
69 #define RIO_MSG_OSR_MUB 0x00000004
70 #define RIO_MSG_OSR_EOMI 0x00000002
71 #define RIO_MSG_OSR_QEI 0x00000001
73 #define RIO_MSG_IMR_MI 0x00000002
74 #define RIO_MSG_ISR_TE 0x00000080
75 #define RIO_MSG_ISR_QFI 0x00000010
76 #define RIO_MSG_ISR_DIQI 0x00000001
78 #define RIO_IPWMR_SEN 0x00100000
79 #define RIO_IPWMR_QFIE 0x00000100
80 #define RIO_IPWMR_EIE 0x00000020
81 #define RIO_IPWMR_CQ 0x00000002
82 #define RIO_IPWMR_PWE 0x00000001
84 #define RIO_IPWSR_QF 0x00100000
85 #define RIO_IPWSR_TE 0x00000080
86 #define RIO_IPWSR_QFI 0x00000010
87 #define RIO_IPWSR_PWD 0x00000008
88 #define RIO_IPWSR_PWB 0x00000004
90 #define RIO_MSG_DESC_SIZE 32
91 #define RIO_MSG_BUFFER_SIZE 4096
92 #define RIO_MIN_TX_RING_SIZE 2
93 #define RIO_MAX_TX_RING_SIZE 2048
94 #define RIO_MIN_RX_RING_SIZE 2
95 #define RIO_MAX_RX_RING_SIZE 2048
97 #define DOORBELL_DMR_DI 0x00000002
98 #define DOORBELL_DSR_TE 0x00000080
99 #define DOORBELL_DSR_QFI 0x00000010
100 #define DOORBELL_DSR_DIQI 0x00000001
101 #define DOORBELL_TID_OFFSET 0x02
102 #define DOORBELL_SID_OFFSET 0x04
103 #define DOORBELL_INFO_OFFSET 0x06
105 #define DOORBELL_MESSAGE_SIZE 0x08
106 #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET))
107 #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET))
108 #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
110 struct rio_atmu_regs {
119 struct rio_msg_regs {
120 u32 omr; /* 0xD_3000 - Outbound message 0 mode register */
121 u32 osr; /* 0xD_3004 - Outbound message 0 status register */
123 u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue
124 dequeue pointer address register */
126 u32 osar; /* 0xD_3014 - Outbound message 0 source address
128 u32 odpr; /* 0xD_3018 - Outbound message 0 destination port
130 u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes
132 u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count
135 u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue
136 enqueue pointer address register */
138 u32 imr; /* 0xD_3060 - Inbound message 0 mode register */
139 u32 isr; /* 0xD_3064 - Inbound message 0 status register */
141 u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue
142 pointer address register*/
144 u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue
145 pointer address register */
147 u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */
148 u32 odsr; /* 0xD_3404 - Outbound doorbell status register */
150 u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port
152 u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes
155 u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold
156 configuration register */
158 u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */
159 u32 dsr; /* 0xD_3464 - Inbound doorbell status register */
161 u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer
164 u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer
167 u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */
168 u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */
169 u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address
171 u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address
186 struct rio_dbell_ring {
191 struct rio_msg_tx_ring {
194 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
195 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
201 struct rio_msg_rx_ring {
204 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
210 struct rio_port_write_msg {
220 void __iomem *regs_win;
221 struct rio_atmu_regs __iomem *atmu_regs;
222 struct rio_atmu_regs __iomem *maint_atmu_regs;
223 struct rio_atmu_regs __iomem *dbell_atmu_regs;
224 void __iomem *dbell_win;
225 void __iomem *maint_win;
226 struct rio_msg_regs __iomem *msg_regs;
227 struct rio_dbell_ring dbell_ring;
228 struct rio_msg_tx_ring msg_tx_ring;
229 struct rio_msg_rx_ring msg_rx_ring;
230 struct rio_port_write_msg port_write_msg;
235 struct work_struct pw_work;
236 struct kfifo pw_fifo;
237 spinlock_t pw_fifo_lock;
240 #define __fsl_read_rio_config(x, addr, err, op) \
241 __asm__ __volatile__( \
242 "1: "op" %1,0(%2)\n" \
245 ".section .fixup,\"ax\"\n" \
249 ".section __ex_table,\"a\"\n" \
253 : "=r" (err), "=r" (x) \
254 : "b" (addr), "i" (-EFAULT), "0" (err))
256 static void __iomem *rio_regs_win;
259 static int (*saved_mcheck_exception)(struct pt_regs *regs);
261 static int fsl_rio_mcheck_exception(struct pt_regs *regs)
263 const struct exception_table_entry *entry = NULL;
264 unsigned long reason = mfspr(SPRN_MCSR);
266 if (reason & MCSR_BUS_RBERR) {
267 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
268 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
269 /* Check if we are prepared to handle this fault */
270 entry = search_exception_tables(regs->nip);
272 pr_debug("RIO: %s - MC Exception handled\n",
274 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
277 regs->nip = entry->fixup;
283 if (saved_mcheck_exception)
284 return saved_mcheck_exception(regs);
286 return cur_cpu_spec->machine_check(regs);
291 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
292 * @mport: RapidIO master port info
293 * @index: ID of RapidIO interface
294 * @destid: Destination ID of target device
295 * @data: 16-bit info field of RapidIO doorbell message
297 * Sends a MPC85xx doorbell message. Returns %0 on success or
298 * %-EINVAL on failure.
300 static int fsl_rio_doorbell_send(struct rio_mport *mport,
301 int index, u16 destid, u16 data)
303 struct rio_priv *priv = mport->priv;
304 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
305 index, destid, data);
306 switch (mport->phy_type) {
307 case RIO_PHY_PARALLEL:
308 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
309 out_be16(priv->dbell_win, data);
312 /* In the serial version silicons, such as MPC8548, MPC8641,
313 * below operations is must be.
315 out_be32(&priv->msg_regs->odmr, 0x00000000);
316 out_be32(&priv->msg_regs->odretcr, 0x00000004);
317 out_be32(&priv->msg_regs->oddpr, destid << 16);
318 out_be32(&priv->msg_regs->oddatr, data);
319 out_be32(&priv->msg_regs->odmr, 0x00000001);
327 * fsl_local_config_read - Generate a MPC85xx local config space read
328 * @mport: RapidIO master port info
329 * @index: ID of RapdiIO interface
330 * @offset: Offset into configuration space
331 * @len: Length (in bytes) of the maintenance transaction
332 * @data: Value to be read into
334 * Generates a MPC85xx local configuration space read. Returns %0 on
335 * success or %-EINVAL on failure.
337 static int fsl_local_config_read(struct rio_mport *mport,
338 int index, u32 offset, int len, u32 *data)
340 struct rio_priv *priv = mport->priv;
341 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
343 *data = in_be32(priv->regs_win + offset);
349 * fsl_local_config_write - Generate a MPC85xx local config space write
350 * @mport: RapidIO master port info
351 * @index: ID of RapdiIO interface
352 * @offset: Offset into configuration space
353 * @len: Length (in bytes) of the maintenance transaction
354 * @data: Value to be written
356 * Generates a MPC85xx local configuration space write. Returns %0 on
357 * success or %-EINVAL on failure.
359 static int fsl_local_config_write(struct rio_mport *mport,
360 int index, u32 offset, int len, u32 data)
362 struct rio_priv *priv = mport->priv;
364 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
365 index, offset, data);
366 out_be32(priv->regs_win + offset, data);
372 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
373 * @mport: RapidIO master port info
374 * @index: ID of RapdiIO interface
375 * @destid: Destination ID of transaction
376 * @hopcount: Number of hops to target device
377 * @offset: Offset into configuration space
378 * @len: Length (in bytes) of the maintenance transaction
379 * @val: Location to be read into
381 * Generates a MPC85xx read maintenance transaction. Returns %0 on
382 * success or %-EINVAL on failure.
385 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
386 u8 hopcount, u32 offset, int len, u32 *val)
388 struct rio_priv *priv = mport->priv;
393 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
394 index, destid, hopcount, offset, len);
396 /* 16MB maintenance window possible */
397 /* allow only aligned access to maintenance registers */
398 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
401 out_be32(&priv->maint_atmu_regs->rowtar,
402 (destid << 22) | (hopcount << 12) | (offset >> 12));
403 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
405 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
408 __fsl_read_rio_config(rval, data, err, "lbz");
411 __fsl_read_rio_config(rval, data, err, "lhz");
414 __fsl_read_rio_config(rval, data, err, "lwz");
421 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
422 err, destid, hopcount, offset);
431 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
432 * @mport: RapidIO master port info
433 * @index: ID of RapdiIO interface
434 * @destid: Destination ID of transaction
435 * @hopcount: Number of hops to target device
436 * @offset: Offset into configuration space
437 * @len: Length (in bytes) of the maintenance transaction
438 * @val: Value to be written
440 * Generates an MPC85xx write maintenance transaction. Returns %0 on
441 * success or %-EINVAL on failure.
444 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
445 u8 hopcount, u32 offset, int len, u32 val)
447 struct rio_priv *priv = mport->priv;
450 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
451 index, destid, hopcount, offset, len, val);
453 /* 16MB maintenance windows possible */
454 /* allow only aligned access to maintenance registers */
455 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
458 out_be32(&priv->maint_atmu_regs->rowtar,
459 (destid << 22) | (hopcount << 12) | (offset >> 12));
460 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
462 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
465 out_8((u8 *) data, val);
468 out_be16((u16 *) data, val);
471 out_be32((u32 *) data, val);
481 * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
482 * @mport: Master port with outbound message queue
483 * @rdev: Target of outbound message
484 * @mbox: Outbound mailbox
485 * @buffer: Message to add to outbound queue
486 * @len: Length of message
488 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
489 * %0 on success or %-EINVAL on failure.
492 rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
493 void *buffer, size_t len)
495 struct rio_priv *priv = mport->priv;
497 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
498 + priv->msg_tx_ring.tx_slot;
502 ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
503 rdev->destid, mbox, (int)buffer, len);
505 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
510 /* Copy and clear rest of buffer */
511 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
513 if (len < (RIO_MAX_MSG_SIZE - 4))
514 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
515 + len, 0, RIO_MAX_MSG_SIZE - len);
517 switch (mport->phy_type) {
518 case RIO_PHY_PARALLEL:
519 /* Set mbox field for message */
520 desc->dport = mbox & 0x3;
522 /* Enable EOMI interrupt, set priority, and set destid */
523 desc->dattr = 0x28000000 | (rdev->destid << 2);
526 /* Set mbox field for message, and set destid */
527 desc->dport = (rdev->destid << 16) | (mbox & 0x3);
529 /* Enable EOMI interrupt and priority */
530 desc->dattr = 0x28000000;
534 /* Set transfer size aligned to next power of 2 (in double words) */
535 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
537 /* Set snooping and source buffer address */
538 desc->saddr = 0x00000004
539 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
541 /* Increment enqueue pointer */
542 omr = in_be32(&priv->msg_regs->omr);
543 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
545 /* Go to next descriptor */
546 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
547 priv->msg_tx_ring.tx_slot = 0;
553 EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
556 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
557 * @irq: Linux interrupt number
558 * @dev_instance: Pointer to interrupt-specific data
560 * Handles outbound message interrupts. Executes a register outbound
561 * mailbox event handler and acks the interrupt occurrence.
564 fsl_rio_tx_handler(int irq, void *dev_instance)
567 struct rio_mport *port = (struct rio_mport *)dev_instance;
568 struct rio_priv *priv = port->priv;
570 osr = in_be32(&priv->msg_regs->osr);
572 if (osr & RIO_MSG_OSR_TE) {
573 pr_info("RIO: outbound message transmission error\n");
574 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
578 if (osr & RIO_MSG_OSR_QOI) {
579 pr_info("RIO: outbound message queue overflow\n");
580 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
584 if (osr & RIO_MSG_OSR_EOMI) {
585 u32 dqp = in_be32(&priv->msg_regs->odqdpar);
586 int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
587 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
590 /* Ack the end-of-message interrupt */
591 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
599 * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
600 * @mport: Master port implementing the outbound message unit
601 * @dev_id: Device specific pointer to pass on event
602 * @mbox: Mailbox to open
603 * @entries: Number of entries in the outbound mailbox ring
605 * Initializes buffer ring, request the outbound message interrupt,
606 * and enables the outbound message unit. Returns %0 on success and
607 * %-EINVAL or %-ENOMEM on failure.
609 int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
612 struct rio_priv *priv = mport->priv;
614 if ((entries < RIO_MIN_TX_RING_SIZE) ||
615 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
620 /* Initialize shadow copy ring */
621 priv->msg_tx_ring.dev_id = dev_id;
622 priv->msg_tx_ring.size = entries;
624 for (i = 0; i < priv->msg_tx_ring.size; i++) {
625 priv->msg_tx_ring.virt_buffer[i] =
626 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
627 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
628 if (!priv->msg_tx_ring.virt_buffer[i]) {
630 for (j = 0; j < priv->msg_tx_ring.size; j++)
631 if (priv->msg_tx_ring.virt_buffer[j])
632 dma_free_coherent(priv->dev,
642 /* Initialize outbound message descriptor ring */
643 priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
644 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
645 &priv->msg_tx_ring.phys, GFP_KERNEL);
646 if (!priv->msg_tx_ring.virt) {
650 memset(priv->msg_tx_ring.virt, 0,
651 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
652 priv->msg_tx_ring.tx_slot = 0;
654 /* Point dequeue/enqueue pointers at first entry in ring */
655 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
656 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
658 /* Configure for snooping */
659 out_be32(&priv->msg_regs->osar, 0x00000004);
661 /* Clear interrupt status */
662 out_be32(&priv->msg_regs->osr, 0x000000b3);
664 /* Hook up outbound message handler */
665 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
666 "msg_tx", (void *)mport);
671 * Configure outbound message unit
673 * Interrupts (all enabled, except QEIE)
677 out_be32(&priv->msg_regs->omr, 0x00100220);
679 /* Set number of entries */
680 out_be32(&priv->msg_regs->omr,
681 in_be32(&priv->msg_regs->omr) |
682 ((get_bitmask_order(entries) - 2) << 12));
684 /* Now enable the unit */
685 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
691 dma_free_coherent(priv->dev,
692 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
693 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
696 for (i = 0; i < priv->msg_tx_ring.size; i++)
697 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
698 priv->msg_tx_ring.virt_buffer[i],
699 priv->msg_tx_ring.phys_buffer[i]);
705 * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
706 * @mport: Master port implementing the outbound message unit
707 * @mbox: Mailbox to close
709 * Disables the outbound message unit, free all buffers, and
710 * frees the outbound message interrupt.
712 void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
714 struct rio_priv *priv = mport->priv;
715 /* Disable inbound message unit */
716 out_be32(&priv->msg_regs->omr, 0);
719 dma_free_coherent(priv->dev,
720 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
721 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
724 free_irq(IRQ_RIO_TX(mport), (void *)mport);
728 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
729 * @irq: Linux interrupt number
730 * @dev_instance: Pointer to interrupt-specific data
732 * Handles inbound message interrupts. Executes a registered inbound
733 * mailbox event handler and acks the interrupt occurrence.
736 fsl_rio_rx_handler(int irq, void *dev_instance)
739 struct rio_mport *port = (struct rio_mport *)dev_instance;
740 struct rio_priv *priv = port->priv;
742 isr = in_be32(&priv->msg_regs->isr);
744 if (isr & RIO_MSG_ISR_TE) {
745 pr_info("RIO: inbound message reception error\n");
746 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
750 /* XXX Need to check/dispatch until queue empty */
751 if (isr & RIO_MSG_ISR_DIQI) {
753 * We implement *only* mailbox 0, but can receive messages
754 * for any mailbox/letter to that mailbox destination. So,
755 * make the callback with an unknown/invalid mailbox number
758 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
760 /* Ack the queueing interrupt */
761 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
769 * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
770 * @mport: Master port implementing the inbound message unit
771 * @dev_id: Device specific pointer to pass on event
772 * @mbox: Mailbox to open
773 * @entries: Number of entries in the inbound mailbox ring
775 * Initializes buffer ring, request the inbound message interrupt,
776 * and enables the inbound message unit. Returns %0 on success
777 * and %-EINVAL or %-ENOMEM on failure.
779 int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
782 struct rio_priv *priv = mport->priv;
784 if ((entries < RIO_MIN_RX_RING_SIZE) ||
785 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
790 /* Initialize client buffer ring */
791 priv->msg_rx_ring.dev_id = dev_id;
792 priv->msg_rx_ring.size = entries;
793 priv->msg_rx_ring.rx_slot = 0;
794 for (i = 0; i < priv->msg_rx_ring.size; i++)
795 priv->msg_rx_ring.virt_buffer[i] = NULL;
797 /* Initialize inbound message ring */
798 priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
799 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
800 &priv->msg_rx_ring.phys, GFP_KERNEL);
801 if (!priv->msg_rx_ring.virt) {
806 /* Point dequeue/enqueue pointers at first entry in ring */
807 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
808 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
810 /* Clear interrupt status */
811 out_be32(&priv->msg_regs->isr, 0x00000091);
813 /* Hook up inbound message handler */
814 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
815 "msg_rx", (void *)mport);
817 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
818 priv->msg_tx_ring.virt_buffer[i],
819 priv->msg_tx_ring.phys_buffer[i]);
824 * Configure inbound message unit:
826 * 4KB max message size
827 * Unmask all interrupt sources
830 out_be32(&priv->msg_regs->imr, 0x001b0060);
832 /* Set number of queue entries */
833 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
835 /* Now enable the unit */
836 setbits32(&priv->msg_regs->imr, 0x1);
843 * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
844 * @mport: Master port implementing the inbound message unit
845 * @mbox: Mailbox to close
847 * Disables the inbound message unit, free all buffers, and
848 * frees the inbound message interrupt.
850 void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
852 struct rio_priv *priv = mport->priv;
853 /* Disable inbound message unit */
854 out_be32(&priv->msg_regs->imr, 0);
857 dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
858 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
861 free_irq(IRQ_RIO_RX(mport), (void *)mport);
865 * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
866 * @mport: Master port implementing the inbound message unit
867 * @mbox: Inbound mailbox number
868 * @buf: Buffer to add to inbound queue
870 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
871 * %0 on success or %-EINVAL on failure.
873 int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
876 struct rio_priv *priv = mport->priv;
878 pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
879 priv->msg_rx_ring.rx_slot);
881 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
883 "RIO: error adding inbound buffer %d, buffer exists\n",
884 priv->msg_rx_ring.rx_slot);
889 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
890 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
891 priv->msg_rx_ring.rx_slot = 0;
897 EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
900 * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
901 * @mport: Master port implementing the inbound message unit
902 * @mbox: Inbound mailbox number
904 * Gets the next available inbound message from the inbound message queue.
905 * A pointer to the message is returned on success or NULL on failure.
907 void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
909 struct rio_priv *priv = mport->priv;
910 u32 phys_buf, virt_buf;
914 phys_buf = in_be32(&priv->msg_regs->ifqdpar);
916 /* If no more messages, then bail out */
917 if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
920 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
921 - priv->msg_rx_ring.phys);
922 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
923 buf = priv->msg_rx_ring.virt_buffer[buf_idx];
927 "RIO: inbound message copy failed, no buffers\n");
931 /* Copy max message size, caller is expected to allocate that big */
932 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
934 /* Clear the available buffer */
935 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
938 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
944 EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
947 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
948 * @irq: Linux interrupt number
949 * @dev_instance: Pointer to interrupt-specific data
951 * Handles doorbell interrupts. Parses a list of registered
952 * doorbell event handlers and executes a matching event handler.
955 fsl_rio_dbell_handler(int irq, void *dev_instance)
958 struct rio_mport *port = (struct rio_mport *)dev_instance;
959 struct rio_priv *priv = port->priv;
961 dsr = in_be32(&priv->msg_regs->dsr);
963 if (dsr & DOORBELL_DSR_TE) {
964 pr_info("RIO: doorbell reception error\n");
965 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
969 if (dsr & DOORBELL_DSR_QFI) {
970 pr_info("RIO: doorbell queue full\n");
971 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
975 /* XXX Need to check/dispatch until queue empty */
976 if (dsr & DOORBELL_DSR_DIQI) {
978 (u32) priv->dbell_ring.virt +
979 (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
980 struct rio_dbell *dbell;
984 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
985 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
987 list_for_each_entry(dbell, &port->dbells, node) {
988 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
989 (dbell->res->end >= DBELL_INF(dmsg))) {
995 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
999 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
1000 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
1002 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
1003 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
1011 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
1012 * @mport: Master port implementing the inbound doorbell unit
1014 * Initializes doorbell unit hardware and inbound DMA buffer
1015 * ring. Called from fsl_rio_setup(). Returns %0 on success
1016 * or %-ENOMEM on failure.
1018 static int fsl_rio_doorbell_init(struct rio_mport *mport)
1020 struct rio_priv *priv = mport->priv;
1023 /* Map outbound doorbell window immediately after maintenance window */
1024 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
1025 RIO_DBELL_WIN_SIZE);
1026 if (!priv->dbell_win) {
1028 "RIO: unable to map outbound doorbell window\n");
1033 /* Initialize inbound doorbells */
1034 priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 *
1035 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
1036 if (!priv->dbell_ring.virt) {
1037 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
1039 iounmap(priv->dbell_win);
1043 /* Point dequeue/enqueue pointers at first entry in ring */
1044 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
1045 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
1047 /* Clear interrupt status */
1048 out_be32(&priv->msg_regs->dsr, 0x00000091);
1050 /* Hook up doorbell handler */
1051 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
1052 "dbell_rx", (void *)mport);
1054 iounmap(priv->dbell_win);
1055 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE,
1056 priv->dbell_ring.virt, priv->dbell_ring.phys);
1058 "MPC85xx RIO: unable to request inbound doorbell irq");
1062 /* Configure doorbells for snooping, 512 entries, and enable */
1063 out_be32(&priv->msg_regs->dmr, 0x00108161);
1070 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
1071 * @irq: Linux interrupt number
1072 * @dev_instance: Pointer to interrupt-specific data
1074 * Handles port write interrupts. Parses a list of registered
1075 * port write event handlers and executes a matching event handler.
1078 fsl_rio_port_write_handler(int irq, void *dev_instance)
1081 struct rio_mport *port = (struct rio_mport *)dev_instance;
1082 struct rio_priv *priv = port->priv;
1085 ipwmr = in_be32(&priv->msg_regs->pwmr);
1086 ipwsr = in_be32(&priv->msg_regs->pwsr);
1088 epwisr = in_be32(priv->regs_win + RIO_EPWISR);
1089 if (epwisr & 0x80000000) {
1090 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1091 pr_info("RIO_LTLEDCSR = 0x%x\n", tmp);
1092 out_be32(priv->regs_win + RIO_LTLEDCSR, 0);
1095 if (!(epwisr & 0x00000001))
1099 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
1100 if (ipwsr & RIO_IPWSR_QF)
1102 if (ipwsr & RIO_IPWSR_TE)
1104 if (ipwsr & RIO_IPWSR_QFI)
1106 if (ipwsr & RIO_IPWSR_PWD)
1108 if (ipwsr & RIO_IPWSR_PWB)
1112 out_be32(&priv->msg_regs->pwsr,
1113 ipwsr & (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
1115 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
1116 priv->port_write_msg.err_count++;
1117 pr_info("RIO: Port-Write Transaction Err (%d)\n",
1118 priv->port_write_msg.err_count);
1120 if (ipwsr & RIO_IPWSR_PWD) {
1121 priv->port_write_msg.discard_count++;
1122 pr_info("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
1123 priv->port_write_msg.discard_count);
1126 /* Schedule deferred processing if PW was received */
1127 if (ipwsr & RIO_IPWSR_QFI) {
1128 /* Save PW message (if there is room in FIFO),
1129 * otherwise discard it.
1131 if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) {
1132 priv->port_write_msg.msg_count++;
1133 kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt,
1136 priv->port_write_msg.discard_count++;
1137 pr_info("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
1138 priv->port_write_msg.discard_count);
1140 schedule_work(&priv->pw_work);
1143 /* Issue Clear Queue command. This allows another
1144 * port-write to be received.
1146 out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
1151 static void fsl_pw_dpc(struct work_struct *work)
1153 struct rio_priv *priv = container_of(work, struct rio_priv, pw_work);
1154 unsigned long flags;
1155 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
1158 * Process port-write messages
1160 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1161 while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
1163 /* Process one message */
1164 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1168 pr_debug("%s : Port-Write Message:", __func__);
1169 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
1171 pr_debug("\n0x%02x: 0x%08x", i*4,
1174 pr_debug(" 0x%08x", msg_buffer[i]);
1179 /* Pass the port-write message to RIO core for processing */
1180 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
1181 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1183 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1187 * fsl_rio_pw_enable - enable/disable port-write interface init
1188 * @mport: Master port implementing the port write unit
1189 * @enable: 1=enable; 0=disable port-write message handling
1191 static int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
1193 struct rio_priv *priv = mport->priv;
1196 rval = in_be32(&priv->msg_regs->pwmr);
1199 rval |= RIO_IPWMR_PWE;
1201 rval &= ~RIO_IPWMR_PWE;
1203 out_be32(&priv->msg_regs->pwmr, rval);
1209 * fsl_rio_port_write_init - MPC85xx port write interface init
1210 * @mport: Master port implementing the port write unit
1212 * Initializes port write unit hardware and DMA buffer
1213 * ring. Called from fsl_rio_setup(). Returns %0 on success
1214 * or %-ENOMEM on failure.
1216 static int fsl_rio_port_write_init(struct rio_mport *mport)
1218 struct rio_priv *priv = mport->priv;
1221 /* Following configurations require a disabled port write controller */
1222 out_be32(&priv->msg_regs->pwmr,
1223 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE);
1225 /* Initialize port write */
1226 priv->port_write_msg.virt = dma_alloc_coherent(priv->dev,
1228 &priv->port_write_msg.phys, GFP_KERNEL);
1229 if (!priv->port_write_msg.virt) {
1230 pr_err("RIO: unable allocate port write queue\n");
1234 priv->port_write_msg.err_count = 0;
1235 priv->port_write_msg.discard_count = 0;
1237 /* Point dequeue/enqueue pointers at first entry */
1238 out_be32(&priv->msg_regs->epwqbar, 0);
1239 out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys);
1241 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
1242 in_be32(&priv->msg_regs->epwqbar),
1243 in_be32(&priv->msg_regs->pwqbar));
1245 /* Clear interrupt status IPWSR */
1246 out_be32(&priv->msg_regs->pwsr,
1247 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
1249 /* Configure port write contoller for snooping enable all reporting,
1251 out_be32(&priv->msg_regs->pwmr,
1252 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
1255 /* Hook up port-write handler */
1256 rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 0,
1257 "port-write", (void *)mport);
1259 pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
1263 INIT_WORK(&priv->pw_work, fsl_pw_dpc);
1264 spin_lock_init(&priv->pw_fifo_lock);
1265 if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
1266 pr_err("FIFO allocation failed\n");
1271 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
1272 in_be32(&priv->msg_regs->pwmr),
1273 in_be32(&priv->msg_regs->pwsr));
1278 free_irq(IRQ_RIO_PW(mport), (void *)mport);
1280 dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE,
1281 priv->port_write_msg.virt,
1282 priv->port_write_msg.phys);
1286 static char *cmdline = NULL;
1288 static int fsl_rio_get_hdid(int index)
1290 /* XXX Need to parse multiple entries in some format */
1294 return simple_strtol(cmdline, NULL, 0);
1297 static int fsl_rio_get_cmdline(char *s)
1306 __setup("riohdid=", fsl_rio_get_cmdline);
1308 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
1313 switch (ccsr >> 30) {
1324 dev_info(dev, "Hardware port width: %s\n", str);
1326 switch ((ccsr >> 27) & 7) {
1328 str = "Single-lane 0";
1331 str = "Single-lane 2";
1340 dev_info(dev, "Training connection status: %s\n", str);
1343 if (!(ccsr & 0x80000000))
1344 dev_info(dev, "Output port operating in 8-bit mode\n");
1345 if (!(ccsr & 0x08000000))
1346 dev_info(dev, "Input port operating in 8-bit mode\n");
1351 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
1352 * @dev: platform_device pointer
1354 * Initializes MPC85xx RapidIO hardware interface, configures
1355 * master port with system-specific info, and registers the
1356 * master port with the RapidIO subsystem.
1358 int fsl_rio_setup(struct platform_device *dev)
1360 struct rio_ops *ops;
1361 struct rio_mport *port;
1362 struct rio_priv *priv;
1364 const u32 *dt_range, *cell;
1365 struct resource regs;
1368 u64 law_start, law_size;
1371 if (!dev->dev.of_node) {
1372 dev_err(&dev->dev, "Device OF-Node is NULL");
1376 rc = of_address_to_resource(dev->dev.of_node, 0, ®s);
1378 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
1379 dev->dev.of_node->full_name);
1382 dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name);
1383 dev_info(&dev->dev, "Regs: %pR\n", ®s);
1385 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen);
1387 dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
1388 dev->dev.of_node->full_name);
1392 /* Get node address wide */
1393 cell = of_get_property(dev->dev.of_node, "#address-cells", NULL);
1397 aw = of_n_addr_cells(dev->dev.of_node);
1398 /* Get node size wide */
1399 cell = of_get_property(dev->dev.of_node, "#size-cells", NULL);
1403 sw = of_n_size_cells(dev->dev.of_node);
1404 /* Get parent address wide wide */
1405 paw = of_n_addr_cells(dev->dev.of_node);
1407 law_start = of_read_number(dt_range + aw, paw);
1408 law_size = of_read_number(dt_range + aw + paw, sw);
1410 dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
1411 law_start, law_size);
1413 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
1418 ops->lcread = fsl_local_config_read;
1419 ops->lcwrite = fsl_local_config_write;
1420 ops->cread = fsl_rio_config_read;
1421 ops->cwrite = fsl_rio_config_write;
1422 ops->dsend = fsl_rio_doorbell_send;
1423 ops->pwenable = fsl_rio_pw_enable;
1425 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
1433 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
1435 printk(KERN_ERR "Can't alloc memory for 'priv'\n");
1440 INIT_LIST_HEAD(&port->dbells);
1441 port->iores.start = law_start;
1442 port->iores.end = law_start + law_size - 1;
1443 port->iores.flags = IORESOURCE_MEM;
1444 port->iores.name = "rio_io_win";
1446 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0);
1447 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2);
1448 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3);
1449 priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4);
1450 dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n",
1451 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq);
1453 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1454 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
1455 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
1456 strcpy(port->name, "RIO0 mport");
1458 priv->dev = &dev->dev;
1461 port->host_deviceid = fsl_rio_get_hdid(port->id);
1464 rio_register_mport(port);
1466 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);
1467 rio_regs_win = priv->regs_win;
1469 /* Probe the master port phy type */
1470 ccsr = in_be32(priv->regs_win + RIO_CCSR);
1471 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
1472 dev_info(&dev->dev, "RapidIO PHY type: %s\n",
1473 (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" :
1474 ((port->phy_type == RIO_PHY_SERIAL) ? "serial" :
1476 /* Checking the port training status */
1477 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1478 dev_err(&dev->dev, "Port is not ready. "
1479 "Try to restart connection...\n");
1480 switch (port->phy_type) {
1481 case RIO_PHY_SERIAL:
1483 out_be32(priv->regs_win + RIO_CCSR, 0);
1485 setbits32(priv->regs_win + RIO_CCSR, 0x02000000);
1487 setbits32(priv->regs_win + RIO_CCSR, 0x00600000);
1489 case RIO_PHY_PARALLEL:
1491 out_be32(priv->regs_win + RIO_CCSR, 0x22000000);
1493 out_be32(priv->regs_win + RIO_CCSR, 0x44000000);
1497 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1498 dev_err(&dev->dev, "Port restart failed.\n");
1502 dev_info(&dev->dev, "Port restart success!\n");
1504 fsl_rio_info(&dev->dev, ccsr);
1506 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
1507 & RIO_PEF_CTLS) >> 4;
1508 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
1509 port->sys_size ? 65536 : 256);
1511 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
1512 + RIO_ATMU_REGS_OFFSET);
1513 priv->maint_atmu_regs = priv->atmu_regs + 1;
1514 priv->dbell_atmu_regs = priv->atmu_regs + 2;
1515 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
1516 ((port->phy_type == RIO_PHY_SERIAL) ?
1517 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
1519 /* Set to receive any dist ID for serial RapidIO controller. */
1520 if (port->phy_type == RIO_PHY_SERIAL)
1521 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
1523 /* Configure maintenance transaction window */
1524 out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12);
1525 out_be32(&priv->maint_atmu_regs->rowar,
1526 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
1528 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
1530 /* Configure outbound doorbell window */
1531 out_be32(&priv->dbell_atmu_regs->rowbar,
1532 (law_start + RIO_MAINT_WIN_SIZE) >> 12);
1533 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */
1534 fsl_rio_doorbell_init(port);
1535 fsl_rio_port_write_init(port);
1538 saved_mcheck_exception = ppc_md.machine_check_exception;
1539 ppc_md.machine_check_exception = fsl_rio_mcheck_exception;
1541 /* Ensure that RFXE is set */
1542 mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000));
1546 iounmap(priv->regs_win);
1556 /* The probe function for RapidIO peer-to-peer network.
1558 static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev,
1559 const struct of_device_id *match)
1562 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
1563 dev->dev.of_node->full_name);
1565 rc = fsl_rio_setup(dev);
1569 /* Enumerate all registered ports */
1570 rc = rio_init_mports();
1575 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
1577 .compatible = "fsl,rapidio-delta",
1582 static struct of_platform_driver fsl_of_rio_rpn_driver = {
1584 .name = "fsl-of-rio",
1585 .owner = THIS_MODULE,
1586 .of_match_table = fsl_of_rio_rpn_ids,
1588 .probe = fsl_of_rio_rpn_probe,
1591 static __init int fsl_of_rio_rpn_init(void)
1593 return of_register_platform_driver(&fsl_of_rio_rpn_driver);
1596 subsys_initcall(fsl_of_rio_rpn_init);