2 * arch/powerpc/sysdev/dart_iommu.c
4 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
5 * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>,
8 * Based on pSeries_iommu.c:
9 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
10 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
12 * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include <linux/init.h>
31 #include <linux/types.h>
33 #include <linux/spinlock.h>
34 #include <linux/string.h>
35 #include <linux/pci.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/vmalloc.h>
38 #include <linux/suspend.h>
39 #include <linux/memblock.h>
40 #include <linux/gfp.h>
43 #include <asm/iommu.h>
44 #include <asm/pci-bridge.h>
45 #include <asm/machdep.h>
46 #include <asm/cacheflush.h>
47 #include <asm/ppc-pci.h>
51 /* Physical base address and size of the DART table */
52 unsigned long dart_tablebase; /* exported to htab_initialize */
53 static unsigned long dart_tablesize;
55 /* Virtual base address of the DART table */
56 static u32 *dart_vbase;
58 static u32 *dart_copy;
61 /* Mapped base address for the dart */
62 static unsigned int __iomem *dart;
64 /* Dummy val that entries are set to when unused */
65 static unsigned int dart_emptyval;
67 static struct iommu_table iommu_table_dart;
68 static int iommu_table_dart_inited;
69 static int dart_dirty;
70 static int dart_is_u4;
72 #define DART_U4_BYPASS_BASE 0x8000000000ull
76 static inline void dart_tlb_invalidate_all(void)
79 unsigned int reg, inv_bit;
84 /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the
85 * control register and wait for it to clear.
87 * Gotcha: Sometimes, the DART won't detect that the bit gets
88 * set. If so, clear it and set it again.
93 inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB;
96 reg = DART_IN(DART_CNTL);
98 DART_OUT(DART_CNTL, reg);
100 while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit))
102 if (l == (1L << limit)) {
105 reg = DART_IN(DART_CNTL);
107 DART_OUT(DART_CNTL, reg);
110 panic("DART: TLB did not flush after waiting a long "
115 static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
118 unsigned int l, limit;
120 reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
121 (bus_rpn & DART_CNTL_U4_IONE_MASK);
122 DART_OUT(DART_CNTL, reg);
127 while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) {
132 if (l == (1L << limit)) {
137 panic("DART: TLB did not flush after waiting a long "
142 static void dart_flush(struct iommu_table *tbl)
146 dart_tlb_invalidate_all();
151 static int dart_build(struct iommu_table *tbl, long index,
152 long npages, unsigned long uaddr,
153 enum dma_data_direction direction,
154 struct dma_attrs *attrs)
160 DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
162 dp = ((unsigned int*)tbl->it_base) + index;
164 /* On U3, all memory is contiguous, so we can move this
169 rpn = __pa(uaddr) >> DART_PAGE_SHIFT;
171 *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
173 uaddr += DART_PAGE_SIZE;
176 /* make sure all updates have reached memory */
178 in_be32((unsigned __iomem *)dp);
184 dart_tlb_invalidate_one(rpn++);
192 static void dart_free(struct iommu_table *tbl, long index, long npages)
196 /* We don't worry about flushing the TLB cache. The only drawback of
197 * not doing it is that we won't catch buggy device drivers doing
198 * bad DMAs, but then no 32-bit architecture ever does either.
201 DBG("dart: free at: %lx, %lx\n", index, npages);
203 dp = ((unsigned int *)tbl->it_base) + index;
206 *(dp++) = dart_emptyval;
210 static int __init dart_init(struct device_node *dart_node)
213 unsigned long tmp, base, size;
216 if (dart_tablebase == 0 || dart_tablesize == 0) {
217 printk(KERN_INFO "DART: table not allocated, using "
222 if (of_address_to_resource(dart_node, 0, &r))
223 panic("DART: can't get register base ! ");
225 /* Make sure nothing from the DART range remains in the CPU cache
226 * from a previous mapping that existed before the kernel took
229 flush_dcache_phys_range(dart_tablebase,
230 dart_tablebase + dart_tablesize);
232 /* Allocate a spare page to map all invalid DART pages. We need to do
233 * that to work around what looks like a problem with the HT bridge
234 * prefetching into invalid pages and corrupting data
236 tmp = memblock_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE);
237 dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) &
240 /* Map in DART registers */
241 dart = ioremap(r.start, resource_size(&r));
243 panic("DART: Cannot map registers!");
245 /* Map in DART table */
246 dart_vbase = ioremap(__pa(dart_tablebase), dart_tablesize);
248 /* Fill initial table */
249 for (i = 0; i < dart_tablesize/4; i++)
250 dart_vbase[i] = dart_emptyval;
252 /* Initialize DART with table base and enable it. */
253 base = dart_tablebase >> DART_PAGE_SHIFT;
254 size = dart_tablesize >> DART_PAGE_SHIFT;
256 size &= DART_SIZE_U4_SIZE_MASK;
257 DART_OUT(DART_BASE_U4, base);
258 DART_OUT(DART_SIZE_U4, size);
259 DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE);
261 size &= DART_CNTL_U3_SIZE_MASK;
263 DART_CNTL_U3_ENABLE |
264 (base << DART_CNTL_U3_BASE_SHIFT) |
265 (size << DART_CNTL_U3_SIZE_SHIFT));
268 /* Invalidate DART to get rid of possible stale TLBs */
269 dart_tlb_invalidate_all();
271 printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n",
272 dart_is_u4 ? "U4" : "U3");
277 static void iommu_table_dart_setup(void)
279 iommu_table_dart.it_busno = 0;
280 iommu_table_dart.it_offset = 0;
281 /* it_size is in number of entries */
282 iommu_table_dart.it_size = dart_tablesize / sizeof(u32);
284 /* Initialize the common IOMMU code */
285 iommu_table_dart.it_base = (unsigned long)dart_vbase;
286 iommu_table_dart.it_index = 0;
287 iommu_table_dart.it_blocksize = 1;
288 iommu_init_table(&iommu_table_dart, -1);
290 /* Reserve the last page of the DART to avoid possible prefetch
291 * past the DART mapped area
293 set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map);
296 static void dma_dev_setup_dart(struct device *dev)
298 /* We only have one iommu table on the mac for now, which makes
299 * things simple. Setup all PCI devices to point to this table
301 if (get_dma_ops(dev) == &dma_direct_ops)
302 set_dma_offset(dev, DART_U4_BYPASS_BASE);
304 set_iommu_table_base(dev, &iommu_table_dart);
307 static void pci_dma_dev_setup_dart(struct pci_dev *dev)
309 dma_dev_setup_dart(&dev->dev);
312 static void pci_dma_bus_setup_dart(struct pci_bus *bus)
314 if (!iommu_table_dart_inited) {
315 iommu_table_dart_inited = 1;
316 iommu_table_dart_setup();
320 static bool dart_device_on_pcie(struct device *dev)
322 struct device_node *np = of_node_get(dev->of_node);
325 if (of_device_is_compatible(np, "U4-pcie") ||
326 of_device_is_compatible(np, "u4-pcie")) {
330 np = of_get_next_parent(np);
335 static int dart_dma_set_mask(struct device *dev, u64 dma_mask)
337 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
340 /* U4 supports a DART bypass, we use it for 64-bit capable
341 * devices to improve performances. However, that only works
342 * for devices connected to U4 own PCIe interface, not bridged
343 * through hypertransport. We need the device to support at
344 * least 40 bits of addresses.
346 if (dart_device_on_pcie(dev) && dma_mask >= DMA_BIT_MASK(40)) {
347 dev_info(dev, "Using 64-bit DMA iommu bypass\n");
348 set_dma_ops(dev, &dma_direct_ops);
350 dev_info(dev, "Using 32-bit DMA via iommu\n");
351 set_dma_ops(dev, &dma_iommu_ops);
353 dma_dev_setup_dart(dev);
355 *dev->dma_mask = dma_mask;
359 void __init iommu_init_early_dart(void)
361 struct device_node *dn;
363 /* Find the DART in the device-tree */
364 dn = of_find_compatible_node(NULL, "dart", "u3-dart");
366 dn = of_find_compatible_node(NULL, "dart", "u4-dart");
368 return; /* use default direct_dma_ops */
372 /* Initialize the DART HW */
373 if (dart_init(dn) != 0)
376 /* Setup low level TCE operations for the core IOMMU code */
377 ppc_md.tce_build = dart_build;
378 ppc_md.tce_free = dart_free;
379 ppc_md.tce_flush = dart_flush;
381 /* Setup bypass if supported */
383 ppc_md.dma_set_mask = dart_dma_set_mask;
385 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_dart;
386 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_dart;
388 /* Setup pci_dma ops */
389 set_pci_dma_ops(&dma_iommu_ops);
393 /* If init failed, use direct iommu and null setup functions */
394 ppc_md.pci_dma_dev_setup = NULL;
395 ppc_md.pci_dma_bus_setup = NULL;
397 /* Setup pci_dma ops */
398 set_pci_dma_ops(&dma_direct_ops);
402 static void iommu_dart_save(void)
404 memcpy(dart_copy, dart_vbase, 2*1024*1024);
407 static void iommu_dart_restore(void)
409 memcpy(dart_vbase, dart_copy, 2*1024*1024);
410 dart_tlb_invalidate_all();
413 static int __init iommu_init_late_dart(void)
415 unsigned long tbasepfn;
418 /* if no dart table exists then we won't need to save it
419 * and the area has also not been reserved */
423 tbasepfn = __pa(dart_tablebase) >> PAGE_SHIFT;
424 register_nosave_region_late(tbasepfn,
425 tbasepfn + ((1<<24) >> PAGE_SHIFT));
427 /* For suspend we need to copy the dart contents because
428 * it is not part of the regular mapping (see above) and
429 * thus not saved automatically. The memory for this copy
430 * must be allocated early because we need 2 MB. */
431 p = alloc_pages(GFP_KERNEL, 21 - PAGE_SHIFT);
433 dart_copy = page_address(p);
435 ppc_md.iommu_save = iommu_dart_save;
436 ppc_md.iommu_restore = iommu_dart_restore;
441 late_initcall(iommu_init_late_dart);
444 void __init alloc_dart_table(void)
446 /* Only reserve DART space if machine has more than 1GB of RAM
447 * or if requested with iommu=on on cmdline.
449 * 1GB of RAM is picked as limit because some default devices
450 * (i.e. Airport Extreme) have 30 bit address range limits.
456 if (!iommu_force_on && memblock_end_of_DRAM() <= 0x40000000ull)
459 /* 512 pages (2MB) is max DART tablesize. */
460 dart_tablesize = 1UL << 21;
461 /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we
462 * will blow up an entire large page anyway in the kernel mapping
464 dart_tablebase = (unsigned long)
465 __va(memblock_alloc_base(1UL<<24, 1UL<<24, 0x80000000L));
467 printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase);