2 * The file intends to implement the functions needed by EEH, which is
3 * built on IODA compliant chip. Actually, lots of functions related
4 * to EEH would be built based on the OPAL APIs.
6 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/bootmem.h>
15 #include <linux/debugfs.h>
16 #include <linux/delay.h>
18 #include <linux/irq.h>
19 #include <linux/kernel.h>
20 #include <linux/msi.h>
21 #include <linux/notifier.h>
22 #include <linux/pci.h>
23 #include <linux/string.h>
26 #include <asm/eeh_event.h>
28 #include <asm/iommu.h>
29 #include <asm/msi_bitmap.h>
31 #include <asm/pci-bridge.h>
32 #include <asm/ppc-pci.h>
38 static int ioda_eeh_nb_init = 0;
40 static int ioda_eeh_event(struct notifier_block *nb,
41 unsigned long events, void *change)
43 uint64_t changed_evts = (uint64_t)change;
45 /* We simply send special EEH event */
46 if ((changed_evts & OPAL_EVENT_PCI_ERROR) &&
47 (events & OPAL_EVENT_PCI_ERROR) &&
49 eeh_send_failure_event(NULL);
54 static struct notifier_block ioda_eeh_nb = {
55 .notifier_call = ioda_eeh_event,
60 #ifdef CONFIG_DEBUG_FS
61 static int ioda_eeh_dbgfs_set(void *data, int offset, u64 val)
63 struct pci_controller *hose = data;
64 struct pnv_phb *phb = hose->private_data;
66 out_be64(phb->regs + offset, val);
70 static int ioda_eeh_dbgfs_get(void *data, int offset, u64 *val)
72 struct pci_controller *hose = data;
73 struct pnv_phb *phb = hose->private_data;
75 *val = in_be64(phb->regs + offset);
79 static int ioda_eeh_outb_dbgfs_set(void *data, u64 val)
81 return ioda_eeh_dbgfs_set(data, 0xD10, val);
84 static int ioda_eeh_outb_dbgfs_get(void *data, u64 *val)
86 return ioda_eeh_dbgfs_get(data, 0xD10, val);
89 static int ioda_eeh_inbA_dbgfs_set(void *data, u64 val)
91 return ioda_eeh_dbgfs_set(data, 0xD90, val);
94 static int ioda_eeh_inbA_dbgfs_get(void *data, u64 *val)
96 return ioda_eeh_dbgfs_get(data, 0xD90, val);
99 static int ioda_eeh_inbB_dbgfs_set(void *data, u64 val)
101 return ioda_eeh_dbgfs_set(data, 0xE10, val);
104 static int ioda_eeh_inbB_dbgfs_get(void *data, u64 *val)
106 return ioda_eeh_dbgfs_get(data, 0xE10, val);
109 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_outb_dbgfs_ops, ioda_eeh_outb_dbgfs_get,
110 ioda_eeh_outb_dbgfs_set, "0x%llx\n");
111 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbA_dbgfs_ops, ioda_eeh_inbA_dbgfs_get,
112 ioda_eeh_inbA_dbgfs_set, "0x%llx\n");
113 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbB_dbgfs_ops, ioda_eeh_inbB_dbgfs_get,
114 ioda_eeh_inbB_dbgfs_set, "0x%llx\n");
115 #endif /* CONFIG_DEBUG_FS */
118 * ioda_eeh_post_init - Chip dependent post initialization
119 * @hose: PCI controller
121 * The function will be called after eeh PEs and devices
122 * have been built. That means the EEH is ready to supply
123 * service with I/O cache.
125 static int ioda_eeh_post_init(struct pci_controller *hose)
127 struct pnv_phb *phb = hose->private_data;
130 /* Register OPAL event notifier */
131 if (!ioda_eeh_nb_init) {
132 ret = opal_notifier_register(&ioda_eeh_nb);
134 pr_err("%s: Can't register OPAL event notifier (%d)\n",
139 ioda_eeh_nb_init = 1;
142 #ifdef CONFIG_DEBUG_FS
144 debugfs_create_file("err_injct_outbound", 0600,
146 &ioda_eeh_outb_dbgfs_ops);
147 debugfs_create_file("err_injct_inboundA", 0600,
149 &ioda_eeh_inbA_dbgfs_ops);
150 debugfs_create_file("err_injct_inboundB", 0600,
152 &ioda_eeh_inbB_dbgfs_ops);
156 phb->eeh_state |= PNV_EEH_STATE_ENABLED;
162 * ioda_eeh_set_option - Set EEH operation or I/O setting
166 * Enable or disable EEH option for the indicated PE. The
167 * function also can be used to enable I/O or DMA for the
170 static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
174 struct pci_controller *hose = pe->phb;
175 struct pnv_phb *phb = hose->private_data;
177 /* Check on PE number */
178 if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
179 pr_err("%s: PE address %x out of range [0, %x] "
181 __func__, pe->addr, phb->ioda.total_pe,
182 hose->global_number);
188 case EEH_OPT_DISABLE:
194 case EEH_OPT_THAW_MMIO:
195 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
196 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO);
198 pr_warning("%s: Failed to enable MMIO for "
199 "PHB#%x-PE#%x, err=%lld\n",
200 __func__, hose->global_number, pe_no, ret);
205 case EEH_OPT_THAW_DMA:
206 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
207 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA);
209 pr_warning("%s: Failed to enable DMA for "
210 "PHB#%x-PE#%x, err=%lld\n",
211 __func__, hose->global_number, pe_no, ret);
217 pr_warning("%s: Invalid option %d\n", __func__, option);
225 * ioda_eeh_get_state - Retrieve the state of PE
228 * The PE's state should be retrieved from the PEEV, PEST
229 * IODA tables. Since the OPAL has exported the function
230 * to do it, it'd better to use that.
232 static int ioda_eeh_get_state(struct eeh_pe *pe)
239 struct pci_controller *hose = pe->phb;
240 struct pnv_phb *phb = hose->private_data;
243 * Sanity check on PE address. The PHB PE address should
246 if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
247 pr_err("%s: PE address %x out of range [0, %x] "
249 __func__, pe->addr, phb->ioda.total_pe,
250 hose->global_number);
251 return EEH_STATE_NOT_SUPPORT;
254 /* Retrieve PE status through OPAL */
256 ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
257 &fstate, &pcierr, NULL);
259 pr_err("%s: Failed to get EEH status on "
260 "PHB#%x-PE#%x\n, err=%lld\n",
261 __func__, hose->global_number, pe_no, ret);
262 return EEH_STATE_NOT_SUPPORT;
265 /* Check PHB status */
266 if (pe->type & EEH_PE_PHB) {
268 result &= ~EEH_STATE_RESET_ACTIVE;
270 if (pcierr != OPAL_EEH_PHB_ERROR) {
271 result |= EEH_STATE_MMIO_ACTIVE;
272 result |= EEH_STATE_DMA_ACTIVE;
273 result |= EEH_STATE_MMIO_ENABLED;
274 result |= EEH_STATE_DMA_ENABLED;
280 /* Parse result out */
283 case OPAL_EEH_STOPPED_NOT_FROZEN:
284 result &= ~EEH_STATE_RESET_ACTIVE;
285 result |= EEH_STATE_MMIO_ACTIVE;
286 result |= EEH_STATE_DMA_ACTIVE;
287 result |= EEH_STATE_MMIO_ENABLED;
288 result |= EEH_STATE_DMA_ENABLED;
290 case OPAL_EEH_STOPPED_MMIO_FREEZE:
291 result &= ~EEH_STATE_RESET_ACTIVE;
292 result |= EEH_STATE_DMA_ACTIVE;
293 result |= EEH_STATE_DMA_ENABLED;
295 case OPAL_EEH_STOPPED_DMA_FREEZE:
296 result &= ~EEH_STATE_RESET_ACTIVE;
297 result |= EEH_STATE_MMIO_ACTIVE;
298 result |= EEH_STATE_MMIO_ENABLED;
300 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
301 result &= ~EEH_STATE_RESET_ACTIVE;
303 case OPAL_EEH_STOPPED_RESET:
304 result |= EEH_STATE_RESET_ACTIVE;
306 case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
307 result |= EEH_STATE_UNAVAILABLE;
309 case OPAL_EEH_STOPPED_PERM_UNAVAIL:
310 result |= EEH_STATE_NOT_SUPPORT;
313 pr_warning("%s: Unexpected EEH status 0x%x "
315 __func__, fstate, hose->global_number, pe_no);
321 static int ioda_eeh_pe_clear(struct eeh_pe *pe)
323 struct pci_controller *hose;
332 phb = pe->phb->private_data;
334 /* Clear the EEH error on the PE */
335 ret = opal_pci_eeh_freeze_clear(phb->opal_id,
336 pe_no, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
338 pr_err("%s: Failed to clear EEH error for "
339 "PHB#%x-PE#%x, err=%lld\n",
340 __func__, hose->global_number, pe_no, ret);
345 * Read the PE state back and verify that the frozen
346 * state has been removed.
348 ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
349 &fstate, &pcierr, NULL);
351 pr_err("%s: Failed to get EEH status on "
352 "PHB#%x-PE#%x\n, err=%lld\n",
353 __func__, hose->global_number, pe_no, ret);
357 if (fstate != OPAL_EEH_STOPPED_NOT_FROZEN) {
358 pr_err("%s: Frozen state not cleared on "
359 "PHB#%x-PE#%x, sts=%x\n",
360 __func__, hose->global_number, pe_no, fstate);
367 static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
369 s64 rc = OPAL_HARDWARE;
372 rc = opal_pci_poll(phb->opal_id);
382 static int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
384 struct pnv_phb *phb = hose->private_data;
385 s64 rc = OPAL_HARDWARE;
387 pr_debug("%s: Reset PHB#%x, option=%d\n",
388 __func__, hose->global_number, option);
390 /* Issue PHB complete reset request */
391 if (option == EEH_RESET_FUNDAMENTAL ||
392 option == EEH_RESET_HOT)
393 rc = opal_pci_reset(phb->opal_id,
396 else if (option == EEH_RESET_DEACTIVATE)
397 rc = opal_pci_reset(phb->opal_id,
399 OPAL_DEASSERT_RESET);
404 * Poll state of the PHB until the request is done
407 rc = ioda_eeh_phb_poll(phb);
409 if (rc != OPAL_SUCCESS)
415 static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
417 struct pnv_phb *phb = hose->private_data;
418 s64 rc = OPAL_SUCCESS;
420 pr_debug("%s: Reset PHB#%x, option=%d\n",
421 __func__, hose->global_number, option);
424 * During the reset deassert time, we needn't care
425 * the reset scope because the firmware does nothing
426 * for fundamental or hot reset during deassert phase.
428 if (option == EEH_RESET_FUNDAMENTAL)
429 rc = opal_pci_reset(phb->opal_id,
430 OPAL_PCI_FUNDAMENTAL_RESET,
432 else if (option == EEH_RESET_HOT)
433 rc = opal_pci_reset(phb->opal_id,
436 else if (option == EEH_RESET_DEACTIVATE)
437 rc = opal_pci_reset(phb->opal_id,
439 OPAL_DEASSERT_RESET);
443 /* Poll state of the PHB until the request is done */
444 rc = ioda_eeh_phb_poll(phb);
446 if (rc != OPAL_SUCCESS)
452 static int ioda_eeh_bridge_reset(struct pci_controller *hose,
453 struct pci_dev *dev, int option)
457 pr_debug("%s: Reset device %04x:%02x:%02x.%01x with option %d\n",
458 __func__, hose->global_number, dev->bus->number,
459 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), option);
462 case EEH_RESET_FUNDAMENTAL:
464 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
465 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
466 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
468 case EEH_RESET_DEACTIVATE:
469 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
470 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
471 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
479 * ioda_eeh_reset - Reset the indicated PE
481 * @option: reset option
483 * Do reset on the indicated PE. For PCI bus sensitive PE,
484 * we need to reset the parent p2p bridge. The PHB has to
485 * be reinitialized if the p2p bridge is root bridge. For
486 * PCI device sensitive PE, we will try to reset the device
487 * through FLR. For now, we don't have OPAL APIs to do HARD
488 * reset yet, so all reset would be SOFT (HOT) reset.
490 static int ioda_eeh_reset(struct eeh_pe *pe, int option)
492 struct pci_controller *hose = pe->phb;
497 * Anyway, we have to clear the problematic state for the
498 * corresponding PE. However, we needn't do it if the PE
499 * is PHB associated. That means the PHB is having fatal
500 * errors and it needs reset. Further more, the AIB interface
501 * isn't reliable any more.
503 if (!(pe->type & EEH_PE_PHB) &&
504 (option == EEH_RESET_HOT ||
505 option == EEH_RESET_FUNDAMENTAL)) {
506 ret = ioda_eeh_pe_clear(pe);
512 * The rules applied to reset, either fundamental or hot reset:
514 * We always reset the direct upstream bridge of the PE. If the
515 * direct upstream bridge isn't root bridge, we always take hot
516 * reset no matter what option (fundamental or hot) is. Otherwise,
517 * we should do the reset according to the required option.
519 if (pe->type & EEH_PE_PHB) {
520 ret = ioda_eeh_phb_reset(hose, option);
522 bus = eeh_pe_bus_get(pe);
523 if (pci_is_root_bus(bus))
524 ret = ioda_eeh_root_reset(hose, option);
526 ret = ioda_eeh_bridge_reset(hose, bus->self, option);
533 * ioda_eeh_get_log - Retrieve error log
535 * @severity: Severity level of the log
536 * @drv_log: buffer to store the log
537 * @len: space of the log buffer
539 * The function is used to retrieve error log from P7IOC.
541 static int ioda_eeh_get_log(struct eeh_pe *pe, int severity,
542 char *drv_log, unsigned long len)
546 struct pci_controller *hose = pe->phb;
547 struct pnv_phb *phb = hose->private_data;
549 spin_lock_irqsave(&phb->lock, flags);
551 ret = opal_pci_get_phb_diag_data2(phb->opal_id,
552 phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
554 spin_unlock_irqrestore(&phb->lock, flags);
555 pr_warning("%s: Can't get log for PHB#%x-PE#%x (%lld)\n",
556 __func__, hose->global_number, pe->addr, ret);
560 /* The PHB diag-data is always indicative */
561 pnv_pci_dump_phb_diag_data(hose, phb->diag.blob);
563 spin_unlock_irqrestore(&phb->lock, flags);
569 * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE
572 * For particular PE, it might have included PCI bridges. In order
573 * to make the PE work properly, those PCI bridges should be configured
574 * correctly. However, we need do nothing on P7IOC since the reset
575 * function will do everything that should be covered by the function.
577 static int ioda_eeh_configure_bridge(struct eeh_pe *pe)
582 static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data)
585 pr_info(" GEM XFIR: %016llx\n", data->gemXfir);
586 pr_info(" GEM RFIR: %016llx\n", data->gemRfir);
587 pr_info(" GEM RIRQFIR: %016llx\n", data->gemRirqfir);
588 pr_info(" GEM Mask: %016llx\n", data->gemMask);
589 pr_info(" GEM RWOF: %016llx\n", data->gemRwof);
592 pr_info(" LEM FIR: %016llx\n", data->lemFir);
593 pr_info(" LEM Error Mask: %016llx\n", data->lemErrMask);
594 pr_info(" LEM Action 0: %016llx\n", data->lemAction0);
595 pr_info(" LEM Action 1: %016llx\n", data->lemAction1);
596 pr_info(" LEM WOF: %016llx\n", data->lemWof);
599 static void ioda_eeh_hub_diag(struct pci_controller *hose)
601 struct pnv_phb *phb = hose->private_data;
602 struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
605 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
606 if (rc != OPAL_SUCCESS) {
607 pr_warning("%s: Failed to get HUB#%llx diag-data (%ld)\n",
608 __func__, phb->hub_id, rc);
612 switch (data->type) {
613 case OPAL_P7IOC_DIAG_TYPE_RGC:
614 pr_info("P7IOC diag-data for RGC\n\n");
615 ioda_eeh_hub_diag_common(data);
616 pr_info(" RGC Status: %016llx\n", data->rgc.rgcStatus);
617 pr_info(" RGC LDCP: %016llx\n", data->rgc.rgcLdcp);
619 case OPAL_P7IOC_DIAG_TYPE_BI:
620 pr_info("P7IOC diag-data for BI %s\n\n",
621 data->bi.biDownbound ? "Downbound" : "Upbound");
622 ioda_eeh_hub_diag_common(data);
623 pr_info(" BI LDCP 0: %016llx\n", data->bi.biLdcp0);
624 pr_info(" BI LDCP 1: %016llx\n", data->bi.biLdcp1);
625 pr_info(" BI LDCP 2: %016llx\n", data->bi.biLdcp2);
626 pr_info(" BI Fence Status: %016llx\n", data->bi.biFenceStatus);
628 case OPAL_P7IOC_DIAG_TYPE_CI:
629 pr_info("P7IOC diag-data for CI Port %d\\nn",
631 ioda_eeh_hub_diag_common(data);
632 pr_info(" CI Port Status: %016llx\n", data->ci.ciPortStatus);
633 pr_info(" CI Port LDCP: %016llx\n", data->ci.ciPortLdcp);
635 case OPAL_P7IOC_DIAG_TYPE_MISC:
636 pr_info("P7IOC diag-data for MISC\n\n");
637 ioda_eeh_hub_diag_common(data);
639 case OPAL_P7IOC_DIAG_TYPE_I2C:
640 pr_info("P7IOC diag-data for I2C\n\n");
641 ioda_eeh_hub_diag_common(data);
644 pr_warning("%s: Invalid type of HUB#%llx diag-data (%d)\n",
645 __func__, phb->hub_id, data->type);
649 static void ioda_eeh_phb_diag(struct pci_controller *hose)
651 struct pnv_phb *phb = hose->private_data;
654 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
655 PNV_PCI_DIAG_BUF_SIZE);
656 if (rc != OPAL_SUCCESS) {
657 pr_warning("%s: Failed to get diag-data for PHB#%x (%ld)\n",
658 __func__, hose->global_number, rc);
662 pnv_pci_dump_phb_diag_data(hose, phb->diag.blob);
665 static int ioda_eeh_get_phb_pe(struct pci_controller *hose,
668 struct eeh_pe *phb_pe;
670 phb_pe = eeh_phb_pe_get(hose);
672 pr_warning("%s Can't find PE for PHB#%d\n",
673 __func__, hose->global_number);
681 static int ioda_eeh_get_pe(struct pci_controller *hose,
682 u16 pe_no, struct eeh_pe **pe)
684 struct eeh_pe *phb_pe, *dev_pe;
687 /* Find the PHB PE */
688 if (ioda_eeh_get_phb_pe(hose, &phb_pe))
691 /* Find the PE according to PE# */
692 memset(&dev, 0, sizeof(struct eeh_dev));
694 dev.pe_config_addr = pe_no;
695 dev_pe = eeh_pe_get(&dev);
696 if (!dev_pe) return -EEXIST;
703 * ioda_eeh_next_error - Retrieve next error for EEH core to handle
704 * @pe: The affected PE
706 * The function is expected to be called by EEH core while it gets
707 * special EEH event (without binding PE). The function calls to
708 * OPAL APIs for next error to handle. The informational error is
709 * handled internally by platform. However, the dead IOC, dead PHB,
710 * fenced PHB and frozen PE should be handled by EEH core eventually.
712 static int ioda_eeh_next_error(struct eeh_pe **pe)
714 struct pci_controller *hose;
717 u16 err_type, severity;
719 int ret = EEH_NEXT_ERR_NONE;
722 * While running here, it's safe to purge the event queue.
723 * And we should keep the cached OPAL notifier event sychronized
724 * between the kernel and firmware.
726 eeh_remove_event(NULL);
727 opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
729 list_for_each_entry(hose, &hose_list, list_node) {
731 * If the subordinate PCI buses of the PHB has been
732 * removed, we needn't take care of it any more.
734 phb = hose->private_data;
735 if (phb->eeh_state & PNV_EEH_STATE_REMOVED)
738 rc = opal_pci_next_error(phb->opal_id,
739 &frozen_pe_no, &err_type, &severity);
741 /* If OPAL API returns error, we needn't proceed */
742 if (rc != OPAL_SUCCESS) {
743 pr_devel("%s: Invalid return value on "
744 "PHB#%x (0x%lx) from opal_pci_next_error",
745 __func__, hose->global_number, rc);
749 /* If the PHB doesn't have error, stop processing */
750 if (err_type == OPAL_EEH_NO_ERROR ||
751 severity == OPAL_EEH_SEV_NO_ERROR) {
752 pr_devel("%s: No error found on PHB#%x\n",
753 __func__, hose->global_number);
758 * Processing the error. We're expecting the error with
759 * highest priority reported upon multiple errors on the
762 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
763 __func__, err_type, severity,
764 frozen_pe_no, hose->global_number);
766 case OPAL_EEH_IOC_ERROR:
767 if (severity == OPAL_EEH_SEV_IOC_DEAD) {
768 list_for_each_entry(hose, &hose_list,
770 phb = hose->private_data;
771 phb->eeh_state |= PNV_EEH_STATE_REMOVED;
774 pr_err("EEH: dead IOC detected\n");
775 ret = EEH_NEXT_ERR_DEAD_IOC;
776 } else if (severity == OPAL_EEH_SEV_INF) {
777 pr_info("EEH: IOC informative error "
779 ioda_eeh_hub_diag(hose);
780 ret = EEH_NEXT_ERR_NONE;
784 case OPAL_EEH_PHB_ERROR:
785 if (severity == OPAL_EEH_SEV_PHB_DEAD) {
786 if (ioda_eeh_get_phb_pe(hose, pe))
789 pr_err("EEH: dead PHB#%x detected\n",
790 hose->global_number);
791 phb->eeh_state |= PNV_EEH_STATE_REMOVED;
792 ret = EEH_NEXT_ERR_DEAD_PHB;
793 } else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
794 if (ioda_eeh_get_phb_pe(hose, pe))
797 pr_err("EEH: fenced PHB#%x detected\n",
798 hose->global_number);
799 ret = EEH_NEXT_ERR_FENCED_PHB;
800 } else if (severity == OPAL_EEH_SEV_INF) {
801 pr_info("EEH: PHB#%x informative error "
803 hose->global_number);
804 ioda_eeh_phb_diag(hose);
805 ret = EEH_NEXT_ERR_NONE;
809 case OPAL_EEH_PE_ERROR:
811 * If we can't find the corresponding PE, the
812 * PEEV / PEST would be messy. So we force an
813 * fenced PHB so that it can be recovered.
815 if (ioda_eeh_get_pe(hose, frozen_pe_no, pe)) {
816 if (!ioda_eeh_get_phb_pe(hose, pe)) {
817 pr_err("EEH: Escalated fenced PHB#%x "
818 "detected for PE#%llx\n",
821 ret = EEH_NEXT_ERR_FENCED_PHB;
823 ret = EEH_NEXT_ERR_NONE;
826 pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
827 (*pe)->addr, (*pe)->phb->global_number);
828 ret = EEH_NEXT_ERR_FROZEN_PE;
833 pr_warn("%s: Unexpected error type %d\n",
838 * If we have no errors on the specific PHB or only
839 * informative error there, we continue poking it.
840 * Otherwise, we need actions to be taken by upper
843 if (ret > EEH_NEXT_ERR_INF)
850 struct pnv_eeh_ops ioda_eeh_ops = {
851 .post_init = ioda_eeh_post_init,
852 .set_option = ioda_eeh_set_option,
853 .get_state = ioda_eeh_get_state,
854 .reset = ioda_eeh_reset,
855 .get_log = ioda_eeh_get_log,
856 .configure_bridge = ioda_eeh_configure_bridge,
857 .next_error = ioda_eeh_next_error