2 * MPC5200 General Purpose Timer device driver
4 * Copyright (c) 2009 Secret Lab Technologies Ltd.
5 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * This file is a driver for the the General Purpose Timer (gpt) devices
13 * found on the MPC5200 SoC. Each timer has an IO pin which can be used
14 * for GPIO or can be used to raise interrupts. The timer function can
15 * be used independently from the IO pin, or it can be used to control
16 * output signals or measure input signals.
18 * This driver supports the GPIO and IRQ controller functions of the GPT
19 * device. Timer functions are not yet supported.
21 * The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used,
22 * this prevents the use of any gpt0 gpt function (i.e. they will fail with
23 * -EBUSY). Thus, the safety wdt function always has precedence over the gpt
24 * function. If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT,
25 * this means that gpt0 is locked in wdt mode until the next reboot - this
26 * may be a requirement in safety applications.
28 * To use the GPIO function, the following two properties must be added
29 * to the device tree node for the gpt device (typically in the .dts file
32 * #gpio-cells = < 2 >;
33 * This driver will register the GPIO pin if it finds the gpio-controller
34 * property in the device tree.
36 * To use the IRQ controller function, the following two properties must
37 * be added to the device tree node for the gpt device:
38 * interrupt-controller;
39 * #interrupt-cells = < 1 >;
40 * The IRQ controller binding only uses one cell to specify the interrupt,
41 * and the IRQ flags are encoded in the cell. A cell is not used to encode
42 * the IRQ number because the GPT only has a single IRQ source. For flags,
43 * a value of '1' means rising edge sensitive and '2' means falling edge.
45 * The GPIO and the IRQ controller functions can be used at the same time,
46 * but in this use case the IO line will only work as an input. Trying to
47 * use it as a GPIO output will not work.
49 * When using the GPIO line as an output, it can either be driven as normal
50 * IO, or it can be an Open Collector (OC) output. At the moment it is the
51 * responsibility of either the bootloader or the platform setup code to set
52 * the output mode. This driver does not change the output mode setting.
55 #include <linux/device.h>
56 #include <linux/irq.h>
57 #include <linux/interrupt.h>
59 #include <linux/list.h>
60 #include <linux/mutex.h>
62 #include <linux/of_platform.h>
63 #include <linux/of_gpio.h>
64 #include <linux/kernel.h>
65 #include <linux/slab.h>
67 #include <linux/watchdog.h>
68 #include <linux/miscdevice.h>
69 #include <linux/uaccess.h>
70 #include <asm/div64.h>
71 #include <asm/mpc52xx.h>
73 MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
74 MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß");
75 MODULE_LICENSE("GPL");
78 * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
79 * @dev: pointer to device structure
80 * @regs: virtual address of GPT registers
81 * @lock: spinlock to coordinate between different functions.
82 * @gc: gpio_chip instance structure; used when GPIO is enabled
83 * @irqhost: Pointer to irq_host instance; used when IRQ mode is supported
84 * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
85 * if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
86 * if the timer is actively used as wdt which blocks gpt functions
88 struct mpc52xx_gpt_priv {
89 struct list_head list; /* List of all GPT devices */
91 struct mpc52xx_gpt __iomem *regs;
93 struct irq_host *irqhost;
97 #if defined(CONFIG_GPIOLIB)
102 LIST_HEAD(mpc52xx_gpt_list);
103 DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
105 #define MPC52xx_GPT_MODE_MS_MASK (0x07)
106 #define MPC52xx_GPT_MODE_MS_IC (0x01)
107 #define MPC52xx_GPT_MODE_MS_OC (0x02)
108 #define MPC52xx_GPT_MODE_MS_PWM (0x03)
109 #define MPC52xx_GPT_MODE_MS_GPIO (0x04)
111 #define MPC52xx_GPT_MODE_GPIO_MASK (0x30)
112 #define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20)
113 #define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30)
115 #define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000)
116 #define MPC52xx_GPT_MODE_CONTINUOUS (0x0400)
117 #define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200)
118 #define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
119 #define MPC52xx_GPT_MODE_WDT_EN (0x8000)
121 #define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
122 #define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
123 #define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
124 #define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
126 #define MPC52xx_GPT_MODE_WDT_PING (0xa5)
128 #define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
130 #define MPC52xx_GPT_CAN_WDT (1 << 0)
131 #define MPC52xx_GPT_IS_WDT (1 << 1)
134 /* ---------------------------------------------------------------------
135 * Cascaded interrupt controller hooks
138 static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
140 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
143 spin_lock_irqsave(&gpt->lock, flags);
144 setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
145 spin_unlock_irqrestore(&gpt->lock, flags);
148 static void mpc52xx_gpt_irq_mask(struct irq_data *d)
150 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
153 spin_lock_irqsave(&gpt->lock, flags);
154 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
155 spin_unlock_irqrestore(&gpt->lock, flags);
158 static void mpc52xx_gpt_irq_ack(struct irq_data *d)
160 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
162 out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
165 static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type)
167 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
171 dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type);
173 spin_lock_irqsave(&gpt->lock, flags);
174 reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
175 if (flow_type & IRQF_TRIGGER_RISING)
176 reg |= MPC52xx_GPT_MODE_ICT_RISING;
177 if (flow_type & IRQF_TRIGGER_FALLING)
178 reg |= MPC52xx_GPT_MODE_ICT_FALLING;
179 out_be32(&gpt->regs->mode, reg);
180 spin_unlock_irqrestore(&gpt->lock, flags);
185 static struct irq_chip mpc52xx_gpt_irq_chip = {
186 .name = "MPC52xx GPT",
187 .irq_unmask = mpc52xx_gpt_irq_unmask,
188 .irq_mask = mpc52xx_gpt_irq_mask,
189 .irq_ack = mpc52xx_gpt_irq_ack,
190 .irq_set_type = mpc52xx_gpt_irq_set_type,
193 void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc)
195 struct mpc52xx_gpt_priv *gpt = get_irq_data(virq);
199 status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
201 sub_virq = irq_linear_revmap(gpt->irqhost, 0);
202 generic_handle_irq(sub_virq);
206 static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq,
209 struct mpc52xx_gpt_priv *gpt = h->host_data;
211 dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
212 set_irq_chip_data(virq, gpt);
213 set_irq_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
218 static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct,
219 const u32 *intspec, unsigned int intsize,
220 irq_hw_number_t *out_hwirq,
221 unsigned int *out_flags)
223 struct mpc52xx_gpt_priv *gpt = h->host_data;
225 dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
227 if ((intsize < 1) || (intspec[0] > 3)) {
228 dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name);
232 *out_hwirq = 0; /* The GPT only has 1 IRQ line */
233 *out_flags = intspec[0];
238 static struct irq_host_ops mpc52xx_gpt_irq_ops = {
239 .map = mpc52xx_gpt_irq_map,
240 .xlate = mpc52xx_gpt_irq_xlate,
244 mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
250 cascade_virq = irq_of_parse_and_map(node, 0);
254 gpt->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1,
255 &mpc52xx_gpt_irq_ops, -1);
257 dev_err(gpt->dev, "irq_alloc_host() failed\n");
261 gpt->irqhost->host_data = gpt;
262 set_irq_data(cascade_virq, gpt);
263 set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
265 /* If the GPT is currently disabled, then change it to be in Input
266 * Capture mode. If the mode is non-zero, then the pin could be
267 * already in use for something. */
268 spin_lock_irqsave(&gpt->lock, flags);
269 mode = in_be32(&gpt->regs->mode);
270 if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
271 out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
272 spin_unlock_irqrestore(&gpt->lock, flags);
274 dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
278 /* ---------------------------------------------------------------------
281 #if defined(CONFIG_GPIOLIB)
282 static inline struct mpc52xx_gpt_priv *gc_to_mpc52xx_gpt(struct gpio_chip *gc)
284 return container_of(gc, struct mpc52xx_gpt_priv, gc);
287 static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
289 struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
291 return (in_be32(&gpt->regs->status) >> 8) & 1;
295 mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
297 struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
301 dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
302 r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
304 spin_lock_irqsave(&gpt->lock, flags);
305 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
306 spin_unlock_irqrestore(&gpt->lock, flags);
309 static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
311 struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
314 dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
316 spin_lock_irqsave(&gpt->lock, flags);
317 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
318 spin_unlock_irqrestore(&gpt->lock, flags);
324 mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
326 mpc52xx_gpt_gpio_set(gc, gpio, val);
331 mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
335 /* Only setup GPIO if the device tree claims the GPT is
336 * a GPIO controller */
337 if (!of_find_property(node, "gpio-controller", NULL))
340 gpt->gc.label = kstrdup(node->full_name, GFP_KERNEL);
341 if (!gpt->gc.label) {
342 dev_err(gpt->dev, "out of memory\n");
347 gpt->gc.direction_input = mpc52xx_gpt_gpio_dir_in;
348 gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
349 gpt->gc.get = mpc52xx_gpt_gpio_get;
350 gpt->gc.set = mpc52xx_gpt_gpio_set;
352 gpt->gc.of_node = node;
354 /* Setup external pin in GPIO mode */
355 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
356 MPC52xx_GPT_MODE_MS_GPIO);
358 rc = gpiochip_add(&gpt->gc);
360 dev_err(gpt->dev, "gpiochip_add() failed; rc=%i\n", rc);
362 dev_dbg(gpt->dev, "%s() complete.\n", __func__);
364 #else /* defined(CONFIG_GPIOLIB) */
366 mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { }
367 #endif /* defined(CONFIG_GPIOLIB) */
369 /***********************************************************************
374 * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
375 * @irq: irq of timer.
377 struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq)
379 struct mpc52xx_gpt_priv *gpt;
380 struct list_head *pos;
382 /* Iterate over the list of timers looking for a matching device */
383 mutex_lock(&mpc52xx_gpt_list_mutex);
384 list_for_each(pos, &mpc52xx_gpt_list) {
385 gpt = container_of(pos, struct mpc52xx_gpt_priv, list);
386 if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) {
387 mutex_unlock(&mpc52xx_gpt_list_mutex);
391 mutex_unlock(&mpc52xx_gpt_list_mutex);
395 EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
397 static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,
398 int continuous, int as_wdt)
405 clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS;
406 set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
408 clear |= MPC52xx_GPT_MODE_IRQ_EN;
409 set |= MPC52xx_GPT_MODE_WDT_EN;
410 } else if (continuous)
411 set |= MPC52xx_GPT_MODE_CONTINUOUS;
413 /* Determine the number of clocks in the requested period. 64 bit
414 * arithmatic is done here to preserve the precision until the value
415 * is scaled back down into the u32 range. Period is in 'ns', bus
416 * frequency is in Hz. */
417 clocks = period * (u64)gpt->ipb_freq;
418 do_div(clocks, 1000000000); /* Scale it down to ns range */
420 /* This device cannot handle a clock count greater than 32 bits */
421 if (clocks > 0xffffffff)
424 /* Calculate the prescaler and count values from the clocks value.
425 * 'clocks' is the number of clock ticks in the period. The timer
426 * has 16 bit precision and a 16 bit prescaler. Prescaler is
427 * calculated by integer dividing the clocks by 0x10000 (shifting
428 * down 16 bits) to obtain the smallest possible divisor for clocks
429 * to get a 16 bit count value.
431 * Note: the prescale register is '1' based, not '0' based. ie. a
432 * value of '1' means divide the clock by one. 0xffff divides the
433 * clock by 0xffff. '0x0000' does not divide by zero, but wraps
434 * around and divides by 0x10000. That is why prescale must be
435 * a u32 variable, not a u16, for this calculation. */
436 prescale = (clocks >> 16) + 1;
437 do_div(clocks, prescale);
438 if (clocks > 0xffff) {
439 pr_err("calculation error; prescale:%x clocks:%llx\n",
444 /* Set and enable the timer, reject an attempt to use a wdt as gpt */
445 spin_lock_irqsave(&gpt->lock, flags);
447 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
448 else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
449 spin_unlock_irqrestore(&gpt->lock, flags);
452 out_be32(&gpt->regs->count, prescale << 16 | clocks);
453 clrsetbits_be32(&gpt->regs->mode, clear, set);
454 spin_unlock_irqrestore(&gpt->lock, flags);
460 * mpc52xx_gpt_start_timer - Set and enable the GPT timer
461 * @gpt: Pointer to gpt private data structure
462 * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
463 * @continuous: set to 1 to make timer continuous free running
465 * An interrupt will be generated every time the timer fires
467 int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
470 return mpc52xx_gpt_do_start(gpt, period, continuous, 0);
472 EXPORT_SYMBOL(mpc52xx_gpt_start_timer);
475 * mpc52xx_gpt_stop_timer - Stop a gpt
476 * @gpt: Pointer to gpt private data structure
478 * Returns an error if attempting to stop a wdt
480 int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
484 /* reject the operation if the timer is used as watchdog (gpt 0 only) */
485 spin_lock_irqsave(&gpt->lock, flags);
486 if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
487 spin_unlock_irqrestore(&gpt->lock, flags);
491 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
492 spin_unlock_irqrestore(&gpt->lock, flags);
495 EXPORT_SYMBOL(mpc52xx_gpt_stop_timer);
498 * mpc52xx_gpt_timer_period - Read the timer period
499 * @gpt: Pointer to gpt private data structure
501 * Returns the timer period in ns
503 u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)
509 spin_lock_irqsave(&gpt->lock, flags);
510 period = in_be32(&gpt->regs->count);
511 spin_unlock_irqrestore(&gpt->lock, flags);
513 prescale = period >> 16;
517 period = period * prescale * 1000000000ULL;
518 do_div(period, (u64)gpt->ipb_freq);
521 EXPORT_SYMBOL(mpc52xx_gpt_timer_period);
523 #if defined(CONFIG_MPC5200_WDT)
524 /***********************************************************************
525 * Watchdog API for gpt0
528 #define WDT_IDENTITY "mpc52xx watchdog on GPT0"
530 /* wdt_is_active stores wether or not the /dev/watchdog device is opened */
531 static unsigned long wdt_is_active;
533 /* wdt-capable gpt */
534 static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt;
536 /* low-level wdt functions */
537 static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt)
541 spin_lock_irqsave(&gpt_wdt->lock, flags);
542 out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING);
543 spin_unlock_irqrestore(&gpt_wdt->lock, flags);
546 /* wdt misc device api */
547 static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data,
548 size_t len, loff_t *ppos)
550 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
551 mpc52xx_gpt_wdt_ping(gpt_wdt);
555 static const struct watchdog_info mpc5200_wdt_info = {
556 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
557 .identity = WDT_IDENTITY,
560 static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd,
563 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
564 int __user *data = (int __user *)arg;
570 case WDIOC_GETSUPPORT:
571 ret = copy_to_user(data, &mpc5200_wdt_info,
572 sizeof(mpc5200_wdt_info));
577 case WDIOC_GETSTATUS:
578 case WDIOC_GETBOOTSTATUS:
579 ret = put_user(0, data);
582 case WDIOC_KEEPALIVE:
583 mpc52xx_gpt_wdt_ping(gpt_wdt);
586 case WDIOC_SETTIMEOUT:
587 ret = get_user(timeout, data);
590 real_timeout = (u64) timeout * 1000000000ULL;
591 ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1);
594 /* fall through and return the timeout */
596 case WDIOC_GETTIMEOUT:
597 /* we need to round here as to avoid e.g. the following
599 * - timeout requested is 1 second;
600 * - real timeout @33MHz is 999997090ns
601 * - the int divide by 10^9 will return 0.
604 mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL;
605 do_div(real_timeout, 1000000000ULL);
606 timeout = (int) real_timeout;
607 ret = put_user(timeout, data);
616 static int mpc52xx_wdt_open(struct inode *inode, struct file *file)
621 if (!mpc52xx_gpt_wdt)
624 /* /dev/watchdog can only be opened once */
625 if (test_and_set_bit(0, &wdt_is_active))
628 /* Set and activate the watchdog with 30 seconds timeout */
629 ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL,
632 clear_bit(0, &wdt_is_active);
636 file->private_data = mpc52xx_gpt_wdt;
637 return nonseekable_open(inode, file);
640 static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
642 /* note: releasing the wdt in NOWAYOUT-mode does not stop it */
643 #if !defined(CONFIG_WATCHDOG_NOWAYOUT)
644 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
647 spin_lock_irqsave(&gpt_wdt->lock, flags);
648 clrbits32(&gpt_wdt->regs->mode,
649 MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
650 gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
651 spin_unlock_irqrestore(&gpt_wdt->lock, flags);
653 clear_bit(0, &wdt_is_active);
658 static const struct file_operations mpc52xx_wdt_fops = {
659 .owner = THIS_MODULE,
661 .write = mpc52xx_wdt_write,
662 .unlocked_ioctl = mpc52xx_wdt_ioctl,
663 .open = mpc52xx_wdt_open,
664 .release = mpc52xx_wdt_release,
667 static struct miscdevice mpc52xx_wdt_miscdev = {
668 .minor = WATCHDOG_MINOR,
670 .fops = &mpc52xx_wdt_fops,
673 static int __devinit mpc52xx_gpt_wdt_init(void)
677 /* try to register the watchdog misc device */
678 err = misc_register(&mpc52xx_wdt_miscdev);
680 pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY);
682 pr_info("%s: watchdog device registered\n", WDT_IDENTITY);
686 static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
691 /* remember the gpt for the wdt operation */
692 mpc52xx_gpt_wdt = gpt;
694 /* configure the wdt if the device tree contained a timeout */
695 if (!period || *period == 0)
698 real_timeout = (u64) *period * 1000000000ULL;
699 if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1))
700 dev_warn(gpt->dev, "starting as wdt failed\n");
702 dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
708 static int __devinit mpc52xx_gpt_wdt_init(void)
713 static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
719 #endif /* CONFIG_MPC5200_WDT */
721 /* ---------------------------------------------------------------------
722 * of_platform bus binding code
724 static int __devinit mpc52xx_gpt_probe(struct platform_device *ofdev,
725 const struct of_device_id *match)
727 struct mpc52xx_gpt_priv *gpt;
729 gpt = kzalloc(sizeof *gpt, GFP_KERNEL);
733 spin_lock_init(&gpt->lock);
734 gpt->dev = &ofdev->dev;
735 gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
736 gpt->regs = of_iomap(ofdev->dev.of_node, 0);
742 dev_set_drvdata(&ofdev->dev, gpt);
744 mpc52xx_gpt_gpio_setup(gpt, ofdev->dev.of_node);
745 mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node);
747 mutex_lock(&mpc52xx_gpt_list_mutex);
748 list_add(&gpt->list, &mpc52xx_gpt_list);
749 mutex_unlock(&mpc52xx_gpt_list_mutex);
751 /* check if this device could be a watchdog */
752 if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) ||
753 of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) {
754 const u32 *on_boot_wdt;
756 gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
757 on_boot_wdt = of_get_property(ofdev->dev.of_node,
758 "fsl,wdt-on-boot", NULL);
760 dev_info(gpt->dev, "used as watchdog\n");
761 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
763 dev_info(gpt->dev, "can function as watchdog\n");
764 mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt);
770 static int mpc52xx_gpt_remove(struct platform_device *ofdev)
775 static const struct of_device_id mpc52xx_gpt_match[] = {
776 { .compatible = "fsl,mpc5200-gpt", },
778 /* Depreciated compatible values; don't use for new dts files */
779 { .compatible = "fsl,mpc5200-gpt-gpio", },
780 { .compatible = "mpc5200-gpt", },
784 static struct of_platform_driver mpc52xx_gpt_driver = {
786 .name = "mpc52xx-gpt",
787 .owner = THIS_MODULE,
788 .of_match_table = mpc52xx_gpt_match,
790 .probe = mpc52xx_gpt_probe,
791 .remove = mpc52xx_gpt_remove,
794 static int __init mpc52xx_gpt_init(void)
796 if (of_register_platform_driver(&mpc52xx_gpt_driver))
797 pr_err("error registering MPC52xx GPT driver\n");
802 /* Make sure GPIOs and IRQs get set up before anyone tries to use them */
803 subsys_initcall(mpc52xx_gpt_init);
804 device_initcall(mpc52xx_gpt_wdt_init);