2 * Performance event support - powerpc architecture code
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/perf_event.h>
14 #include <linux/percpu.h>
15 #include <linux/hardirq.h>
18 #include <asm/machdep.h>
19 #include <asm/firmware.h>
20 #include <asm/ptrace.h>
22 struct cpu_hw_events {
29 struct perf_event *event[MAX_HWEVENTS];
30 u64 events[MAX_HWEVENTS];
31 unsigned int flags[MAX_HWEVENTS];
32 unsigned long mmcr[3];
33 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
34 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
35 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
36 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
37 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
39 unsigned int group_flag;
42 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
44 struct power_pmu *ppmu;
47 * Normally, to ignore kernel events we set the FCS (freeze counters
48 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
49 * hypervisor bit set in the MSR, or if we are running on a processor
50 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
51 * then we need to use the FCHV bit to ignore kernel events.
53 static unsigned int freeze_events_kernel = MMCR0_FCS;
56 * 32-bit doesn't have MMCRA but does have an MMCR2,
57 * and a few other names are different.
62 #define MMCR0_PMCjCE MMCR0_PMCnCE
64 #define SPRN_MMCRA SPRN_MMCR2
65 #define MMCRA_SAMPLE_ENABLE 0
67 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
71 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { }
72 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
76 static inline void perf_read_regs(struct pt_regs *regs) { }
77 static inline int perf_intr_is_nmi(struct pt_regs *regs)
82 #endif /* CONFIG_PPC32 */
85 * Things that are specific to 64-bit implementations.
89 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
91 unsigned long mmcra = regs->dsisr;
93 if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) {
94 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
96 return 4 * (slot - 1);
102 * The user wants a data address recorded.
103 * If we're not doing instruction sampling, give them the SDAR
104 * (sampled data address). If we are doing instruction sampling, then
105 * only give them the SDAR if it corresponds to the instruction
106 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC
109 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
111 unsigned long mmcra = regs->dsisr;
112 unsigned long sdsync = (ppmu->flags & PPMU_ALT_SIPR) ?
113 POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC;
115 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync))
116 *addrp = mfspr(SPRN_SDAR);
119 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
121 if (regs->msr & MSR_PR)
122 return PERF_RECORD_MISC_USER;
123 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
124 return PERF_RECORD_MISC_HYPERVISOR;
125 return PERF_RECORD_MISC_KERNEL;
128 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
130 unsigned long mmcra = regs->dsisr;
131 unsigned long sihv = MMCRA_SIHV;
132 unsigned long sipr = MMCRA_SIPR;
134 /* Not a PMU interrupt: Make up flags from regs->msr */
135 if (TRAP(regs) != 0xf00)
136 return perf_flags_from_msr(regs);
139 * If we don't support continuous sampling and this
140 * is not a marked event, same deal
142 if ((ppmu->flags & PPMU_NO_CONT_SAMPLING) &&
143 !(mmcra & MMCRA_SAMPLE_ENABLE))
144 return perf_flags_from_msr(regs);
147 * If we don't have flags in MMCRA, rather than using
148 * the MSR, we intuit the flags from the address in
149 * SIAR which should give slightly more reliable
152 if (ppmu->flags & PPMU_NO_SIPR) {
153 unsigned long siar = mfspr(SPRN_SIAR);
154 if (siar >= PAGE_OFFSET)
155 return PERF_RECORD_MISC_KERNEL;
156 return PERF_RECORD_MISC_USER;
159 if (ppmu->flags & PPMU_ALT_SIPR) {
160 sihv = POWER6_MMCRA_SIHV;
161 sipr = POWER6_MMCRA_SIPR;
164 /* PR has priority over HV, so order below is important */
166 return PERF_RECORD_MISC_USER;
167 if ((mmcra & sihv) && (freeze_events_kernel != MMCR0_FCHV))
168 return PERF_RECORD_MISC_HYPERVISOR;
169 return PERF_RECORD_MISC_KERNEL;
173 * Overload regs->dsisr to store MMCRA so we only need to read it once
176 static inline void perf_read_regs(struct pt_regs *regs)
178 regs->dsisr = mfspr(SPRN_MMCRA);
182 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
185 static inline int perf_intr_is_nmi(struct pt_regs *regs)
190 #endif /* CONFIG_PPC64 */
192 static void perf_event_interrupt(struct pt_regs *regs);
194 void perf_event_print_debug(void)
199 * Read one performance monitor counter (PMC).
201 static unsigned long read_pmc(int idx)
207 val = mfspr(SPRN_PMC1);
210 val = mfspr(SPRN_PMC2);
213 val = mfspr(SPRN_PMC3);
216 val = mfspr(SPRN_PMC4);
219 val = mfspr(SPRN_PMC5);
222 val = mfspr(SPRN_PMC6);
226 val = mfspr(SPRN_PMC7);
229 val = mfspr(SPRN_PMC8);
231 #endif /* CONFIG_PPC64 */
233 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
242 static void write_pmc(int idx, unsigned long val)
246 mtspr(SPRN_PMC1, val);
249 mtspr(SPRN_PMC2, val);
252 mtspr(SPRN_PMC3, val);
255 mtspr(SPRN_PMC4, val);
258 mtspr(SPRN_PMC5, val);
261 mtspr(SPRN_PMC6, val);
265 mtspr(SPRN_PMC7, val);
268 mtspr(SPRN_PMC8, val);
270 #endif /* CONFIG_PPC64 */
272 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
277 * Check if a set of events can all go on the PMU at once.
278 * If they can't, this will look at alternative codes for the events
279 * and see if any combination of alternative codes is feasible.
280 * The feasible set is returned in event_id[].
282 static int power_check_constraints(struct cpu_hw_events *cpuhw,
283 u64 event_id[], unsigned int cflags[],
286 unsigned long mask, value, nv;
287 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
288 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
290 unsigned long addf = ppmu->add_fields;
291 unsigned long tadd = ppmu->test_adder;
293 if (n_ev > ppmu->n_counter)
296 /* First see if the events will go on as-is */
297 for (i = 0; i < n_ev; ++i) {
298 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
299 && !ppmu->limited_pmc_event(event_id[i])) {
300 ppmu->get_alternatives(event_id[i], cflags[i],
301 cpuhw->alternatives[i]);
302 event_id[i] = cpuhw->alternatives[i][0];
304 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
305 &cpuhw->avalues[i][0]))
309 for (i = 0; i < n_ev; ++i) {
310 nv = (value | cpuhw->avalues[i][0]) +
311 (value & cpuhw->avalues[i][0] & addf);
312 if ((((nv + tadd) ^ value) & mask) != 0 ||
313 (((nv + tadd) ^ cpuhw->avalues[i][0]) &
314 cpuhw->amasks[i][0]) != 0)
317 mask |= cpuhw->amasks[i][0];
320 return 0; /* all OK */
322 /* doesn't work, gather alternatives... */
323 if (!ppmu->get_alternatives)
325 for (i = 0; i < n_ev; ++i) {
327 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
328 cpuhw->alternatives[i]);
329 for (j = 1; j < n_alt[i]; ++j)
330 ppmu->get_constraint(cpuhw->alternatives[i][j],
331 &cpuhw->amasks[i][j],
332 &cpuhw->avalues[i][j]);
335 /* enumerate all possibilities and see if any will work */
338 value = mask = nv = 0;
341 /* we're backtracking, restore context */
347 * See if any alternative k for event_id i,
348 * where k > j, will satisfy the constraints.
350 while (++j < n_alt[i]) {
351 nv = (value | cpuhw->avalues[i][j]) +
352 (value & cpuhw->avalues[i][j] & addf);
353 if ((((nv + tadd) ^ value) & mask) == 0 &&
354 (((nv + tadd) ^ cpuhw->avalues[i][j])
355 & cpuhw->amasks[i][j]) == 0)
360 * No feasible alternative, backtrack
361 * to event_id i-1 and continue enumerating its
362 * alternatives from where we got up to.
368 * Found a feasible alternative for event_id i,
369 * remember where we got up to with this event_id,
370 * go on to the next event_id, and start with
371 * the first alternative for it.
377 mask |= cpuhw->amasks[i][j];
383 /* OK, we have a feasible combination, tell the caller the solution */
384 for (i = 0; i < n_ev; ++i)
385 event_id[i] = cpuhw->alternatives[i][choice[i]];
390 * Check if newly-added events have consistent settings for
391 * exclude_{user,kernel,hv} with each other and any previously
394 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
395 int n_prev, int n_new)
397 int eu = 0, ek = 0, eh = 0;
399 struct perf_event *event;
406 for (i = 0; i < n; ++i) {
407 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
408 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
413 eu = event->attr.exclude_user;
414 ek = event->attr.exclude_kernel;
415 eh = event->attr.exclude_hv;
417 } else if (event->attr.exclude_user != eu ||
418 event->attr.exclude_kernel != ek ||
419 event->attr.exclude_hv != eh) {
425 for (i = 0; i < n; ++i)
426 if (cflags[i] & PPMU_LIMITED_PMC_OK)
427 cflags[i] |= PPMU_LIMITED_PMC_REQD;
432 static u64 check_and_compute_delta(u64 prev, u64 val)
434 u64 delta = (val - prev) & 0xfffffffful;
437 * POWER7 can roll back counter values, if the new value is smaller
438 * than the previous value it will cause the delta and the counter to
439 * have bogus values unless we rolled a counter over. If a coutner is
440 * rolled back, it will be smaller, but within 256, which is the maximum
441 * number of events to rollback at once. If we dectect a rollback
442 * return 0. This can lead to a small lack of precision in the
445 if (prev > val && (prev - val) < 256)
451 static void power_pmu_read(struct perf_event *event)
453 s64 val, delta, prev;
455 if (event->hw.state & PERF_HES_STOPPED)
461 * Performance monitor interrupts come even when interrupts
462 * are soft-disabled, as long as interrupts are hard-enabled.
463 * Therefore we treat them like NMIs.
466 prev = local64_read(&event->hw.prev_count);
468 val = read_pmc(event->hw.idx);
469 delta = check_and_compute_delta(prev, val);
472 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
474 local64_add(delta, &event->count);
475 local64_sub(delta, &event->hw.period_left);
479 * On some machines, PMC5 and PMC6 can't be written, don't respect
480 * the freeze conditions, and don't generate interrupts. This tells
481 * us if `event' is using such a PMC.
483 static int is_limited_pmc(int pmcnum)
485 return (ppmu->flags & PPMU_LIMITED_PMC5_6)
486 && (pmcnum == 5 || pmcnum == 6);
489 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
490 unsigned long pmc5, unsigned long pmc6)
492 struct perf_event *event;
493 u64 val, prev, delta;
496 for (i = 0; i < cpuhw->n_limited; ++i) {
497 event = cpuhw->limited_counter[i];
500 val = (event->hw.idx == 5) ? pmc5 : pmc6;
501 prev = local64_read(&event->hw.prev_count);
503 delta = check_and_compute_delta(prev, val);
505 local64_add(delta, &event->count);
509 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
510 unsigned long pmc5, unsigned long pmc6)
512 struct perf_event *event;
516 for (i = 0; i < cpuhw->n_limited; ++i) {
517 event = cpuhw->limited_counter[i];
518 event->hw.idx = cpuhw->limited_hwidx[i];
519 val = (event->hw.idx == 5) ? pmc5 : pmc6;
520 prev = local64_read(&event->hw.prev_count);
521 if (check_and_compute_delta(prev, val))
522 local64_set(&event->hw.prev_count, val);
523 perf_event_update_userpage(event);
528 * Since limited events don't respect the freeze conditions, we
529 * have to read them immediately after freezing or unfreezing the
530 * other events. We try to keep the values from the limited
531 * events as consistent as possible by keeping the delay (in
532 * cycles and instructions) between freezing/unfreezing and reading
533 * the limited events as small and consistent as possible.
534 * Therefore, if any limited events are in use, we read them
535 * both, and always in the same order, to minimize variability,
536 * and do it inside the same asm that writes MMCR0.
538 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
540 unsigned long pmc5, pmc6;
542 if (!cpuhw->n_limited) {
543 mtspr(SPRN_MMCR0, mmcr0);
548 * Write MMCR0, then read PMC5 and PMC6 immediately.
549 * To ensure we don't get a performance monitor interrupt
550 * between writing MMCR0 and freezing/thawing the limited
551 * events, we first write MMCR0 with the event overflow
552 * interrupt enable bits turned off.
554 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
555 : "=&r" (pmc5), "=&r" (pmc6)
556 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
558 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
560 if (mmcr0 & MMCR0_FC)
561 freeze_limited_counters(cpuhw, pmc5, pmc6);
563 thaw_limited_counters(cpuhw, pmc5, pmc6);
566 * Write the full MMCR0 including the event overflow interrupt
567 * enable bits, if necessary.
569 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
570 mtspr(SPRN_MMCR0, mmcr0);
574 * Disable all events to prevent PMU interrupts and to allow
575 * events to be added or removed.
577 static void power_pmu_disable(struct pmu *pmu)
579 struct cpu_hw_events *cpuhw;
584 local_irq_save(flags);
585 cpuhw = &__get_cpu_var(cpu_hw_events);
587 if (!cpuhw->disabled) {
592 * Check if we ever enabled the PMU on this cpu.
594 if (!cpuhw->pmcs_enabled) {
596 cpuhw->pmcs_enabled = 1;
600 * Disable instruction sampling if it was enabled
602 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
604 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
609 * Set the 'freeze counters' bit.
610 * The barrier is to make sure the mtspr has been
611 * executed and the PMU has frozen the events
614 write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC);
617 local_irq_restore(flags);
621 * Re-enable all events if disable == 0.
622 * If we were previously disabled and events were added, then
623 * put the new config on the PMU.
625 static void power_pmu_enable(struct pmu *pmu)
627 struct perf_event *event;
628 struct cpu_hw_events *cpuhw;
633 unsigned int hwc_index[MAX_HWEVENTS];
639 local_irq_save(flags);
640 cpuhw = &__get_cpu_var(cpu_hw_events);
641 if (!cpuhw->disabled) {
642 local_irq_restore(flags);
648 * If we didn't change anything, or only removed events,
649 * no need to recalculate MMCR* settings and reset the PMCs.
650 * Just reenable the PMU with the current MMCR* settings
651 * (possibly updated for removal of events).
653 if (!cpuhw->n_added) {
654 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
655 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
656 if (cpuhw->n_events == 0)
657 ppc_set_pmu_inuse(0);
662 * Compute MMCR* values for the new set of events
664 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
666 /* shouldn't ever get here */
667 printk(KERN_ERR "oops compute_mmcr failed\n");
672 * Add in MMCR0 freeze bits corresponding to the
673 * attr.exclude_* bits for the first event.
674 * We have already checked that all events have the
675 * same values for these bits as the first event.
677 event = cpuhw->event[0];
678 if (event->attr.exclude_user)
679 cpuhw->mmcr[0] |= MMCR0_FCP;
680 if (event->attr.exclude_kernel)
681 cpuhw->mmcr[0] |= freeze_events_kernel;
682 if (event->attr.exclude_hv)
683 cpuhw->mmcr[0] |= MMCR0_FCHV;
686 * Write the new configuration to MMCR* with the freeze
687 * bit set and set the hardware events to their initial values.
688 * Then unfreeze the events.
690 ppc_set_pmu_inuse(1);
691 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
692 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
693 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
697 * Read off any pre-existing events that need to move
700 for (i = 0; i < cpuhw->n_events; ++i) {
701 event = cpuhw->event[i];
702 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
703 power_pmu_read(event);
704 write_pmc(event->hw.idx, 0);
710 * Initialize the PMCs for all the new and moved events.
712 cpuhw->n_limited = n_lim = 0;
713 for (i = 0; i < cpuhw->n_events; ++i) {
714 event = cpuhw->event[i];
717 idx = hwc_index[i] + 1;
718 if (is_limited_pmc(idx)) {
719 cpuhw->limited_counter[n_lim] = event;
720 cpuhw->limited_hwidx[n_lim] = idx;
725 if (event->hw.sample_period) {
726 left = local64_read(&event->hw.period_left);
727 if (left < 0x80000000L)
728 val = 0x80000000L - left;
730 local64_set(&event->hw.prev_count, val);
732 if (event->hw.state & PERF_HES_STOPPED)
735 perf_event_update_userpage(event);
737 cpuhw->n_limited = n_lim;
738 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
742 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
745 * Enable instruction sampling if necessary
747 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
749 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
753 local_irq_restore(flags);
756 static int collect_events(struct perf_event *group, int max_count,
757 struct perf_event *ctrs[], u64 *events,
761 struct perf_event *event;
763 if (!is_software_event(group)) {
767 flags[n] = group->hw.event_base;
768 events[n++] = group->hw.config;
770 list_for_each_entry(event, &group->sibling_list, group_entry) {
771 if (!is_software_event(event) &&
772 event->state != PERF_EVENT_STATE_OFF) {
776 flags[n] = event->hw.event_base;
777 events[n++] = event->hw.config;
784 * Add a event to the PMU.
785 * If all events are not already frozen, then we disable and
786 * re-enable the PMU in order to get hw_perf_enable to do the
787 * actual work of reconfiguring the PMU.
789 static int power_pmu_add(struct perf_event *event, int ef_flags)
791 struct cpu_hw_events *cpuhw;
796 local_irq_save(flags);
797 perf_pmu_disable(event->pmu);
800 * Add the event to the list (if there is room)
801 * and check whether the total set is still feasible.
803 cpuhw = &__get_cpu_var(cpu_hw_events);
804 n0 = cpuhw->n_events;
805 if (n0 >= ppmu->n_counter)
807 cpuhw->event[n0] = event;
808 cpuhw->events[n0] = event->hw.config;
809 cpuhw->flags[n0] = event->hw.event_base;
811 if (!(ef_flags & PERF_EF_START))
812 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
815 * If group events scheduling transaction was started,
816 * skip the schedulability test here, it will be performed
817 * at commit time(->commit_txn) as a whole
819 if (cpuhw->group_flag & PERF_EVENT_TXN)
822 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
824 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
826 event->hw.config = cpuhw->events[n0];
834 perf_pmu_enable(event->pmu);
835 local_irq_restore(flags);
840 * Remove a event from the PMU.
842 static void power_pmu_del(struct perf_event *event, int ef_flags)
844 struct cpu_hw_events *cpuhw;
848 local_irq_save(flags);
849 perf_pmu_disable(event->pmu);
851 power_pmu_read(event);
853 cpuhw = &__get_cpu_var(cpu_hw_events);
854 for (i = 0; i < cpuhw->n_events; ++i) {
855 if (event == cpuhw->event[i]) {
856 while (++i < cpuhw->n_events) {
857 cpuhw->event[i-1] = cpuhw->event[i];
858 cpuhw->events[i-1] = cpuhw->events[i];
859 cpuhw->flags[i-1] = cpuhw->flags[i];
862 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
864 write_pmc(event->hw.idx, 0);
867 perf_event_update_userpage(event);
871 for (i = 0; i < cpuhw->n_limited; ++i)
872 if (event == cpuhw->limited_counter[i])
874 if (i < cpuhw->n_limited) {
875 while (++i < cpuhw->n_limited) {
876 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
877 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
881 if (cpuhw->n_events == 0) {
882 /* disable exceptions if no events are running */
883 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
886 perf_pmu_enable(event->pmu);
887 local_irq_restore(flags);
891 * POWER-PMU does not support disabling individual counters, hence
892 * program their cycle counter to their max value and ignore the interrupts.
895 static void power_pmu_start(struct perf_event *event, int ef_flags)
901 if (!event->hw.idx || !event->hw.sample_period)
904 if (!(event->hw.state & PERF_HES_STOPPED))
907 if (ef_flags & PERF_EF_RELOAD)
908 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
910 local_irq_save(flags);
911 perf_pmu_disable(event->pmu);
914 left = local64_read(&event->hw.period_left);
917 if (left < 0x80000000L)
918 val = 0x80000000L - left;
920 write_pmc(event->hw.idx, val);
922 perf_event_update_userpage(event);
923 perf_pmu_enable(event->pmu);
924 local_irq_restore(flags);
927 static void power_pmu_stop(struct perf_event *event, int ef_flags)
931 if (!event->hw.idx || !event->hw.sample_period)
934 if (event->hw.state & PERF_HES_STOPPED)
937 local_irq_save(flags);
938 perf_pmu_disable(event->pmu);
940 power_pmu_read(event);
941 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
942 write_pmc(event->hw.idx, 0);
944 perf_event_update_userpage(event);
945 perf_pmu_enable(event->pmu);
946 local_irq_restore(flags);
950 * Start group events scheduling transaction
951 * Set the flag to make pmu::enable() not perform the
952 * schedulability test, it will be performed at commit time
954 void power_pmu_start_txn(struct pmu *pmu)
956 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
958 perf_pmu_disable(pmu);
959 cpuhw->group_flag |= PERF_EVENT_TXN;
960 cpuhw->n_txn_start = cpuhw->n_events;
964 * Stop group events scheduling transaction
965 * Clear the flag and pmu::enable() will perform the
966 * schedulability test.
968 void power_pmu_cancel_txn(struct pmu *pmu)
970 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
972 cpuhw->group_flag &= ~PERF_EVENT_TXN;
973 perf_pmu_enable(pmu);
977 * Commit group events scheduling transaction
978 * Perform the group schedulability test as a whole
979 * Return 0 if success
981 int power_pmu_commit_txn(struct pmu *pmu)
983 struct cpu_hw_events *cpuhw;
988 cpuhw = &__get_cpu_var(cpu_hw_events);
990 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
992 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
996 for (i = cpuhw->n_txn_start; i < n; ++i)
997 cpuhw->event[i]->hw.config = cpuhw->events[i];
999 cpuhw->group_flag &= ~PERF_EVENT_TXN;
1000 perf_pmu_enable(pmu);
1005 * Return 1 if we might be able to put event on a limited PMC,
1007 * A event can only go on a limited PMC if it counts something
1008 * that a limited PMC can count, doesn't require interrupts, and
1009 * doesn't exclude any processor mode.
1011 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1015 u64 alt[MAX_EVENT_ALTERNATIVES];
1017 if (event->attr.exclude_user
1018 || event->attr.exclude_kernel
1019 || event->attr.exclude_hv
1020 || event->attr.sample_period)
1023 if (ppmu->limited_pmc_event(ev))
1027 * The requested event_id isn't on a limited PMC already;
1028 * see if any alternative code goes on a limited PMC.
1030 if (!ppmu->get_alternatives)
1033 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1034 n = ppmu->get_alternatives(ev, flags, alt);
1040 * Find an alternative event_id that goes on a normal PMC, if possible,
1041 * and return the event_id code, or 0 if there is no such alternative.
1042 * (Note: event_id code 0 is "don't count" on all machines.)
1044 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1046 u64 alt[MAX_EVENT_ALTERNATIVES];
1049 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1050 n = ppmu->get_alternatives(ev, flags, alt);
1056 /* Number of perf_events counting hardware events */
1057 static atomic_t num_events;
1058 /* Used to avoid races in calling reserve/release_pmc_hardware */
1059 static DEFINE_MUTEX(pmc_reserve_mutex);
1062 * Release the PMU if this is the last perf_event.
1064 static void hw_perf_event_destroy(struct perf_event *event)
1066 if (!atomic_add_unless(&num_events, -1, 1)) {
1067 mutex_lock(&pmc_reserve_mutex);
1068 if (atomic_dec_return(&num_events) == 0)
1069 release_pmc_hardware();
1070 mutex_unlock(&pmc_reserve_mutex);
1075 * Translate a generic cache event_id config to a raw event_id code.
1077 static int hw_perf_cache_event(u64 config, u64 *eventp)
1079 unsigned long type, op, result;
1082 if (!ppmu->cache_events)
1086 type = config & 0xff;
1087 op = (config >> 8) & 0xff;
1088 result = (config >> 16) & 0xff;
1090 if (type >= PERF_COUNT_HW_CACHE_MAX ||
1091 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1092 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1095 ev = (*ppmu->cache_events)[type][op][result];
1104 static int power_pmu_event_init(struct perf_event *event)
1107 unsigned long flags;
1108 struct perf_event *ctrs[MAX_HWEVENTS];
1109 u64 events[MAX_HWEVENTS];
1110 unsigned int cflags[MAX_HWEVENTS];
1113 struct cpu_hw_events *cpuhw;
1118 /* does not support taken branch sampling */
1119 if (has_branch_stack(event))
1122 switch (event->attr.type) {
1123 case PERF_TYPE_HARDWARE:
1124 ev = event->attr.config;
1125 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1127 ev = ppmu->generic_events[ev];
1129 case PERF_TYPE_HW_CACHE:
1130 err = hw_perf_cache_event(event->attr.config, &ev);
1135 ev = event->attr.config;
1141 event->hw.config_base = ev;
1145 * If we are not running on a hypervisor, force the
1146 * exclude_hv bit to 0 so that we don't care what
1147 * the user set it to.
1149 if (!firmware_has_feature(FW_FEATURE_LPAR))
1150 event->attr.exclude_hv = 0;
1153 * If this is a per-task event, then we can use
1154 * PM_RUN_* events interchangeably with their non RUN_*
1155 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1156 * XXX we should check if the task is an idle task.
1159 if (event->attach_state & PERF_ATTACH_TASK)
1160 flags |= PPMU_ONLY_COUNT_RUN;
1163 * If this machine has limited events, check whether this
1164 * event_id could go on a limited event.
1166 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1167 if (can_go_on_limited_pmc(event, ev, flags)) {
1168 flags |= PPMU_LIMITED_PMC_OK;
1169 } else if (ppmu->limited_pmc_event(ev)) {
1171 * The requested event_id is on a limited PMC,
1172 * but we can't use a limited PMC; see if any
1173 * alternative goes on a normal PMC.
1175 ev = normal_pmc_alternative(ev, flags);
1182 * If this is in a group, check if it can go on with all the
1183 * other hardware events in the group. We assume the event
1184 * hasn't been linked into its leader's sibling list at this point.
1187 if (event->group_leader != event) {
1188 n = collect_events(event->group_leader, ppmu->n_counter - 1,
1189 ctrs, events, cflags);
1196 if (check_excludes(ctrs, cflags, n, 1))
1199 cpuhw = &get_cpu_var(cpu_hw_events);
1200 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1201 put_cpu_var(cpu_hw_events);
1205 event->hw.config = events[n];
1206 event->hw.event_base = cflags[n];
1207 event->hw.last_period = event->hw.sample_period;
1208 local64_set(&event->hw.period_left, event->hw.last_period);
1211 * See if we need to reserve the PMU.
1212 * If no events are currently in use, then we have to take a
1213 * mutex to ensure that we don't race with another task doing
1214 * reserve_pmc_hardware or release_pmc_hardware.
1217 if (!atomic_inc_not_zero(&num_events)) {
1218 mutex_lock(&pmc_reserve_mutex);
1219 if (atomic_read(&num_events) == 0 &&
1220 reserve_pmc_hardware(perf_event_interrupt))
1223 atomic_inc(&num_events);
1224 mutex_unlock(&pmc_reserve_mutex);
1226 event->destroy = hw_perf_event_destroy;
1231 static int power_pmu_event_idx(struct perf_event *event)
1233 return event->hw.idx;
1236 struct pmu power_pmu = {
1237 .pmu_enable = power_pmu_enable,
1238 .pmu_disable = power_pmu_disable,
1239 .event_init = power_pmu_event_init,
1240 .add = power_pmu_add,
1241 .del = power_pmu_del,
1242 .start = power_pmu_start,
1243 .stop = power_pmu_stop,
1244 .read = power_pmu_read,
1245 .start_txn = power_pmu_start_txn,
1246 .cancel_txn = power_pmu_cancel_txn,
1247 .commit_txn = power_pmu_commit_txn,
1248 .event_idx = power_pmu_event_idx,
1252 * A counter has overflowed; update its count and record
1253 * things if requested. Note that interrupts are hard-disabled
1254 * here so there is no possibility of being interrupted.
1256 static void record_and_restart(struct perf_event *event, unsigned long val,
1257 struct pt_regs *regs)
1259 u64 period = event->hw.sample_period;
1260 s64 prev, delta, left;
1263 if (event->hw.state & PERF_HES_STOPPED) {
1264 write_pmc(event->hw.idx, 0);
1268 /* we don't have to worry about interrupts here */
1269 prev = local64_read(&event->hw.prev_count);
1270 delta = check_and_compute_delta(prev, val);
1271 local64_add(delta, &event->count);
1274 * See if the total period for this event has expired,
1275 * and update for the next period.
1278 left = local64_read(&event->hw.period_left) - delta;
1285 event->hw.last_period = event->hw.sample_period;
1287 if (left < 0x80000000LL)
1288 val = 0x80000000LL - left;
1291 write_pmc(event->hw.idx, val);
1292 local64_set(&event->hw.prev_count, val);
1293 local64_set(&event->hw.period_left, left);
1294 perf_event_update_userpage(event);
1297 * Finally record data if requested.
1300 struct perf_sample_data data;
1302 perf_sample_data_init(&data, ~0ULL);
1303 data.period = event->hw.last_period;
1305 if (event->attr.sample_type & PERF_SAMPLE_ADDR)
1306 perf_get_data_addr(regs, &data.addr);
1308 if (perf_event_overflow(event, &data, regs))
1309 power_pmu_stop(event, 0);
1314 * Called from generic code to get the misc flags (i.e. processor mode)
1317 unsigned long perf_misc_flags(struct pt_regs *regs)
1319 u32 flags = perf_get_misc_flags(regs);
1323 return user_mode(regs) ? PERF_RECORD_MISC_USER :
1324 PERF_RECORD_MISC_KERNEL;
1328 * Called from generic code to get the instruction pointer
1331 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1333 unsigned long mmcra = regs->dsisr;
1335 /* Not a PMU interrupt */
1336 if (TRAP(regs) != 0xf00)
1339 /* Processor doesn't support sampling non marked events */
1340 if ((ppmu->flags & PPMU_NO_CONT_SAMPLING) &&
1341 !(mmcra & MMCRA_SAMPLE_ENABLE))
1344 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
1347 static bool pmc_overflow(unsigned long val)
1353 * Events on POWER7 can roll back if a speculative event doesn't
1354 * eventually complete. Unfortunately in some rare cases they will
1355 * raise a performance monitor exception. We need to catch this to
1356 * ensure we reset the PMC. In all cases the PMC will be 256 or less
1357 * cycles from overflow.
1359 * We only do this if the first pass fails to find any overflowing
1360 * PMCs because a user might set a period of less than 256 and we
1361 * don't want to mistakenly reset them.
1363 if (__is_processor(PV_POWER7) && ((0x80000000 - val) <= 256))
1370 * Performance monitor interrupt stuff
1372 static void perf_event_interrupt(struct pt_regs *regs)
1375 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1376 struct perf_event *event;
1381 if (cpuhw->n_limited)
1382 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
1385 perf_read_regs(regs);
1387 nmi = perf_intr_is_nmi(regs);
1393 for (i = 0; i < cpuhw->n_events; ++i) {
1394 event = cpuhw->event[i];
1395 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
1397 val = read_pmc(event->hw.idx);
1399 /* event has overflowed */
1401 record_and_restart(event, val, regs);
1406 * In case we didn't find and reset the event that caused
1407 * the interrupt, scan all events and reset any that are
1408 * negative, to avoid getting continual interrupts.
1409 * Any that we processed in the previous loop will not be negative.
1412 for (i = 0; i < ppmu->n_counter; ++i) {
1413 if (is_limited_pmc(i + 1))
1415 val = read_pmc(i + 1);
1416 if (pmc_overflow(val))
1417 write_pmc(i + 1, 0);
1422 * Reset MMCR0 to its normal value. This will set PMXE and
1423 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
1424 * and thus allow interrupts to occur again.
1425 * XXX might want to use MSR.PM to keep the events frozen until
1426 * we get back out of this interrupt.
1428 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
1436 static void power_pmu_setup(int cpu)
1438 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
1442 memset(cpuhw, 0, sizeof(*cpuhw));
1443 cpuhw->mmcr[0] = MMCR0_FC;
1446 static int __cpuinit
1447 power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1449 unsigned int cpu = (long)hcpu;
1451 switch (action & ~CPU_TASKS_FROZEN) {
1452 case CPU_UP_PREPARE:
1453 power_pmu_setup(cpu);
1463 int __cpuinit register_power_pmu(struct power_pmu *pmu)
1466 return -EBUSY; /* something's already registered */
1469 pr_info("%s performance monitor hardware support registered\n",
1474 * Use FCHV to ignore kernel events if MSR.HV is set.
1476 if (mfmsr() & MSR_HV)
1477 freeze_events_kernel = MMCR0_FCHV;
1478 #endif /* CONFIG_PPC64 */
1480 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
1481 perf_cpu_notifier(power_pmu_notifier);