2 * Low level TLB miss handlers for Book3E
4 * Copyright (C) 2008-2009
5 * Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <asm/processor.h>
17 #include <asm/ppc_asm.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/cputable.h>
20 #include <asm/pgtable.h>
21 #include <asm/exception-64e.h>
22 #include <asm/ppc-opcode.h>
23 #include <asm/kvm_asm.h>
24 #include <asm/kvm_booke_hv_asm.h>
26 #ifdef CONFIG_PPC_64K_PAGES
27 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1)
29 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE)
31 #define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE)
32 #define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
33 #define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
35 /**********************************************************************
37 * TLB miss handling for Book3E with a bolted linear mapping *
38 * No virtual page table, no nested TLB misses *
40 **********************************************************************/
42 .macro tlb_prolog_bolted intnum addr
43 mtspr SPRN_SPRG_GEN_SCRATCH,r13
44 mfspr r13,SPRN_SPRG_PACA
45 std r10,PACA_EXTLB+EX_TLB_R10(r13)
47 std r11,PACA_EXTLB+EX_TLB_R11(r13)
48 #ifdef CONFIG_KVM_BOOKE_HV
51 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
53 DO_KVM \intnum, SPRN_SRR1
54 std r16,PACA_EXTLB+EX_TLB_R16(r13)
55 mfspr r16,\addr /* get faulting address */
56 std r14,PACA_EXTLB+EX_TLB_R14(r13)
58 std r15,PACA_EXTLB+EX_TLB_R15(r13)
59 std r10,PACA_EXTLB+EX_TLB_CR(r13)
60 TLB_MISS_PROLOG_STATS_BOLTED
63 .macro tlb_epilog_bolted
64 ld r14,PACA_EXTLB+EX_TLB_CR(r13)
65 ld r10,PACA_EXTLB+EX_TLB_R10(r13)
66 ld r11,PACA_EXTLB+EX_TLB_R11(r13)
68 ld r14,PACA_EXTLB+EX_TLB_R14(r13)
69 ld r15,PACA_EXTLB+EX_TLB_R15(r13)
70 TLB_MISS_RESTORE_STATS_BOLTED
71 ld r16,PACA_EXTLB+EX_TLB_R16(r13)
72 mfspr r13,SPRN_SPRG_GEN_SCRATCH
76 START_EXCEPTION(data_tlb_miss_bolted)
77 tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
79 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
81 /* We do the user/kernel test for the PID here along with the RW test
83 /* We pre-test some combination of permissions to avoid double
86 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
87 * ESR_ST is 0x00800000
88 * _PAGE_BAP_SW is 0x00000010
89 * So the shift is >> 19. This tests for supervisor writeability.
90 * If the page happens to be supervisor writeable and not user
91 * writeable, we will take a new fault later, but that should be
94 * We also move ESR_ST in _PAGE_DIRTY position
95 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
97 * MAS1 is preset for all we need except for TID that needs to
98 * be cleared for kernel translations
103 srdi r15,r16,60 /* get region */
104 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
105 bne- dtlb_miss_fault_bolted /* Bail if fault addr is invalid */
107 rlwinm r10,r11,32-19,27,27
108 rlwimi r10,r11,32-16,19,19
109 cmpwi r15,0 /* user vs kernel check */
110 ori r10,r10,_PAGE_PRESENT
111 oris r11,r10,_PAGE_ACCESSED@h
113 TLB_MISS_STATS_SAVE_INFO_BOLTED
114 bne tlb_miss_kernel_bolted
116 tlb_miss_common_bolted:
118 * This is the guts of the TLB miss handler for bolted-linear.
119 * We are entered with:
121 * r16 = faulting address
122 * r15 = crap (free to use)
123 * r14 = page table base
125 * r11 = PTE permission mask
126 * r10 = crap (free to use)
128 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
131 beq tlb_miss_fault_bolted /* No PGDIR, bail */
133 BEGIN_MMU_FTR_SECTION
134 /* Set the TLB reservation and search for existing entry. Then load
137 PPC_TLBSRX_DOT(0,R16)
138 ldx r14,r14,r15 /* grab pgd entry */
139 beq tlb_miss_done_bolted /* tlb exists already, bail */
141 ldx r14,r14,r15 /* grab pgd entry */
142 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
144 #ifndef CONFIG_PPC_64K_PAGES
145 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
148 bge tlb_miss_fault_bolted /* Bad pgd entry or hugepage; bail */
149 ldx r14,r14,r15 /* grab pud entry */
150 #endif /* CONFIG_PPC_64K_PAGES */
152 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
155 bge tlb_miss_fault_bolted
156 ldx r14,r14,r15 /* Grab pmd entry */
158 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
161 bge tlb_miss_fault_bolted
162 ldx r14,r14,r15 /* Grab PTE, normal (!huge) page */
164 /* Check if required permissions are met */
166 rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
167 bne- tlb_miss_fault_bolted
169 /* Now we build the MAS:
171 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
172 * MAS 1 : Almost fully setup
173 * - PID already updated by caller if necessary
174 * - TSIZE need change if !base page size, not
175 * yet implemented for now
176 * MAS 2 : Defaults not useful, need to be redone
177 * MAS 3+7 : Needs to be done
179 clrrdi r11,r16,12 /* Clear low crap in EA */
180 clrldi r15,r15,12 /* Clear crap at the top */
181 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
182 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
184 andi. r11,r14,_PAGE_DIRTY
185 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
187 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
189 li r11,MAS3_SW|MAS3_UW
192 mtspr SPRN_MAS7_MAS3,r15
195 tlb_miss_done_bolted:
196 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
200 itlb_miss_kernel_bolted:
201 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
202 oris r11,r11,_PAGE_ACCESSED@h
203 tlb_miss_kernel_bolted:
205 ld r14,PACA_KERNELPGD(r13)
206 cmpldi cr0,r15,8 /* Check for vmalloc region */
207 rlwinm r10,r10,0,16,1 /* Clear TID */
209 beq+ tlb_miss_common_bolted
211 tlb_miss_fault_bolted:
212 /* We need to check if it was an instruction miss */
213 andi. r10,r11,_PAGE_EXEC|_PAGE_BAP_SX
214 bne itlb_miss_fault_bolted
215 dtlb_miss_fault_bolted:
216 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
218 b exc_data_storage_book3e
219 itlb_miss_fault_bolted:
220 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
222 b exc_instruction_storage_book3e
224 /* Instruction TLB miss */
225 START_EXCEPTION(instruction_tlb_miss_bolted)
226 tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
228 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
229 srdi r15,r16,60 /* get region */
230 TLB_MISS_STATS_SAVE_INFO_BOLTED
231 bne- itlb_miss_fault_bolted
233 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
235 /* We do the user/kernel test for the PID here along with the RW test
238 cmpldi cr0,r15,0 /* Check for user region */
239 oris r11,r11,_PAGE_ACCESSED@h
240 beq tlb_miss_common_bolted
241 b itlb_miss_kernel_bolted
243 #ifdef CONFIG_PPC_FSL_BOOK3E
245 * TLB miss handling for e6500 and derivatives, using hardware tablewalk.
247 * Linear mapping is bolted: no virtual page table or nested TLB misses
248 * Indirect entries in TLB1, hardware loads resulting direct entries
250 * No HES or NV hint on TLB1, so we need to do software round-robin
251 * No tlbsrx. so we need a spinlock, and we have to deal
252 * with MAS-damage caused by tlbsx
256 START_EXCEPTION(instruction_tlb_miss_e6500)
257 tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
259 ld r11,PACA_TCD_PTR(r13)
260 srdi. r15,r16,60 /* get region */
263 TLB_MISS_STATS_SAVE_INFO_BOLTED
264 bne tlb_miss_kernel_e6500 /* user/kernel test */
266 b tlb_miss_common_e6500
268 START_EXCEPTION(data_tlb_miss_e6500)
269 tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
271 ld r11,PACA_TCD_PTR(r13)
272 srdi. r15,r16,60 /* get region */
275 TLB_MISS_STATS_SAVE_INFO_BOLTED
276 bne tlb_miss_kernel_e6500 /* user vs kernel check */
279 * This is the guts of the TLB miss handler for e6500 and derivatives.
280 * We are entered with:
282 * r16 = page of faulting address (low bit 0 if data, 1 if instruction)
283 * r15 = crap (free to use)
284 * r14 = page table base
286 * r11 = tlb_per_core ptr
287 * r10 = crap (free to use)
289 tlb_miss_common_e6500:
291 * Search if we already have an indirect entry for that virtual
292 * address, and if we do, bail out.
294 * MAS6:IND should be already set based on MAS4
296 addi r10,r11,TCD_LOCK
314 andis. r10,r10,MAS1_VALID@h
315 bne tlb_miss_done_e6500
317 /* Undo MAS-damage from the tlbsx */
319 oris r10,r10,MAS1_VALID@h
323 /* Now, we need to walk the page tables. First check if we are in
326 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
327 bne- tlb_miss_fault_e6500
329 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
332 beq- tlb_miss_fault_e6500 /* No PGDIR, bail */
333 ldx r14,r14,r15 /* grab pgd entry */
335 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
338 bge tlb_miss_fault_e6500 /* Bad pgd entry or hugepage; bail */
339 ldx r14,r14,r15 /* grab pud entry */
341 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
344 bge tlb_miss_fault_e6500
345 ldx r14,r14,r15 /* Grab pmd entry */
349 bge tlb_miss_fault_e6500
351 /* Now we build the MAS for a 2M indirect page:
353 * MAS 0 : ESEL needs to be filled by software round-robin
354 * MAS 1 : Fully set up
355 * - PID already updated by caller if necessary
356 * - TSIZE for now is base ind page size always
357 * - TID already cleared if necessary
358 * MAS 2 : Default not 2M-aligned, need to be redone
359 * MAS 3+7 : Needs to be done
362 ori r14,r14,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
363 mtspr SPRN_MAS7_MAS3,r14
365 clrrdi r15,r16,21 /* make EA 2M-aligned */
368 lbz r15,TCD_ESEL_NEXT(r11)
369 lbz r16,TCD_ESEL_MAX(r11)
370 lbz r14,TCD_ESEL_FIRST(r11)
371 rlwimi r10,r15,16,0x00ff0000 /* insert esel_next into MAS0 */
372 addi r15,r15,1 /* increment esel_next */
375 iseleq r15,r14,r15 /* if next == last use first */
376 stb r15,TCD_ESEL_NEXT(r11)
381 .macro tlb_unlock_e6500
384 stb r15,TCD_LOCK(r11)
388 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
392 tlb_miss_kernel_e6500:
394 ld r14,PACA_KERNELPGD(r13)
395 cmpldi cr0,r15,8 /* Check for vmalloc region */
396 rlwinm r10,r10,0,16,1 /* Clear TID */
398 beq+ tlb_miss_common_e6500
400 tlb_miss_fault_e6500:
402 /* We need to check if it was an instruction miss */
404 bne itlb_miss_fault_e6500
405 dtlb_miss_fault_e6500:
406 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
408 b exc_data_storage_book3e
409 itlb_miss_fault_e6500:
410 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
412 b exc_instruction_storage_book3e
413 #endif /* CONFIG_PPC_FSL_BOOK3E */
415 /**********************************************************************
417 * TLB miss handling for Book3E with TLB reservation and HES support *
419 **********************************************************************/
423 START_EXCEPTION(data_tlb_miss)
426 /* Now we handle the fault proper. We only save DEAR in normal
427 * fault case since that's the only interesting values here.
428 * We could probably also optimize by not saving SRR0/1 in the
429 * linear mapping case but I'll leave that for later
432 mfspr r16,SPRN_DEAR /* get faulting address */
433 srdi r15,r16,60 /* get region */
434 cmpldi cr0,r15,0xc /* linear mapping ? */
435 TLB_MISS_STATS_SAVE_INFO
436 beq tlb_load_linear /* yes -> go to linear map load */
438 /* The page tables are mapped virtually linear. At this point, though,
439 * we don't know whether we are trying to fault in a first level
440 * virtual address or a virtual page table address. We can get that
441 * from bit 0x1 of the region ID which we have set for a page table
444 bne- virt_page_table_tlb_miss
446 std r14,EX_TLB_ESR(r12); /* save ESR */
447 std r16,EX_TLB_DEAR(r12); /* save DEAR */
449 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
451 oris r11,r11,_PAGE_ACCESSED@h
453 /* We do the user/kernel test for the PID here along with the RW test
455 cmpldi cr0,r15,0 /* Check for user region */
457 /* We pre-test some combination of permissions to avoid double
460 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
461 * ESR_ST is 0x00800000
462 * _PAGE_BAP_SW is 0x00000010
463 * So the shift is >> 19. This tests for supervisor writeability.
464 * If the page happens to be supervisor writeable and not user
465 * writeable, we will take a new fault later, but that should be
466 * a rare enough case.
468 * We also move ESR_ST in _PAGE_DIRTY position
469 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
471 * MAS1 is preset for all we need except for TID that needs to
472 * be cleared for kernel translations
474 rlwimi r11,r14,32-19,27,27
475 rlwimi r11,r14,32-16,19,19
477 /* XXX replace the RMW cycles with immediate loads + writes */
478 1: mfspr r10,SPRN_MAS1
479 cmpldi cr0,r15,8 /* Check for vmalloc region */
480 rlwinm r10,r10,0,16,1 /* Clear TID */
484 /* We got a crappy address, just fault with whatever DEAR and ESR
487 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
488 TLB_MISS_EPILOG_ERROR
489 b exc_data_storage_book3e
491 /* Instruction TLB miss */
492 START_EXCEPTION(instruction_tlb_miss)
495 /* If we take a recursive fault, the second level handler may need
496 * to know whether we are handling a data or instruction fault in
497 * order to get to the right store fault handler. We provide that
498 * info by writing a crazy value in ESR in our exception frame
500 li r14,-1 /* store to exception frame is done later */
502 /* Now we handle the fault proper. We only save DEAR in the non
503 * linear mapping case since we know the linear mapping case will
504 * not re-enter. We could indeed optimize and also not save SRR0/1
505 * in the linear mapping case but I'll leave that for later
507 * Faulting address is SRR0 which is already in r16
509 srdi r15,r16,60 /* get region */
510 cmpldi cr0,r15,0xc /* linear mapping ? */
511 TLB_MISS_STATS_SAVE_INFO
512 beq tlb_load_linear /* yes -> go to linear map load */
514 /* We do the user/kernel test for the PID here along with the RW test
516 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
517 oris r11,r11,_PAGE_ACCESSED@h
519 cmpldi cr0,r15,0 /* Check for user region */
520 std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */
523 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
524 oris r11,r11,_PAGE_ACCESSED@h
525 /* XXX replace the RMW cycles with immediate loads + writes */
527 cmpldi cr0,r15,8 /* Check for vmalloc region */
528 rlwinm r10,r10,0,16,1 /* Clear TID */
532 /* We got a crappy address, just fault */
533 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
534 TLB_MISS_EPILOG_ERROR
535 b exc_instruction_storage_book3e
538 * This is the guts of the first-level TLB miss handler for direct
539 * misses. We are entered with:
541 * r16 = faulting address
543 * r14 = crap (free to use)
545 * r12 = TLB exception frame in PACA
546 * r11 = PTE permission mask
547 * r10 = crap (free to use)
550 /* So we first construct the page table address. We do that by
551 * shifting the bottom of the address (not the region ID) by
552 * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and
553 * or'ing the fourth high bit.
555 * NOTE: For 64K pages, we do things slightly differently in
556 * order to handle the weird page table format used by linux
559 #ifdef CONFIG_PPC_64K_PAGES
560 /* For the top bits, 16 bytes per PTE */
561 rldicl r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4
562 /* Now create the bottom bits as 0 in position 0x8000 and
563 * the rest calculated for 8 bytes per PTE
565 rldicl r15,r16,64-(PAGE_SHIFT-3),64-15
566 /* Insert the bottom bits in */
567 rlwimi r14,r15,0,16,31
569 rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
575 BEGIN_MMU_FTR_SECTION
576 /* Set the TLB reservation and search for existing entry. Then load
579 PPC_TLBSRX_DOT(0,R16)
581 beq normal_tlb_miss_done
584 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
586 finish_normal_tlb_miss:
587 /* Check if required permissions are met */
589 bne- normal_tlb_miss_access_fault
591 /* Now we build the MAS:
593 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
594 * MAS 1 : Almost fully setup
595 * - PID already updated by caller if necessary
596 * - TSIZE need change if !base page size, not
597 * yet implemented for now
598 * MAS 2 : Defaults not useful, need to be redone
599 * MAS 3+7 : Needs to be done
601 * TODO: mix up code below for better scheduling
603 clrrdi r11,r16,12 /* Clear low crap in EA */
604 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
607 /* Check page size, if not standard, update MAS1 */
608 rldicl r11,r14,64-8,64-8
609 #ifdef CONFIG_PPC_64K_PAGES
610 cmpldi cr0,r11,BOOK3E_PAGESZ_64K
612 cmpldi cr0,r11,BOOK3E_PAGESZ_4K
616 rlwimi r11,r14,31,21,24
617 rlwinm r11,r11,0,21,19
620 /* Move RPN in position */
621 rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
622 clrldi r15,r11,12 /* Clear crap at the top */
623 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
624 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
626 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
627 andi. r11,r14,_PAGE_DIRTY
629 li r11,MAS3_SW|MAS3_UW
632 BEGIN_MMU_FTR_SECTION
637 mtspr SPRN_MAS7_MAS3,r15
638 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
642 normal_tlb_miss_done:
643 /* We don't bother with restoring DEAR or ESR since we know we are
644 * level 0 and just going back to userland. They are only needed
645 * if you are going to take an access fault
647 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
648 TLB_MISS_EPILOG_SUCCESS
651 normal_tlb_miss_access_fault:
652 /* We need to check if it was an instruction miss */
653 andi. r10,r11,_PAGE_EXEC
655 ld r14,EX_TLB_DEAR(r12)
656 ld r15,EX_TLB_ESR(r12)
659 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
660 TLB_MISS_EPILOG_ERROR
661 b exc_data_storage_book3e
662 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
663 TLB_MISS_EPILOG_ERROR
664 b exc_instruction_storage_book3e
668 * This is the guts of the second-level TLB miss handler for direct
669 * misses. We are entered with:
671 * r16 = virtual page table faulting address
672 * r15 = region (top 4 bits of address)
673 * r14 = crap (free to use)
675 * r12 = TLB exception frame in PACA
676 * r11 = crap (free to use)
677 * r10 = crap (free to use)
679 * Note that this should only ever be called as a second level handler
680 * with the current scheme when using SW load.
681 * That means we can always get the original fault DEAR at
682 * EX_TLB_DEAR-EX_TLB_SIZE(r12)
684 * It can be re-entered by the linear mapping miss handler. However, to
685 * avoid too much complication, it will restart the whole fault at level
686 * 0 so we don't care too much about clobbers
688 * XXX That code was written back when we couldn't clobber r14. We can now,
689 * so we could probably optimize things a bit
691 virt_page_table_tlb_miss:
692 /* Are we hitting a kernel page table ? */
695 /* The cool thing now is that r10 contains 0 for user and 8 for kernel,
696 * and we happen to have the swapper_pg_dir at offset 8 from the user
697 * pgdir in the PACA :-).
701 /* If kernel, we need to clear MAS1 TID */
703 /* XXX replace the RMW cycles with immediate loads + writes */
705 rlwinm r10,r10,0,16,1 /* Clear TID */
708 BEGIN_MMU_FTR_SECTION
709 /* Search if we already have a TLB entry for that virtual address, and
710 * if we do, bail out.
712 PPC_TLBSRX_DOT(0,R16)
713 beq virt_page_table_tlb_miss_done
714 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
716 /* Now, we need to walk the page tables. First check if we are in
719 rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4
720 bne- virt_page_table_tlb_miss_fault
722 /* Get the PGD pointer */
725 beq- virt_page_table_tlb_miss_fault
727 /* Get to PGD entry */
728 rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3
732 bge virt_page_table_tlb_miss_fault
734 #ifndef CONFIG_PPC_64K_PAGES
735 /* Get to PUD entry */
736 rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
740 bge virt_page_table_tlb_miss_fault
741 #endif /* CONFIG_PPC_64K_PAGES */
743 /* Get to PMD entry */
744 rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
748 bge virt_page_table_tlb_miss_fault
750 /* Ok, we're all right, we can now create a kernel translation for
751 * a 4K or 64K page from r16 -> r15.
753 /* Now we build the MAS:
755 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
756 * MAS 1 : Almost fully setup
757 * - PID already updated by caller if necessary
758 * - TSIZE for now is base page size always
759 * MAS 2 : Use defaults
760 * MAS 3+7 : Needs to be done
762 * So we only do MAS 2 and 3 for now...
764 clrldi r11,r15,4 /* remove region ID from RPN */
765 ori r10,r11,1 /* Or-in SR */
767 BEGIN_MMU_FTR_SECTION
772 mtspr SPRN_MAS7_MAS3,r10
773 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
777 BEGIN_MMU_FTR_SECTION
778 virt_page_table_tlb_miss_done:
780 /* We have overriden MAS2:EPN but currently our primary TLB miss
781 * handler will always restore it so that should not be an issue,
782 * if we ever optimize the primary handler to not write MAS2 on
783 * some cases, we'll have to restore MAS2:EPN here based on the
784 * original fault's DEAR. If we do that we have to modify the
785 * ITLB miss handler to also store SRR0 in the exception frame
788 * However, one nasty thing we did is we cleared the reservation
789 * (well, potentially we did). We do a trick here thus if we
790 * are not a level 0 exception (we interrupted the TLB miss) we
791 * offset the return address by -4 in order to replay the tlbsrx
795 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
797 ld r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
799 std r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
801 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
802 /* Return to caller, normal case */
803 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK);
804 TLB_MISS_EPILOG_SUCCESS
807 virt_page_table_tlb_miss_fault:
808 /* If we fault here, things are a little bit tricky. We need to call
809 * either data or instruction store fault, and we need to retrieve
810 * the original fault address and ESR (for data).
812 * The thing is, we know that in normal circumstances, this is
813 * always called as a second level tlb miss for SW load or as a first
814 * level TLB miss for HW load, so we should be able to peek at the
815 * relevant information in the first exception frame in the PACA.
817 * However, we do need to double check that, because we may just hit
818 * a stray kernel pointer or a userland attack trying to hit those
819 * areas. If that is the case, we do a data fault. (We can't get here
820 * from an instruction tlb miss anyway).
822 * Note also that when going to a fault, we must unwind the previous
823 * level as well. Since we are doing that, we don't need to clear or
824 * restore the TLB reservation neither.
827 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
828 bne- virt_page_table_tlb_miss_whacko_fault
830 /* We dig the original DEAR and ESR from slot 0 */
831 ld r15,EX_TLB_DEAR+PACA_EXTLB(r13)
832 ld r16,EX_TLB_ESR+PACA_EXTLB(r13)
834 /* We check for the "special" ESR value for instruction faults */
839 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT);
840 TLB_MISS_EPILOG_ERROR
841 b exc_data_storage_book3e
842 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT);
843 TLB_MISS_EPILOG_ERROR
844 b exc_instruction_storage_book3e
846 virt_page_table_tlb_miss_whacko_fault:
847 /* The linear fault will restart everything so ESR and DEAR will
848 * not have been clobbered, let's just fault with what we have
850 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT);
851 TLB_MISS_EPILOG_ERROR
852 b exc_data_storage_book3e
855 /**************************************************************
857 * TLB miss handling for Book3E with hw page table support *
859 **************************************************************/
863 START_EXCEPTION(data_tlb_miss_htw)
866 /* Now we handle the fault proper. We only save DEAR in normal
867 * fault case since that's the only interesting values here.
868 * We could probably also optimize by not saving SRR0/1 in the
869 * linear mapping case but I'll leave that for later
872 mfspr r16,SPRN_DEAR /* get faulting address */
873 srdi r11,r16,60 /* get region */
874 cmpldi cr0,r11,0xc /* linear mapping ? */
875 TLB_MISS_STATS_SAVE_INFO
876 beq tlb_load_linear /* yes -> go to linear map load */
878 /* We do the user/kernel test for the PID here along with the RW test
880 cmpldi cr0,r11,0 /* Check for user region */
881 ld r15,PACAPGD(r13) /* Load user pgdir */
884 /* XXX replace the RMW cycles with immediate loads + writes */
885 1: mfspr r10,SPRN_MAS1
886 cmpldi cr0,r11,8 /* Check for vmalloc region */
887 rlwinm r10,r10,0,16,1 /* Clear TID */
889 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
892 /* We got a crappy address, just fault with whatever DEAR and ESR
895 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
896 TLB_MISS_EPILOG_ERROR
897 b exc_data_storage_book3e
899 /* Instruction TLB miss */
900 START_EXCEPTION(instruction_tlb_miss_htw)
903 /* If we take a recursive fault, the second level handler may need
904 * to know whether we are handling a data or instruction fault in
905 * order to get to the right store fault handler. We provide that
906 * info by keeping a crazy value for ESR in r14
908 li r14,-1 /* store to exception frame is done later */
910 /* Now we handle the fault proper. We only save DEAR in the non
911 * linear mapping case since we know the linear mapping case will
912 * not re-enter. We could indeed optimize and also not save SRR0/1
913 * in the linear mapping case but I'll leave that for later
915 * Faulting address is SRR0 which is already in r16
917 srdi r11,r16,60 /* get region */
918 cmpldi cr0,r11,0xc /* linear mapping ? */
919 TLB_MISS_STATS_SAVE_INFO
920 beq tlb_load_linear /* yes -> go to linear map load */
922 /* We do the user/kernel test for the PID here along with the RW test
924 cmpldi cr0,r11,0 /* Check for user region */
925 ld r15,PACAPGD(r13) /* Load user pgdir */
928 /* XXX replace the RMW cycles with immediate loads + writes */
929 1: mfspr r10,SPRN_MAS1
930 cmpldi cr0,r11,8 /* Check for vmalloc region */
931 rlwinm r10,r10,0,16,1 /* Clear TID */
933 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
936 /* We got a crappy address, just fault */
937 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
938 TLB_MISS_EPILOG_ERROR
939 b exc_instruction_storage_book3e
943 * This is the guts of the second-level TLB miss handler for direct
944 * misses. We are entered with:
946 * r16 = virtual page table faulting address
950 * r12 = TLB exception frame in PACA
951 * r11 = crap (free to use)
952 * r10 = crap (free to use)
954 * It can be re-entered by the linear mapping miss handler. However, to
955 * avoid too much complication, it will save/restore things for us
958 /* Search if we already have a TLB entry for that virtual address, and
959 * if we do, bail out.
961 * MAS1:IND should be already set based on MAS4
963 PPC_TLBSRX_DOT(0,R16)
964 beq htw_tlb_miss_done
966 /* Now, we need to walk the page tables. First check if we are in
969 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
970 bne- htw_tlb_miss_fault
972 /* Get the PGD pointer */
974 beq- htw_tlb_miss_fault
976 /* Get to PGD entry */
977 rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3
981 bge htw_tlb_miss_fault
983 #ifndef CONFIG_PPC_64K_PAGES
984 /* Get to PUD entry */
985 rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
989 bge htw_tlb_miss_fault
990 #endif /* CONFIG_PPC_64K_PAGES */
992 /* Get to PMD entry */
993 rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
997 bge htw_tlb_miss_fault
999 /* Ok, we're all right, we can now create an indirect entry for
1000 * a 1M or 256M page.
1002 * The last trick is now that because we use "half" pages for
1003 * the HTW (1M IND is 2K and 256M IND is 32K) we need to account
1004 * for an added LSB bit to the RPN. For 64K pages, there is no
1005 * problem as we already use 32K arrays (half PTE pages), but for
1006 * 4K page we need to extract a bit from the virtual address and
1007 * insert it into the "PA52" bit of the RPN.
1009 #ifndef CONFIG_PPC_64K_PAGES
1010 rlwimi r15,r16,32-9,20,20
1012 /* Now we build the MAS:
1014 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
1015 * MAS 1 : Almost fully setup
1016 * - PID already updated by caller if necessary
1017 * - TSIZE for now is base ind page size always
1018 * MAS 2 : Use defaults
1019 * MAS 3+7 : Needs to be done
1021 #ifdef CONFIG_PPC_64K_PAGES
1022 ori r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT)
1024 ori r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
1027 BEGIN_MMU_FTR_SECTION
1031 MMU_FTR_SECTION_ELSE
1032 mtspr SPRN_MAS7_MAS3,r10
1033 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
1038 /* We don't bother with restoring DEAR or ESR since we know we are
1039 * level 0 and just going back to userland. They are only needed
1040 * if you are going to take an access fault
1042 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK)
1043 TLB_MISS_EPILOG_SUCCESS
1047 /* We need to check if it was an instruction miss. We know this
1048 * though because r14 would contain -1
1054 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT)
1055 TLB_MISS_EPILOG_ERROR
1056 b exc_data_storage_book3e
1057 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT)
1058 TLB_MISS_EPILOG_ERROR
1059 b exc_instruction_storage_book3e
1062 * This is the guts of "any" level TLB miss handler for kernel linear
1063 * mapping misses. We are entered with:
1066 * r16 = faulting address
1067 * r15 = crap (free to use)
1068 * r14 = ESR (data) or -1 (instruction)
1070 * r12 = TLB exception frame in PACA
1071 * r11 = crap (free to use)
1072 * r10 = crap (free to use)
1074 * In addition we know that we will not re-enter, so in theory, we could
1075 * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later.
1077 * We also need to be careful about MAS registers here & TLB reservation,
1078 * as we know we'll have clobbered them if we interrupt the main TLB miss
1079 * handlers in which case we probably want to do a full restart at level
1080 * 0 rather than saving / restoring the MAS.
1082 * Note: If we care about performance of that core, we can easily shuffle
1083 * a few things around
1086 /* For now, we assume the linear mapping is contiguous and stops at
1087 * linear_map_top. We also assume the size is a multiple of 1G, thus
1088 * we only use 1G pages for now. That might have to be changed in a
1089 * final implementation, especially when dealing with hypervisors
1092 ld r11,linear_map_top@got(r11)
1095 bge tlb_load_linear_fault
1097 /* MAS1 need whole new setup. */
1098 li r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT)
1099 oris r15,r15,MAS1_VALID@h /* MAS1 needs V and TSIZE */
1102 /* Already somebody there ? */
1103 PPC_TLBSRX_DOT(0,R16)
1104 beq tlb_load_linear_done
1106 /* Now we build the remaining MAS. MAS0 and 2 should be fine
1107 * with their defaults, which leaves us with MAS 3 and 7. The
1108 * mapping is linear, so we just take the address, clear the
1109 * region bits, and or in the permission bits which are currently
1112 clrrdi r10,r16,30 /* 1G page index */
1113 clrldi r10,r10,4 /* clear region bits */
1114 ori r10,r10,MAS3_SR|MAS3_SW|MAS3_SX
1116 BEGIN_MMU_FTR_SECTION
1120 MMU_FTR_SECTION_ELSE
1121 mtspr SPRN_MAS7_MAS3,r10
1122 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
1126 tlb_load_linear_done:
1127 /* We use the "error" epilog for success as we do want to
1128 * restore to the initial faulting context, whatever it was.
1129 * We do that because we can't resume a fault within a TLB
1130 * miss handler, due to MAS and TLB reservation being clobbered.
1132 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR)
1133 TLB_MISS_EPILOG_ERROR
1136 tlb_load_linear_fault:
1137 /* We keep the DEAR and ESR around, this shouldn't have happened */
1140 TLB_MISS_EPILOG_ERROR_SPECIAL
1141 b exc_data_storage_book3e
1142 1: TLB_MISS_EPILOG_ERROR_SPECIAL
1143 b exc_instruction_storage_book3e
1146 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS
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