2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
32 #ifdef __LITTLE_ENDIAN__
33 #error Need to fix lppaca and SLB shadow accesses in little endian mode
36 /* Values in HSTATE_NAPPING(r13) */
37 #define NAPPING_CEDE 1
38 #define NAPPING_NOVCPU 2
41 * Call kvmppc_hv_entry in real mode.
42 * Must be called with interrupts hard-disabled.
46 * LR = return address to continue at after eventually re-enabling MMU
48 _GLOBAL(kvmppc_hv_entry_trampoline)
50 std r0, PPC_LR_STKOFF(r1)
53 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
58 mtmsrd r0,1 /* clear RI in MSR */
64 ld r4, HSTATE_KVM_VCPU(r13)
67 /* Back from guest - restore host state and return to caller */
70 /* Restore host DABR and DABRX */
71 ld r5,HSTATE_DABR(r13)
75 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
81 /* Reload the host's PMU registers */
82 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
83 lbz r4, LPPACA_PMCINUSE(r3)
85 beq 23f /* skip if not */
86 lwz r3, HSTATE_PMC(r13)
87 lwz r4, HSTATE_PMC + 4(r13)
88 lwz r5, HSTATE_PMC + 8(r13)
89 lwz r6, HSTATE_PMC + 12(r13)
90 lwz r8, HSTATE_PMC + 16(r13)
91 lwz r9, HSTATE_PMC + 20(r13)
93 lwz r10, HSTATE_PMC + 24(r13)
94 lwz r11, HSTATE_PMC + 28(r13)
95 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
105 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
106 ld r3, HSTATE_MMCR(r13)
107 ld r4, HSTATE_MMCR + 8(r13)
108 ld r5, HSTATE_MMCR + 16(r13)
116 * Reload DEC. HDEC interrupts were disabled when
117 * we reloaded the host's LPCR value.
119 ld r3, HSTATE_DECEXP(r13)
125 * For external and machine check interrupts, we need
126 * to call the Linux handler to process the interrupt.
127 * We do that by jumping to absolute address 0x500 for
128 * external interrupts, or the machine_check_fwnmi label
129 * for machine checks (since firmware might have patched
130 * the vector area at 0x200). The [h]rfid at the end of the
131 * handler will return to the book3s_hv_interrupts.S code.
132 * For other interrupts we do the rfid to get back
133 * to the book3s_hv_interrupts.S code here.
135 ld r8, 112+PPC_LR_STKOFF(r1)
137 ld r7, HSTATE_HOST_MSR(r13)
139 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
140 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
143 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
145 /* RFI into the highmem handler, or branch to interrupt handler */
149 mtmsrd r6, 1 /* Clear RI in MSR */
152 beqa 0x500 /* external interrupt (PPC970) */
153 beq cr1, 13f /* machine check */
156 /* On POWER7, we have external interrupts set to use HSRR0/1 */
157 11: mtspr SPRN_HSRR0, r8
161 13: b machine_check_fwnmi
164 kvmppc_primary_no_guest:
165 /* We handle this much like a ceded vcpu */
166 /* set our bit in napping_threads */
167 ld r5, HSTATE_KVM_VCORE(r13)
168 lbz r7, HSTATE_PTID(r13)
171 addi r6, r5, VCORE_NAPPING_THREADS
176 /* order napping_threads update vs testing entry_exit_count */
179 lwz r7, VCORE_ENTRY_EXIT(r5)
181 bge kvm_novcpu_exit /* another thread already exiting */
182 li r3, NAPPING_NOVCPU
183 stb r3, HSTATE_NAPPING(r13)
185 stb r3, HSTATE_HWTHREAD_REQ(r13)
190 ld r1, HSTATE_HOST_R1(r13)
191 ld r5, HSTATE_KVM_VCORE(r13)
193 stb r0, HSTATE_NAPPING(r13)
194 stb r0, HSTATE_HWTHREAD_REQ(r13)
196 /* see if any other thread is already exiting */
198 lwz r0, VCORE_ENTRY_EXIT(r5)
202 /* clear our bit in napping_threads */
203 lbz r7, HSTATE_PTID(r13)
206 addi r6, r5, VCORE_NAPPING_THREADS
212 /* Check the wake reason in SRR1 to see why we got here */
214 rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */
215 cmpwi r3, 4 /* was it an external interrupt? */
216 bne kvm_novcpu_exit /* if not, exit the guest */
218 /* extern interrupt - read and handle it */
219 li r12, BOOK3S_INTERRUPT_EXTERNAL
225 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
226 ld r4, HSTATE_KVM_VCPU(r13)
234 * We come in here when wakened from nap mode.
235 * Relocation is off and most register values are lost.
236 * r13 points to the PACA.
238 .globl kvm_start_guest
242 li r0,KVM_HWTHREAD_IN_KVM
243 stb r0,HSTATE_HWTHREAD_STATE(r13)
245 /* NV GPR values from power7_idle() will no longer be valid */
247 stb r0,PACA_NAPSTATELOST(r13)
249 /* were we napping due to cede? */
250 lbz r0,HSTATE_NAPPING(r13)
251 cmpwi r0,NAPPING_CEDE
253 cmpwi r0,NAPPING_NOVCPU
254 beq kvm_novcpu_wakeup
256 ld r1,PACAEMERGSP(r13)
257 subi r1,r1,STACK_FRAME_OVERHEAD
260 * We weren't napping due to cede, so this must be a secondary
261 * thread being woken up to run a guest, or being woken up due
262 * to a stray IPI. (Or due to some machine check or hypervisor
263 * maintenance interrupt while the core is in KVM.)
266 /* Check the wake reason in SRR1 to see why we got here */
268 rlwinm r3,r3,44-31,0x7 /* extract wake reason field */
269 cmpwi r3,4 /* was it an external interrupt? */
271 ld r5,HSTATE_XICS_PHYS(r13)
272 li r7,XICS_XIRR /* if it was an external interrupt, */
273 lwzcix r8,r5,r7 /* get and ack the interrupt */
275 clrldi. r9,r8,40 /* get interrupt source ID. */
276 beq 28f /* none there? */
277 cmpwi r9,XICS_IPI /* was it an IPI? */
281 stbcix r0,r5,r6 /* clear IPI */
282 stwcix r8,r5,r7 /* EOI the interrupt */
283 sync /* order loading of vcpu after that */
285 /* get vcpu pointer, NULL if we have no vcpu to run */
286 ld r4,HSTATE_KVM_VCPU(r13)
288 /* if we have no vcpu to run, go back to sleep */
292 27: /* XXX should handle hypervisor maintenance interrupts etc. here */
294 28: /* SRR1 said external but ICP said nope?? */
296 29: /* External non-IPI interrupt to offline secondary thread? help?? */
297 stw r8,HSTATE_SAVED_XIRR(r13)
301 /* Set HSTATE_DSCR(r13) to something sensible */
302 LOAD_REG_ADDR(r6, dscr_default)
304 std r6, HSTATE_DSCR(r13)
308 /* Back from the guest, go back to nap */
309 /* Clear our vcpu pointer so we don't come back in early */
311 std r0, HSTATE_KVM_VCPU(r13)
313 /* Clear any pending IPI - we're an offline thread */
314 ld r5, HSTATE_XICS_PHYS(r13)
316 lwzcix r3, r5, r7 /* ack any pending interrupt */
317 rlwinm. r0, r3, 0, 0xffffff /* any pending? */
322 stbcix r0, r5, r6 /* clear the IPI */
323 stwcix r3, r5, r7 /* EOI it */
326 /* increment the nap count and then go to nap mode */
327 ld r4, HSTATE_KVM_VCORE(r13)
328 addi r4, r4, VCORE_NAP_COUNT
329 lwsync /* make previous updates visible */
336 li r0, KVM_HWTHREAD_IN_NAP
337 stb r0, HSTATE_HWTHREAD_STATE(r13)
341 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
344 std r0, HSTATE_SCRATCH0(r13)
346 ld r0, HSTATE_SCRATCH0(r13)
352 /******************************************************************************
356 *****************************************************************************/
358 .global kvmppc_hv_entry
363 * R4 = vcpu pointer (or NULL)
367 * all other volatile GPRS = free
370 std r0, PPC_LR_STKOFF(r1)
373 /* Save R1 in the PACA */
374 std r1, HSTATE_HOST_R1(r13)
376 li r6, KVM_GUEST_MODE_HOST_HV
377 stb r6, HSTATE_IN_GUEST(r13)
387 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
389 * POWER7 host -> guest partition switch code.
390 * We don't have to lock against concurrent tlbies,
391 * but we do have to coordinate across hardware threads.
393 /* Increment entry count iff exit count is zero. */
394 ld r5,HSTATE_KVM_VCORE(r13)
395 addi r9,r5,VCORE_ENTRY_EXIT
397 cmpwi r3,0x100 /* any threads starting to exit? */
398 bge secondary_too_late /* if so we're too late to the party */
403 /* Primary thread switches to guest partition. */
404 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
405 lbz r6,HSTATE_PTID(r13)
410 li r0,LPID_RSVD /* switch to reserved LPID */
413 mtspr SPRN_SDR1,r6 /* switch to partition page table */
417 /* See if we need to flush the TLB */
418 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
419 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
420 srdi r6,r6,6 /* doubleword number */
421 sldi r6,r6,3 /* address offset */
423 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
429 23: ldarx r7,0,r6 /* if set, clear the bit */
433 /* Flush the TLB of any entries for this LPID */
434 /* use arch 2.07S as a proxy for POWER8 */
436 li r6,512 /* POWER8 has 512 sets */
438 li r6,128 /* POWER7 has 128 sets */
439 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
441 li r7,0x800 /* IS field = 0b10 */
448 /* Add timebase offset onto timebase */
449 22: ld r8,VCORE_TB_OFFSET(r5)
452 mftb r6 /* current host timebase */
454 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
455 mftb r7 /* check if lower 24 bits overflowed */
460 addis r8,r8,0x100 /* if so, increment upper 40 bits */
463 /* Load guest PCR value to select appropriate compat mode */
464 37: ld r7, VCORE_PCR(r5)
471 /* DPDES is shared between threads */
472 ld r8, VCORE_DPDES(r5)
474 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
477 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
480 /* Secondary threads wait for primary to have done partition switch */
481 20: lbz r0,VCORE_IN_GUEST(r5)
485 /* Set LPCR and RMOR. */
486 10: ld r8,VCORE_LPCR(r5)
492 /* Check if HDEC expires soon */
494 cmpwi r3,512 /* 1 microsecond */
495 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
500 * PPC970 host -> guest partition switch code.
501 * We have to lock against concurrent tlbies,
502 * using native_tlbie_lock to lock against host tlbies
503 * and kvm->arch.tlbie_lock to lock against guest tlbies.
504 * We also have to invalidate the TLB since its
505 * entries aren't tagged with the LPID.
507 30: ld r5,HSTATE_KVM_VCORE(r13)
508 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
510 /* first take native_tlbie_lock */
513 .tc native_tlbie_lock[TC],native_tlbie_lock
515 ld r3,toc_tlbie_lock@toc(2)
516 #ifdef __BIG_ENDIAN__
517 lwz r8,PACA_LOCK_TOKEN(r13)
519 lwz r8,PACAPACAINDEX(r13)
528 ld r5,HSTATE_KVM_VCORE(r13)
529 ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */
531 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
535 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
538 stw r0,0(r3) /* drop native_tlbie_lock */
540 /* invalidate the whole TLB */
549 /* Take the guest's tlbie_lock */
550 addi r3,r9,KVM_TLBIE_LOCK
558 mtspr SPRN_SDR1,r6 /* switch to partition page table */
560 /* Set up HID4 with the guest's LPID etc. */
565 /* drop the guest's tlbie_lock */
569 /* Check if HDEC expires soon */
572 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
575 /* Enable HDEC interrupts */
578 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
588 /* Do we have a guest vcpu to run? */
590 beq kvmppc_primary_no_guest
593 /* Load up guest SLB entries */
594 lwz r5,VCPU_SLB_MAX(r4)
599 1: ld r8,VCPU_SLB_E(r6)
602 addi r6,r6,VCPU_SLB_SIZE
605 /* Increment yield count if they have a VPA */
609 lwz r5, LPPACA_YIELDCOUNT(r3)
611 stw r5, LPPACA_YIELDCOUNT(r3)
613 stb r6, VCPU_VPA_DIRTY(r4)
617 /* Save purr/spurr */
620 std r5,HSTATE_PURR(r13)
621 std r6,HSTATE_SPURR(r13)
626 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
629 /* Set partition DABR */
630 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
635 BEGIN_FTR_SECTION_NESTED(89)
637 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89)
638 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
640 /* Load guest PMU registers */
641 /* R4 is live here (vcpu pointer) */
643 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
644 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
646 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
647 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
648 lwz r6, VCPU_PMC + 8(r4)
649 lwz r7, VCPU_PMC + 12(r4)
650 lwz r8, VCPU_PMC + 16(r4)
651 lwz r9, VCPU_PMC + 20(r4)
653 lwz r10, VCPU_PMC + 24(r4)
654 lwz r11, VCPU_PMC + 28(r4)
655 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
665 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
667 ld r5, VCPU_MMCR + 8(r4)
668 ld r6, VCPU_MMCR + 16(r4)
676 ld r5, VCPU_MMCR + 24(r4)
678 lwz r7, VCPU_PMC + 24(r4)
679 lwz r8, VCPU_PMC + 28(r4)
680 ld r9, VCPU_MMCR + 32(r4)
686 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
690 /* Load up FP, VMX and VSX registers */
693 ld r14, VCPU_GPR(R14)(r4)
694 ld r15, VCPU_GPR(R15)(r4)
695 ld r16, VCPU_GPR(R16)(r4)
696 ld r17, VCPU_GPR(R17)(r4)
697 ld r18, VCPU_GPR(R18)(r4)
698 ld r19, VCPU_GPR(R19)(r4)
699 ld r20, VCPU_GPR(R20)(r4)
700 ld r21, VCPU_GPR(R21)(r4)
701 ld r22, VCPU_GPR(R22)(r4)
702 ld r23, VCPU_GPR(R23)(r4)
703 ld r24, VCPU_GPR(R24)(r4)
704 ld r25, VCPU_GPR(R25)(r4)
705 ld r26, VCPU_GPR(R26)(r4)
706 ld r27, VCPU_GPR(R27)(r4)
707 ld r28, VCPU_GPR(R28)(r4)
708 ld r29, VCPU_GPR(R29)(r4)
709 ld r30, VCPU_GPR(R30)(r4)
710 ld r31, VCPU_GPR(R31)(r4)
713 /* Switch DSCR to guest value */
716 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
719 /* Skip next section on POWER7 or PPC970 */
721 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
722 /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
725 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
728 /* Load up POWER8-specific registers */
730 lwz r6, VCPU_PSPB(r4)
736 ld r6, VCPU_DAWRX(r4)
737 ld r7, VCPU_CIABR(r4)
747 ld r5, VCPU_TFHAR(r4)
748 ld r6, VCPU_TFIAR(r4)
749 ld r7, VCPU_TEXASR(r4)
750 ld r8, VCPU_EBBHR(r4)
753 mtspr SPRN_TEXASR, r7
755 ld r5, VCPU_EBBRR(r4)
756 ld r6, VCPU_BESCR(r4)
757 ld r7, VCPU_CSIGR(r4)
763 ld r5, VCPU_TCSCR(r4)
765 lwz r7, VCPU_GUEST_PID(r4)
774 * Set the decrementer to the guest decrementer.
776 ld r8,VCPU_DEC_EXPIRES(r4)
782 ld r5, VCPU_SPRG0(r4)
783 ld r6, VCPU_SPRG1(r4)
784 ld r7, VCPU_SPRG2(r4)
785 ld r8, VCPU_SPRG3(r4)
791 /* Load up DAR and DSISR */
793 lwz r6, VCPU_DSISR(r4)
798 /* Restore AMR and UAMOR, set AMOR to all 1s */
805 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
807 /* Restore state of CTRL run bit; assume 1 on entry */
823 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
827 /* r11 = vcpu->arch.msr & ~MSR_HV */
828 rldicl r11, r11, 63 - MSR_HV_LG, 1
829 rotldi r11, r11, 1 + MSR_HV_LG
832 /* Check if we can deliver an external or decrementer interrupt now */
833 ld r0,VCPU_PENDING_EXC(r4)
834 lis r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
844 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
846 li r0,BOOK3S_INTERRUPT_EXTERNAL
850 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
856 li r0,BOOK3S_INTERRUPT_DECREMENTER
859 /* Move SRR0 and SRR1 into the respective regs */
860 5: mtspr SPRN_SRR0, r6
866 * R10: value for HSRR0
867 * R11: value for HSRR1
872 stb r0,VCPU_CEDED(r4) /* cancel cede */
876 /* Activate guest mode, so faults get handled by KVM */
877 li r9, KVM_GUEST_MODE_GUEST_HV
878 stb r9, HSTATE_IN_GUEST(r13)
885 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
888 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
895 ld r1, VCPU_GPR(R1)(r4)
896 ld r2, VCPU_GPR(R2)(r4)
897 ld r3, VCPU_GPR(R3)(r4)
898 ld r5, VCPU_GPR(R5)(r4)
899 ld r6, VCPU_GPR(R6)(r4)
900 ld r7, VCPU_GPR(R7)(r4)
901 ld r8, VCPU_GPR(R8)(r4)
902 ld r9, VCPU_GPR(R9)(r4)
903 ld r10, VCPU_GPR(R10)(r4)
904 ld r11, VCPU_GPR(R11)(r4)
905 ld r12, VCPU_GPR(R12)(r4)
906 ld r13, VCPU_GPR(R13)(r4)
910 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
911 ld r0, VCPU_GPR(R0)(r4)
912 ld r4, VCPU_GPR(R4)(r4)
917 /******************************************************************************
921 *****************************************************************************/
924 * We come here from the first-level interrupt handlers.
926 .globl kvmppc_interrupt_hv
930 * R12 = interrupt vector
932 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
933 * guest R13 saved in SPRN_SCRATCH0
935 /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
936 std r9, HSTATE_HOST_R2(r13)
938 lbz r9, HSTATE_IN_GUEST(r13)
939 cmpwi r9, KVM_GUEST_MODE_HOST_HV
940 beq kvmppc_bad_host_intr
941 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
942 cmpwi r9, KVM_GUEST_MODE_GUEST
943 ld r9, HSTATE_HOST_R2(r13)
944 beq kvmppc_interrupt_pr
946 /* We're now back in the host but in guest MMU context */
947 li r9, KVM_GUEST_MODE_HOST_HV
948 stb r9, HSTATE_IN_GUEST(r13)
950 ld r9, HSTATE_KVM_VCPU(r13)
954 std r0, VCPU_GPR(R0)(r9)
955 std r1, VCPU_GPR(R1)(r9)
956 std r2, VCPU_GPR(R2)(r9)
957 std r3, VCPU_GPR(R3)(r9)
958 std r4, VCPU_GPR(R4)(r9)
959 std r5, VCPU_GPR(R5)(r9)
960 std r6, VCPU_GPR(R6)(r9)
961 std r7, VCPU_GPR(R7)(r9)
962 std r8, VCPU_GPR(R8)(r9)
963 ld r0, HSTATE_HOST_R2(r13)
964 std r0, VCPU_GPR(R9)(r9)
965 std r10, VCPU_GPR(R10)(r9)
966 std r11, VCPU_GPR(R11)(r9)
967 ld r3, HSTATE_SCRATCH0(r13)
968 lwz r4, HSTATE_SCRATCH1(r13)
969 std r3, VCPU_GPR(R12)(r9)
972 ld r3, HSTATE_CFAR(r13)
973 std r3, VCPU_CFAR(r9)
974 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
976 ld r4, HSTATE_PPR(r13)
978 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
980 /* Restore R1/R2 so we can handle faults */
981 ld r1, HSTATE_HOST_R1(r13)
986 std r10, VCPU_SRR0(r9)
987 std r11, VCPU_SRR1(r9)
988 andi. r0, r12, 2 /* need to read HSRR0/1? */
990 mfspr r10, SPRN_HSRR0
991 mfspr r11, SPRN_HSRR1
993 1: std r10, VCPU_PC(r9)
994 std r11, VCPU_MSR(r9)
998 std r3, VCPU_GPR(R13)(r9)
1001 stw r12,VCPU_TRAP(r9)
1003 /* Save HEIR (HV emulation assist reg) in last_inst
1004 if this is an HEI (HV emulation interrupt, e40) */
1005 li r3,KVM_INST_FETCH_FAILED
1007 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1010 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1011 11: stw r3,VCPU_LAST_INST(r9)
1013 /* these are volatile across C function calls */
1016 std r3, VCPU_CTR(r9)
1017 stw r4, VCPU_XER(r9)
1020 /* If this is a page table miss then see if it's theirs or ours */
1021 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1023 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1025 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1027 /* See if this is a leftover HDEC interrupt */
1028 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1034 /* See if this is an hcall we can handle in real mode */
1035 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1036 beq hcall_try_real_mode
1038 /* Only handle external interrupts here on arch 206 and later */
1040 b ext_interrupt_to_host
1041 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1043 /* External interrupt ? */
1044 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1045 bne+ ext_interrupt_to_host
1047 /* External interrupt, first check for host_ipi. If this is
1048 * set, we know the host wants us out so let's do it now
1053 bgt ext_interrupt_to_host
1055 /* Allright, looks like an IPI for the guest, we need to set MER */
1056 /* Check if any CPU is heading out to the host, if so head out too */
1057 ld r5, HSTATE_KVM_VCORE(r13)
1058 lwz r0, VCORE_ENTRY_EXIT(r5)
1060 bge ext_interrupt_to_host
1062 /* See if there is a pending interrupt for the guest */
1064 ld r0, VCPU_PENDING_EXC(r9)
1065 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
1066 rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
1067 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
1070 /* And if the guest EE is set, we can deliver immediately, else
1071 * we return to the guest with MER set
1073 andi. r0, r11, MSR_EE
1075 mtspr SPRN_SRR0, r10
1076 mtspr SPRN_SRR1, r11
1077 li r10, BOOK3S_INTERRUPT_EXTERNAL
1078 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1084 ext_interrupt_to_host:
1086 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1087 /* Save more register state */
1090 std r6, VCPU_DAR(r9)
1091 stw r7, VCPU_DSISR(r9)
1093 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1094 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1096 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1097 std r6, VCPU_FAULT_DAR(r9)
1098 stw r7, VCPU_FAULT_DSISR(r9)
1100 /* See if it is a machine check */
1101 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1102 beq machine_check_realmode
1105 /* Save guest CTRL register, set runlatch to 1 */
1106 6: mfspr r6,SPRN_CTRLF
1107 stw r6,VCPU_CTRL(r9)
1113 /* Read the guest SLB and save it away */
1114 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1120 andis. r0,r8,SLB_ESID_V@h
1122 add r8,r8,r6 /* put index in */
1124 std r8,VCPU_SLB_E(r7)
1125 std r3,VCPU_SLB_V(r7)
1126 addi r7,r7,VCPU_SLB_SIZE
1130 stw r5,VCPU_SLB_MAX(r9)
1133 * Save the guest PURR/SPURR
1139 ld r8,VCPU_SPURR(r9)
1140 std r5,VCPU_PURR(r9)
1141 std r6,VCPU_SPURR(r9)
1146 * Restore host PURR/SPURR and add guest times
1147 * so that the time in the guest gets accounted.
1149 ld r3,HSTATE_PURR(r13)
1150 ld r4,HSTATE_SPURR(r13)
1155 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
1162 std r5,VCPU_DEC_EXPIRES(r9)
1166 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1167 /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
1170 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
1173 /* Save POWER8-specific registers */
1177 std r5, VCPU_IAMR(r9)
1178 stw r6, VCPU_PSPB(r9)
1179 std r7, VCPU_FSCR(r9)
1184 std r6, VCPU_VTB(r9)
1185 std r7, VCPU_TAR(r9)
1186 mfspr r5, SPRN_TFHAR
1187 mfspr r6, SPRN_TFIAR
1188 mfspr r7, SPRN_TEXASR
1189 mfspr r8, SPRN_EBBHR
1190 std r5, VCPU_TFHAR(r9)
1191 std r6, VCPU_TFIAR(r9)
1192 std r7, VCPU_TEXASR(r9)
1193 std r8, VCPU_EBBHR(r9)
1194 mfspr r5, SPRN_EBBRR
1195 mfspr r6, SPRN_BESCR
1196 mfspr r7, SPRN_CSIGR
1198 std r5, VCPU_EBBRR(r9)
1199 std r6, VCPU_BESCR(r9)
1200 std r7, VCPU_CSIGR(r9)
1201 std r8, VCPU_TACR(r9)
1202 mfspr r5, SPRN_TCSCR
1206 std r5, VCPU_TCSCR(r9)
1207 std r6, VCPU_ACOP(r9)
1208 stw r7, VCPU_GUEST_PID(r9)
1209 std r8, VCPU_WORT(r9)
1212 /* Save and reset AMR and UAMOR before turning on the MMU */
1217 std r6,VCPU_UAMOR(r9)
1220 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1222 /* Switch DSCR back to host value */
1225 ld r7, HSTATE_DSCR(r13)
1226 std r8, VCPU_DSCR(r9)
1228 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1230 /* Save non-volatile GPRs */
1231 std r14, VCPU_GPR(R14)(r9)
1232 std r15, VCPU_GPR(R15)(r9)
1233 std r16, VCPU_GPR(R16)(r9)
1234 std r17, VCPU_GPR(R17)(r9)
1235 std r18, VCPU_GPR(R18)(r9)
1236 std r19, VCPU_GPR(R19)(r9)
1237 std r20, VCPU_GPR(R20)(r9)
1238 std r21, VCPU_GPR(R21)(r9)
1239 std r22, VCPU_GPR(R22)(r9)
1240 std r23, VCPU_GPR(R23)(r9)
1241 std r24, VCPU_GPR(R24)(r9)
1242 std r25, VCPU_GPR(R25)(r9)
1243 std r26, VCPU_GPR(R26)(r9)
1244 std r27, VCPU_GPR(R27)(r9)
1245 std r28, VCPU_GPR(R28)(r9)
1246 std r29, VCPU_GPR(R29)(r9)
1247 std r30, VCPU_GPR(R30)(r9)
1248 std r31, VCPU_GPR(R31)(r9)
1251 mfspr r3, SPRN_SPRG0
1252 mfspr r4, SPRN_SPRG1
1253 mfspr r5, SPRN_SPRG2
1254 mfspr r6, SPRN_SPRG3
1255 std r3, VCPU_SPRG0(r9)
1256 std r4, VCPU_SPRG1(r9)
1257 std r5, VCPU_SPRG2(r9)
1258 std r6, VCPU_SPRG3(r9)
1264 /* Increment yield count if they have a VPA */
1265 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1268 lwz r3, LPPACA_YIELDCOUNT(r8)
1270 stw r3, LPPACA_YIELDCOUNT(r8)
1272 stb r3, VCPU_VPA_DIRTY(r9)
1274 /* Save PMU registers if requested */
1275 /* r8 and cr0.eq are live here */
1277 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1278 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1279 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1280 mfspr r6, SPRN_MMCRA
1282 /* On P7, clear MMCRA in order to disable SDAR updates */
1284 mtspr SPRN_MMCRA, r7
1285 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1287 beq 21f /* if no VPA, save PMU stuff anyway */
1288 lbz r7, LPPACA_PMCINUSE(r8)
1289 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1291 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1293 21: mfspr r5, SPRN_MMCR1
1296 std r4, VCPU_MMCR(r9)
1297 std r5, VCPU_MMCR + 8(r9)
1298 std r6, VCPU_MMCR + 16(r9)
1299 std r7, VCPU_SIAR(r9)
1300 std r8, VCPU_SDAR(r9)
1308 mfspr r10, SPRN_PMC7
1309 mfspr r11, SPRN_PMC8
1310 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1311 stw r3, VCPU_PMC(r9)
1312 stw r4, VCPU_PMC + 4(r9)
1313 stw r5, VCPU_PMC + 8(r9)
1314 stw r6, VCPU_PMC + 12(r9)
1315 stw r7, VCPU_PMC + 16(r9)
1316 stw r8, VCPU_PMC + 20(r9)
1318 stw r10, VCPU_PMC + 24(r9)
1319 stw r11, VCPU_PMC + 28(r9)
1320 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1322 mfspr r4, SPRN_MMCR2
1324 mfspr r6, SPRN_SPMC1
1325 mfspr r7, SPRN_SPMC2
1326 mfspr r8, SPRN_MMCRS
1327 std r4, VCPU_MMCR + 24(r9)
1328 std r5, VCPU_SIER(r9)
1329 stw r6, VCPU_PMC + 24(r9)
1330 stw r7, VCPU_PMC + 28(r9)
1331 std r8, VCPU_MMCR + 32(r9)
1333 mtspr SPRN_MMCRS, r4
1334 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1342 hdec_soon: /* r12 = trap, r13 = paca */
1345 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1347 * POWER7 guest -> host partition switch code.
1348 * We don't have to lock against tlbies but we do
1349 * have to coordinate the hardware threads.
1351 /* Increment the threads-exiting-guest count in the 0xff00
1352 bits of vcore->entry_exit_count */
1354 ld r5,HSTATE_KVM_VCORE(r13)
1355 addi r6,r5,VCORE_ENTRY_EXIT
1363 * At this point we have an interrupt that we have to pass
1364 * up to the kernel or qemu; we can't handle it in real mode.
1365 * Thus we have to do a partition switch, so we have to
1366 * collect the other threads, if we are the first thread
1367 * to take an interrupt. To do this, we set the HDEC to 0,
1368 * which causes an HDEC interrupt in all threads within 2ns
1369 * because the HDEC register is shared between all 4 threads.
1370 * However, we don't need to bother if this is an HDEC
1371 * interrupt, since the other threads will already be on their
1372 * way here in that case.
1374 cmpwi r3,0x100 /* Are we the first here? */
1376 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1382 * Send an IPI to any napping threads, since an HDEC interrupt
1383 * doesn't wake CPUs up from nap.
1385 lwz r3,VCORE_NAPPING_THREADS(r5)
1386 lbz r4,HSTATE_PTID(r13)
1389 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
1391 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
1395 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1398 stbcix r0,r7,r8 /* trigger the IPI */
1400 addi r6,r6,PACA_SIZE
1404 /* Secondary threads wait for primary to do partition switch */
1405 43: ld r5,HSTATE_KVM_VCORE(r13)
1406 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1407 lbz r3,HSTATE_PTID(r13)
1411 13: lbz r3,VCORE_IN_GUEST(r5)
1417 /* Primary thread waits for all the secondaries to exit guest */
1418 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1425 /* Primary thread switches back to host partition */
1426 ld r6,KVM_HOST_SDR1(r4)
1427 lwz r7,KVM_HOST_LPID(r4)
1428 li r8,LPID_RSVD /* switch to reserved LPID */
1431 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1436 /* DPDES is shared between threads */
1437 mfspr r7, SPRN_DPDES
1438 std r7, VCORE_DPDES(r5)
1439 /* clear DPDES so we don't get guest doorbells in the host */
1441 mtspr SPRN_DPDES, r8
1442 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1444 /* Subtract timebase offset from timebase */
1445 ld r8,VCORE_TB_OFFSET(r5)
1448 mftb r6 /* current host timebase */
1450 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1451 mftb r7 /* check if lower 24 bits overflowed */
1456 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1460 17: ld r0, VCORE_PCR(r5)
1466 /* Signal secondary CPUs to continue */
1467 stb r0,VCORE_IN_GUEST(r5)
1468 lis r8,0x7fff /* MAX_INT@h */
1471 16: ld r8,KVM_HOST_LPCR(r4)
1477 * PPC970 guest -> host partition switch code.
1478 * We have to lock against concurrent tlbies, and
1479 * we have to flush the whole TLB.
1481 32: ld r5,HSTATE_KVM_VCORE(r13)
1482 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1484 /* Take the guest's tlbie_lock */
1485 #ifdef __BIG_ENDIAN__
1486 lwz r8,PACA_LOCK_TOKEN(r13)
1488 lwz r8,PACAPACAINDEX(r13)
1490 addi r3,r4,KVM_TLBIE_LOCK
1498 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1500 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1504 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1507 stw r0,0(r3) /* drop guest tlbie_lock */
1509 /* invalidate the whole TLB */
1518 /* take native_tlbie_lock */
1519 ld r3,toc_tlbie_lock@toc(2)
1527 ld r6,KVM_HOST_SDR1(r4)
1528 mtspr SPRN_SDR1,r6 /* switch to host page table */
1530 /* Set up host HID4 value */
1535 stw r0,0(r3) /* drop native_tlbie_lock */
1537 lis r8,0x7fff /* MAX_INT@h */
1540 /* Disable HDEC interrupts */
1543 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1553 /* load host SLB entries */
1554 33: ld r8,PACA_SLBSHADOWPTR(r13)
1556 .rept SLB_NUM_BOLTED
1557 ld r5,SLBSHADOW_SAVEAREA(r8)
1558 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1559 andis. r7,r5,SLB_ESID_V@h
1565 /* Unset guest mode */
1566 li r0, KVM_GUEST_MODE_NONE
1567 stb r0, HSTATE_IN_GUEST(r13)
1569 ld r0, 112+PPC_LR_STKOFF(r1)
1575 * Check whether an HDSI is an HPTE not found fault or something else.
1576 * If it is an HPTE not found fault that is due to the guest accessing
1577 * a page that they have mapped but which we have paged out, then
1578 * we continue on with the guest exit path. In all other cases,
1579 * reflect the HDSI to the guest as a DSI.
1583 mfspr r6, SPRN_HDSISR
1584 /* HPTE not found fault or protection fault? */
1585 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1586 beq 1f /* if not, send it to the guest */
1587 andi. r0, r11, MSR_DR /* data relocation enabled? */
1590 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1591 bne 1f /* if no SLB entry found */
1592 4: std r4, VCPU_FAULT_DAR(r9)
1593 stw r6, VCPU_FAULT_DSISR(r9)
1595 /* Search the hash table. */
1596 mr r3, r9 /* vcpu pointer */
1597 li r7, 1 /* data fault */
1598 bl .kvmppc_hpte_hv_fault
1599 ld r9, HSTATE_KVM_VCPU(r13)
1601 ld r11, VCPU_MSR(r9)
1602 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1603 cmpdi r3, 0 /* retry the instruction */
1605 cmpdi r3, -1 /* handle in kernel mode */
1607 cmpdi r3, -2 /* MMIO emulation; need instr word */
1610 /* Synthesize a DSI for the guest */
1611 ld r4, VCPU_FAULT_DAR(r9)
1613 1: mtspr SPRN_DAR, r4
1614 mtspr SPRN_DSISR, r6
1615 mtspr SPRN_SRR0, r10
1616 mtspr SPRN_SRR1, r11
1617 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1618 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1620 fast_interrupt_c_return:
1621 6: ld r7, VCPU_CTR(r9)
1622 lwz r8, VCPU_XER(r9)
1628 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1629 ld r5, KVM_VRMA_SLB_V(r5)
1632 /* If this is for emulated MMIO, load the instruction word */
1633 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1635 /* Set guest mode to 'jump over instruction' so if lwz faults
1636 * we'll just continue at the next IP. */
1637 li r0, KVM_GUEST_MODE_SKIP
1638 stb r0, HSTATE_IN_GUEST(r13)
1640 /* Do the access with MSR:DR enabled */
1642 ori r4, r3, MSR_DR /* Enable paging for data */
1647 /* Store the result */
1648 stw r8, VCPU_LAST_INST(r9)
1650 /* Unset guest mode. */
1651 li r0, KVM_GUEST_MODE_HOST_HV
1652 stb r0, HSTATE_IN_GUEST(r13)
1656 * Similarly for an HISI, reflect it to the guest as an ISI unless
1657 * it is an HPTE not found fault for a page that we have paged out.
1660 andis. r0, r11, SRR1_ISI_NOPT@h
1662 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1665 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1666 bne 1f /* if no SLB entry found */
1668 /* Search the hash table. */
1669 mr r3, r9 /* vcpu pointer */
1672 li r7, 0 /* instruction fault */
1673 bl .kvmppc_hpte_hv_fault
1674 ld r9, HSTATE_KVM_VCPU(r13)
1676 ld r11, VCPU_MSR(r9)
1677 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1678 cmpdi r3, 0 /* retry the instruction */
1679 beq fast_interrupt_c_return
1680 cmpdi r3, -1 /* handle in kernel mode */
1683 /* Synthesize an ISI for the guest */
1685 1: mtspr SPRN_SRR0, r10
1686 mtspr SPRN_SRR1, r11
1687 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1688 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1690 b fast_interrupt_c_return
1692 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1693 ld r5, KVM_VRMA_SLB_V(r6)
1697 * Try to handle an hcall in real mode.
1698 * Returns to the guest if we handle it, or continues on up to
1699 * the kernel if we can't (i.e. if we don't have a handler for
1700 * it, or if the handler returns H_TOO_HARD).
1702 .globl hcall_try_real_mode
1703 hcall_try_real_mode:
1704 ld r3,VCPU_GPR(R3)(r9)
1706 /* sc 1 from userspace - reflect to guest syscall */
1707 bne sc_1_fast_return
1709 cmpldi r3,hcall_real_table_end - hcall_real_table
1711 LOAD_REG_ADDR(r4, hcall_real_table)
1717 mr r3,r9 /* get vcpu pointer */
1718 ld r4,VCPU_GPR(R4)(r9)
1721 beq hcall_real_fallback
1722 ld r4,HSTATE_KVM_VCPU(r13)
1723 std r3,VCPU_GPR(R3)(r4)
1731 li r10, BOOK3S_INTERRUPT_SYSCALL
1732 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1737 /* We've attempted a real mode hcall, but it's punted it back
1738 * to userspace. We need to restore some clobbered volatiles
1739 * before resuming the pass-it-to-qemu path */
1740 hcall_real_fallback:
1741 li r12,BOOK3S_INTERRUPT_SYSCALL
1742 ld r9, HSTATE_KVM_VCPU(r13)
1746 .globl hcall_real_table
1748 .long 0 /* 0 - unused */
1749 .long .kvmppc_h_remove - hcall_real_table
1750 .long .kvmppc_h_enter - hcall_real_table
1751 .long .kvmppc_h_read - hcall_real_table
1752 .long 0 /* 0x10 - H_CLEAR_MOD */
1753 .long 0 /* 0x14 - H_CLEAR_REF */
1754 .long .kvmppc_h_protect - hcall_real_table
1755 .long 0 /* 0x1c - H_GET_TCE */
1756 .long .kvmppc_h_put_tce - hcall_real_table
1757 .long 0 /* 0x24 - H_SET_SPRG0 */
1758 .long .kvmppc_h_set_dabr - hcall_real_table
1773 #ifdef CONFIG_KVM_XICS
1774 .long .kvmppc_rm_h_eoi - hcall_real_table
1775 .long .kvmppc_rm_h_cppr - hcall_real_table
1776 .long .kvmppc_rm_h_ipi - hcall_real_table
1777 .long 0 /* 0x70 - H_IPOLL */
1778 .long .kvmppc_rm_h_xirr - hcall_real_table
1780 .long 0 /* 0x64 - H_EOI */
1781 .long 0 /* 0x68 - H_CPPR */
1782 .long 0 /* 0x6c - H_IPI */
1783 .long 0 /* 0x70 - H_IPOLL */
1784 .long 0 /* 0x74 - H_XIRR */
1812 .long .kvmppc_h_cede - hcall_real_table
1829 .long .kvmppc_h_bulk_remove - hcall_real_table
1830 hcall_real_table_end:
1836 _GLOBAL(kvmppc_h_set_dabr)
1839 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1840 std r4,VCPU_DABR(r3)
1841 /* Work around P7 bug where DABR can get corrupted on mtspr */
1842 1: mtspr SPRN_DABR,r4
1850 _GLOBAL(kvmppc_h_cede)
1852 std r11,VCPU_MSR(r3)
1854 stb r0,VCPU_CEDED(r3)
1855 sync /* order setting ceded vs. testing prodded */
1856 lbz r5,VCPU_PRODDED(r3)
1858 bne kvm_cede_prodded
1859 li r0,0 /* set trap to 0 to say hcall is handled */
1860 stw r0,VCPU_TRAP(r3)
1862 std r0,VCPU_GPR(R3)(r3)
1864 b kvm_cede_exit /* just send it up to host on 970 */
1865 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1868 * Set our bit in the bitmask of napping threads unless all the
1869 * other threads are already napping, in which case we send this
1872 ld r5,HSTATE_KVM_VCORE(r13)
1873 lbz r6,HSTATE_PTID(r13)
1874 lwz r8,VCORE_ENTRY_EXIT(r5)
1878 addi r6,r5,VCORE_NAPPING_THREADS
1887 stb r0,HSTATE_NAPPING(r13)
1888 /* order napping_threads update vs testing entry_exit_count */
1891 lwz r7,VCORE_ENTRY_EXIT(r5)
1893 bge 33f /* another thread already exiting */
1896 * Although not specifically required by the architecture, POWER7
1897 * preserves the following registers in nap mode, even if an SMT mode
1898 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1899 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1901 /* Save non-volatile GPRs */
1902 std r14, VCPU_GPR(R14)(r3)
1903 std r15, VCPU_GPR(R15)(r3)
1904 std r16, VCPU_GPR(R16)(r3)
1905 std r17, VCPU_GPR(R17)(r3)
1906 std r18, VCPU_GPR(R18)(r3)
1907 std r19, VCPU_GPR(R19)(r3)
1908 std r20, VCPU_GPR(R20)(r3)
1909 std r21, VCPU_GPR(R21)(r3)
1910 std r22, VCPU_GPR(R22)(r3)
1911 std r23, VCPU_GPR(R23)(r3)
1912 std r24, VCPU_GPR(R24)(r3)
1913 std r25, VCPU_GPR(R25)(r3)
1914 std r26, VCPU_GPR(R26)(r3)
1915 std r27, VCPU_GPR(R27)(r3)
1916 std r28, VCPU_GPR(R28)(r3)
1917 std r29, VCPU_GPR(R29)(r3)
1918 std r30, VCPU_GPR(R30)(r3)
1919 std r31, VCPU_GPR(R31)(r3)
1925 * Take a nap until a decrementer or external interrupt occurs,
1926 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1929 stb r0,HSTATE_HWTHREAD_REQ(r13)
1931 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
1935 std r0, HSTATE_SCRATCH0(r13)
1937 ld r0, HSTATE_SCRATCH0(r13)
1944 /* get vcpu pointer */
1945 ld r4, HSTATE_KVM_VCPU(r13)
1947 /* Woken by external or decrementer interrupt */
1948 ld r1, HSTATE_HOST_R1(r13)
1950 /* load up FP state */
1954 ld r14, VCPU_GPR(R14)(r4)
1955 ld r15, VCPU_GPR(R15)(r4)
1956 ld r16, VCPU_GPR(R16)(r4)
1957 ld r17, VCPU_GPR(R17)(r4)
1958 ld r18, VCPU_GPR(R18)(r4)
1959 ld r19, VCPU_GPR(R19)(r4)
1960 ld r20, VCPU_GPR(R20)(r4)
1961 ld r21, VCPU_GPR(R21)(r4)
1962 ld r22, VCPU_GPR(R22)(r4)
1963 ld r23, VCPU_GPR(R23)(r4)
1964 ld r24, VCPU_GPR(R24)(r4)
1965 ld r25, VCPU_GPR(R25)(r4)
1966 ld r26, VCPU_GPR(R26)(r4)
1967 ld r27, VCPU_GPR(R27)(r4)
1968 ld r28, VCPU_GPR(R28)(r4)
1969 ld r29, VCPU_GPR(R29)(r4)
1970 ld r30, VCPU_GPR(R30)(r4)
1971 ld r31, VCPU_GPR(R31)(r4)
1973 /* clear our bit in vcore->napping_threads */
1974 33: ld r5,HSTATE_KVM_VCORE(r13)
1975 lbz r3,HSTATE_PTID(r13)
1978 addi r6,r5,VCORE_NAPPING_THREADS
1984 stb r0,HSTATE_NAPPING(r13)
1986 /* Check the wake reason in SRR1 to see why we got here */
1988 rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */
1989 cmpwi r3, 4 /* was it an external interrupt? */
1990 li r12, BOOK3S_INTERRUPT_EXTERNAL
1993 ld r11, VCPU_MSR(r9)
1994 beq do_ext_interrupt /* if so */
1996 /* see if any other thread is already exiting */
1997 lwz r0,VCORE_ENTRY_EXIT(r5)
1999 blt kvmppc_cede_reentry /* if not go back to guest */
2001 /* some threads are exiting, so go to the guest exit path */
2002 b hcall_real_fallback
2004 /* cede when already previously prodded case */
2007 stb r0,VCPU_PRODDED(r3)
2008 sync /* order testing prodded vs. clearing ceded */
2009 stb r0,VCPU_CEDED(r3)
2013 /* we've ceded but we want to give control to the host */
2015 b hcall_real_fallback
2017 /* Try to handle a machine check in real mode */
2018 machine_check_realmode:
2019 mr r3, r9 /* get vcpu pointer */
2020 bl .kvmppc_realmode_machine_check
2022 cmpdi r3, 0 /* continue exiting from guest? */
2023 ld r9, HSTATE_KVM_VCPU(r13)
2024 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2026 /* If not, deliver a machine check. SRR0/1 are already set */
2027 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2028 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
2030 b fast_interrupt_c_return
2033 * Determine what sort of external interrupt is pending (if any).
2035 * 0 if no interrupt is pending
2036 * 1 if an interrupt is pending that needs to be handled by the host
2037 * -1 if there was a guest wakeup IPI (which has now been cleared)
2040 /* see if a host IPI is pending */
2042 lbz r0, HSTATE_HOST_IPI(r13)
2046 /* Now read the interrupt from the ICP */
2047 ld r6, HSTATE_XICS_PHYS(r13)
2052 rlwinm. r3, r0, 0, 0xffffff
2054 beq 1f /* if nothing pending in the ICP */
2056 /* We found something in the ICP...
2058 * If it's not an IPI, stash it in the PACA and return to
2059 * the host, we don't (yet) handle directing real external
2060 * interrupts directly to the guest
2062 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
2066 /* It's an IPI, clear the MFRR and EOI it */
2069 stbcix r3, r6, r8 /* clear the IPI */
2070 stwcix r0, r6, r7 /* EOI it */
2073 /* We need to re-check host IPI now in case it got set in the
2074 * meantime. If it's clear, we bounce the interrupt to the
2077 lbz r0, HSTATE_HOST_IPI(r13)
2081 /* OK, it's an IPI for us */
2085 42: /* It's not an IPI and it's for the host, stash it in the PACA
2086 * before exit, it will be picked up by the host ICP driver
2088 stw r0, HSTATE_SAVED_XIRR(r13)
2091 43: /* We raced with the host, we need to resend that IPI, bummer */
2093 stbcix r0, r6, r8 /* set the IPI */
2098 * Save away FP, VMX and VSX registers.
2100 * N.B. r30 and r31 are volatile across this function,
2101 * thus it is not callable from C.
2108 #ifdef CONFIG_ALTIVEC
2110 oris r8,r8,MSR_VEC@h
2111 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2115 oris r8,r8,MSR_VSX@h
2116 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2120 addi r3,r3,VCPU_FPRS
2122 #ifdef CONFIG_ALTIVEC
2124 addi r3,r31,VCPU_VRS
2126 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2128 mfspr r6,SPRN_VRSAVE
2129 stw r6,VCPU_VRSAVE(r3)
2136 * Load up FP, VMX and VSX registers
2138 * N.B. r30 and r31 are volatile across this function,
2139 * thus it is not callable from C.
2146 #ifdef CONFIG_ALTIVEC
2148 oris r8,r8,MSR_VEC@h
2149 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2153 oris r8,r8,MSR_VSX@h
2154 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2158 addi r3,r4,VCPU_FPRS
2160 #ifdef CONFIG_ALTIVEC
2162 addi r3,r31,VCPU_VRS
2164 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2166 lwz r7,VCPU_VRSAVE(r4)
2167 mtspr SPRN_VRSAVE,r7
2173 * We come here if we get any exception or interrupt while we are
2174 * executing host real mode code while in guest MMU context.
2175 * For now just spin, but we should do something better.
2177 kvmppc_bad_host_intr: