2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
32 #ifdef __LITTLE_ENDIAN__
33 #error Need to fix lppaca and SLB shadow accesses in little endian mode
37 * Call kvmppc_hv_entry in real mode.
38 * Must be called with interrupts hard-disabled.
42 * LR = return address to continue at after eventually re-enabling MMU
44 _GLOBAL(kvmppc_hv_entry_trampoline)
46 std r0, PPC_LR_STKOFF(r1)
49 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
54 mtmsrd r0,1 /* clear RI in MSR */
62 /* Back from guest - restore host state and return to caller */
64 /* Restore host DABR and DABRX */
65 ld r5,HSTATE_DABR(r13)
75 * Reload DEC. HDEC interrupts were disabled when
76 * we reloaded the host's LPCR value.
78 ld r3, HSTATE_DECEXP(r13)
83 /* Reload the host's PMU registers */
84 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
85 lbz r4, LPPACA_PMCINUSE(r3)
87 beq 23f /* skip if not */
88 lwz r3, HSTATE_PMC(r13)
89 lwz r4, HSTATE_PMC + 4(r13)
90 lwz r5, HSTATE_PMC + 8(r13)
91 lwz r6, HSTATE_PMC + 12(r13)
92 lwz r8, HSTATE_PMC + 16(r13)
93 lwz r9, HSTATE_PMC + 20(r13)
95 lwz r10, HSTATE_PMC + 24(r13)
96 lwz r11, HSTATE_PMC + 28(r13)
97 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
107 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
108 ld r3, HSTATE_MMCR(r13)
109 ld r4, HSTATE_MMCR + 8(r13)
110 ld r5, HSTATE_MMCR + 16(r13)
118 * For external and machine check interrupts, we need
119 * to call the Linux handler to process the interrupt.
120 * We do that by jumping to absolute address 0x500 for
121 * external interrupts, or the machine_check_fwnmi label
122 * for machine checks (since firmware might have patched
123 * the vector area at 0x200). The [h]rfid at the end of the
124 * handler will return to the book3s_hv_interrupts.S code.
125 * For other interrupts we do the rfid to get back
126 * to the book3s_hv_interrupts.S code here.
128 ld r8, 112+PPC_LR_STKOFF(r1)
130 ld r7, HSTATE_HOST_MSR(r13)
132 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
133 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
136 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
138 /* RFI into the highmem handler, or branch to interrupt handler */
142 mtmsrd r6, 1 /* Clear RI in MSR */
145 beqa 0x500 /* external interrupt (PPC970) */
146 beq cr1, 13f /* machine check */
149 /* On POWER7, we have external interrupts set to use HSRR0/1 */
150 11: mtspr SPRN_HSRR0, r8
154 13: b machine_check_fwnmi
158 * We come in here when wakened from nap mode on a secondary hw thread.
159 * Relocation is off and most register values are lost.
160 * r13 points to the PACA.
162 .globl kvm_start_guest
164 ld r1,PACAEMERGSP(r13)
165 subi r1,r1,STACK_FRAME_OVERHEAD
168 li r0,KVM_HWTHREAD_IN_KVM
169 stb r0,HSTATE_HWTHREAD_STATE(r13)
171 /* NV GPR values from power7_idle() will no longer be valid */
173 stb r0,PACA_NAPSTATELOST(r13)
175 /* were we napping due to cede? */
176 lbz r0,HSTATE_NAPPING(r13)
181 * We weren't napping due to cede, so this must be a secondary
182 * thread being woken up to run a guest, or being woken up due
183 * to a stray IPI. (Or due to some machine check or hypervisor
184 * maintenance interrupt while the core is in KVM.)
187 /* Check the wake reason in SRR1 to see why we got here */
189 rlwinm r3,r3,44-31,0x7 /* extract wake reason field */
190 cmpwi r3,4 /* was it an external interrupt? */
192 ld r5,HSTATE_XICS_PHYS(r13)
193 li r7,XICS_XIRR /* if it was an external interrupt, */
194 lwzcix r8,r5,r7 /* get and ack the interrupt */
196 clrldi. r9,r8,40 /* get interrupt source ID. */
197 beq 28f /* none there? */
198 cmpwi r9,XICS_IPI /* was it an IPI? */
202 stbcix r0,r5,r6 /* clear IPI */
203 stwcix r8,r5,r7 /* EOI the interrupt */
204 sync /* order loading of vcpu after that */
206 /* get vcpu pointer, NULL if we have no vcpu to run */
207 ld r4,HSTATE_KVM_VCPU(r13)
209 /* if we have no vcpu to run, go back to sleep */
213 27: /* XXX should handle hypervisor maintenance interrupts etc. here */
215 28: /* SRR1 said external but ICP said nope?? */
217 29: /* External non-IPI interrupt to offline secondary thread? help?? */
218 stw r8,HSTATE_SAVED_XIRR(r13)
221 30: bl kvmppc_hv_entry
223 /* Back from the guest, go back to nap */
224 /* Clear our vcpu pointer so we don't come back in early */
226 std r0, HSTATE_KVM_VCPU(r13)
228 /* Clear any pending IPI - we're an offline thread */
229 ld r5, HSTATE_XICS_PHYS(r13)
231 lwzcix r3, r5, r7 /* ack any pending interrupt */
232 rlwinm. r0, r3, 0, 0xffffff /* any pending? */
237 stbcix r0, r5, r6 /* clear the IPI */
238 stwcix r3, r5, r7 /* EOI it */
241 /* increment the nap count and then go to nap mode */
242 ld r4, HSTATE_KVM_VCORE(r13)
243 addi r4, r4, VCORE_NAP_COUNT
244 lwsync /* make previous updates visible */
251 li r0, KVM_HWTHREAD_IN_NAP
252 stb r0, HSTATE_HWTHREAD_STATE(r13)
255 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
258 std r0, HSTATE_SCRATCH0(r13)
260 ld r0, HSTATE_SCRATCH0(r13)
266 /******************************************************************************
270 *****************************************************************************/
272 .global kvmppc_hv_entry
281 * all other volatile GPRS = free
284 std r0, PPC_LR_STKOFF(r1)
287 /* Set partition DABR */
288 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
295 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
297 /* Load guest PMU registers */
298 /* R4 is live here (vcpu pointer) */
300 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
301 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
303 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
304 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
305 lwz r6, VCPU_PMC + 8(r4)
306 lwz r7, VCPU_PMC + 12(r4)
307 lwz r8, VCPU_PMC + 16(r4)
308 lwz r9, VCPU_PMC + 20(r4)
310 lwz r10, VCPU_PMC + 24(r4)
311 lwz r11, VCPU_PMC + 28(r4)
312 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
322 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
324 ld r5, VCPU_MMCR + 8(r4)
325 ld r6, VCPU_MMCR + 16(r4)
335 /* Load up FP, VMX and VSX registers */
338 ld r14, VCPU_GPR(R14)(r4)
339 ld r15, VCPU_GPR(R15)(r4)
340 ld r16, VCPU_GPR(R16)(r4)
341 ld r17, VCPU_GPR(R17)(r4)
342 ld r18, VCPU_GPR(R18)(r4)
343 ld r19, VCPU_GPR(R19)(r4)
344 ld r20, VCPU_GPR(R20)(r4)
345 ld r21, VCPU_GPR(R21)(r4)
346 ld r22, VCPU_GPR(R22)(r4)
347 ld r23, VCPU_GPR(R23)(r4)
348 ld r24, VCPU_GPR(R24)(r4)
349 ld r25, VCPU_GPR(R25)(r4)
350 ld r26, VCPU_GPR(R26)(r4)
351 ld r27, VCPU_GPR(R27)(r4)
352 ld r28, VCPU_GPR(R28)(r4)
353 ld r29, VCPU_GPR(R29)(r4)
354 ld r30, VCPU_GPR(R30)(r4)
355 ld r31, VCPU_GPR(R31)(r4)
358 /* Switch DSCR to guest value */
361 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
364 * Set the decrementer to the guest decrementer.
366 ld r8,VCPU_DEC_EXPIRES(r4)
372 ld r5, VCPU_SPRG0(r4)
373 ld r6, VCPU_SPRG1(r4)
374 ld r7, VCPU_SPRG2(r4)
375 ld r8, VCPU_SPRG3(r4)
381 /* Save R1 in the PACA */
382 std r1, HSTATE_HOST_R1(r13)
384 /* Load up DAR and DSISR */
386 lwz r6, VCPU_DSISR(r4)
390 li r6, KVM_GUEST_MODE_HOST_HV
391 stb r6, HSTATE_IN_GUEST(r13)
394 /* Restore AMR and UAMOR, set AMOR to all 1s */
401 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
411 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
413 * POWER7 host -> guest partition switch code.
414 * We don't have to lock against concurrent tlbies,
415 * but we do have to coordinate across hardware threads.
417 /* Increment entry count iff exit count is zero. */
418 ld r5,HSTATE_KVM_VCORE(r13)
419 addi r9,r5,VCORE_ENTRY_EXIT
421 cmpwi r3,0x100 /* any threads starting to exit? */
422 bge secondary_too_late /* if so we're too late to the party */
427 /* Primary thread switches to guest partition. */
428 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
434 li r0,LPID_RSVD /* switch to reserved LPID */
437 mtspr SPRN_SDR1,r6 /* switch to partition page table */
441 /* See if we need to flush the TLB */
442 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
443 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
444 srdi r6,r6,6 /* doubleword number */
445 sldi r6,r6,3 /* address offset */
447 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
453 23: ldarx r7,0,r6 /* if set, clear the bit */
457 li r6,128 /* and flush the TLB */
459 li r7,0x800 /* IS field = 0b10 */
466 /* Add timebase offset onto timebase */
467 22: ld r8,VCORE_TB_OFFSET(r5)
470 mftb r6 /* current host timebase */
472 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
473 mftb r7 /* check if lower 24 bits overflowed */
478 addis r8,r8,0x100 /* if so, increment upper 40 bits */
481 /* Load guest PCR value to select appropriate compat mode */
482 37: ld r7, VCORE_PCR(r5)
488 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
491 /* Secondary threads wait for primary to have done partition switch */
492 20: lbz r0,VCORE_IN_GUEST(r5)
496 /* Set LPCR and RMOR. */
497 10: ld r8,VCORE_LPCR(r5)
503 /* Increment yield count if they have a VPA */
507 lwz r5, LPPACA_YIELDCOUNT(r3)
509 stw r5, LPPACA_YIELDCOUNT(r3)
511 stb r6, VCPU_VPA_DIRTY(r4)
513 /* Check if HDEC expires soon */
516 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
520 /* Save purr/spurr */
523 std r5,HSTATE_PURR(r13)
524 std r6,HSTATE_SPURR(r13)
532 * PPC970 host -> guest partition switch code.
533 * We have to lock against concurrent tlbies,
534 * using native_tlbie_lock to lock against host tlbies
535 * and kvm->arch.tlbie_lock to lock against guest tlbies.
536 * We also have to invalidate the TLB since its
537 * entries aren't tagged with the LPID.
539 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
541 /* first take native_tlbie_lock */
544 .tc native_tlbie_lock[TC],native_tlbie_lock
546 ld r3,toc_tlbie_lock@toc(2)
547 #ifdef __BIG_ENDIAN__
548 lwz r8,PACA_LOCK_TOKEN(r13)
550 lwz r8,PACAPACAINDEX(r13)
559 ld r5,HSTATE_KVM_VCORE(r13)
560 ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */
562 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
566 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
569 stw r0,0(r3) /* drop native_tlbie_lock */
571 /* invalidate the whole TLB */
580 /* Take the guest's tlbie_lock */
581 addi r3,r9,KVM_TLBIE_LOCK
589 mtspr SPRN_SDR1,r6 /* switch to partition page table */
591 /* Set up HID4 with the guest's LPID etc. */
596 /* drop the guest's tlbie_lock */
600 /* Check if HDEC expires soon */
603 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
607 /* Enable HDEC interrupts */
610 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
620 /* Load up guest SLB entries */
621 31: lwz r5,VCPU_SLB_MAX(r4)
626 1: ld r8,VCPU_SLB_E(r6)
629 addi r6,r6,VCPU_SLB_SIZE
633 /* Restore state of CTRL run bit; assume 1 on entry */
649 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
653 /* r11 = vcpu->arch.msr & ~MSR_HV */
654 rldicl r11, r11, 63 - MSR_HV_LG, 1
655 rotldi r11, r11, 1 + MSR_HV_LG
658 /* Check if we can deliver an external or decrementer interrupt now */
659 ld r0,VCPU_PENDING_EXC(r4)
660 lis r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
670 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
672 li r0,BOOK3S_INTERRUPT_EXTERNAL
676 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
682 li r0,BOOK3S_INTERRUPT_DECREMENTER
685 /* Move SRR0 and SRR1 into the respective regs */
686 5: mtspr SPRN_SRR0, r6
692 * R10: value for HSRR0
693 * R11: value for HSRR1
698 stb r0,VCPU_CEDED(r4) /* cancel cede */
702 /* Activate guest mode, so faults get handled by KVM */
703 li r9, KVM_GUEST_MODE_GUEST_HV
704 stb r9, HSTATE_IN_GUEST(r13)
711 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
714 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
721 ld r1, VCPU_GPR(R1)(r4)
722 ld r2, VCPU_GPR(R2)(r4)
723 ld r3, VCPU_GPR(R3)(r4)
724 ld r5, VCPU_GPR(R5)(r4)
725 ld r6, VCPU_GPR(R6)(r4)
726 ld r7, VCPU_GPR(R7)(r4)
727 ld r8, VCPU_GPR(R8)(r4)
728 ld r9, VCPU_GPR(R9)(r4)
729 ld r10, VCPU_GPR(R10)(r4)
730 ld r11, VCPU_GPR(R11)(r4)
731 ld r12, VCPU_GPR(R12)(r4)
732 ld r13, VCPU_GPR(R13)(r4)
736 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
737 ld r0, VCPU_GPR(R0)(r4)
738 ld r4, VCPU_GPR(R4)(r4)
743 /******************************************************************************
747 *****************************************************************************/
750 * We come here from the first-level interrupt handlers.
752 .globl kvmppc_interrupt_hv
756 * R12 = interrupt vector
758 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
759 * guest R13 saved in SPRN_SCRATCH0
761 /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
762 std r9, HSTATE_HOST_R2(r13)
764 lbz r9, HSTATE_IN_GUEST(r13)
765 cmpwi r9, KVM_GUEST_MODE_HOST_HV
766 beq kvmppc_bad_host_intr
767 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
768 cmpwi r9, KVM_GUEST_MODE_GUEST
769 ld r9, HSTATE_HOST_R2(r13)
770 beq kvmppc_interrupt_pr
772 /* We're now back in the host but in guest MMU context */
773 li r9, KVM_GUEST_MODE_HOST_HV
774 stb r9, HSTATE_IN_GUEST(r13)
776 ld r9, HSTATE_KVM_VCPU(r13)
780 std r0, VCPU_GPR(R0)(r9)
781 std r1, VCPU_GPR(R1)(r9)
782 std r2, VCPU_GPR(R2)(r9)
783 std r3, VCPU_GPR(R3)(r9)
784 std r4, VCPU_GPR(R4)(r9)
785 std r5, VCPU_GPR(R5)(r9)
786 std r6, VCPU_GPR(R6)(r9)
787 std r7, VCPU_GPR(R7)(r9)
788 std r8, VCPU_GPR(R8)(r9)
789 ld r0, HSTATE_HOST_R2(r13)
790 std r0, VCPU_GPR(R9)(r9)
791 std r10, VCPU_GPR(R10)(r9)
792 std r11, VCPU_GPR(R11)(r9)
793 ld r3, HSTATE_SCRATCH0(r13)
794 lwz r4, HSTATE_SCRATCH1(r13)
795 std r3, VCPU_GPR(R12)(r9)
798 ld r3, HSTATE_CFAR(r13)
799 std r3, VCPU_CFAR(r9)
800 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
802 ld r4, HSTATE_PPR(r13)
804 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
806 /* Restore R1/R2 so we can handle faults */
807 ld r1, HSTATE_HOST_R1(r13)
812 std r10, VCPU_SRR0(r9)
813 std r11, VCPU_SRR1(r9)
814 andi. r0, r12, 2 /* need to read HSRR0/1? */
816 mfspr r10, SPRN_HSRR0
817 mfspr r11, SPRN_HSRR1
819 1: std r10, VCPU_PC(r9)
820 std r11, VCPU_MSR(r9)
824 std r3, VCPU_GPR(R13)(r9)
827 stw r12,VCPU_TRAP(r9)
829 /* Save HEIR (HV emulation assist reg) in last_inst
830 if this is an HEI (HV emulation interrupt, e40) */
831 li r3,KVM_INST_FETCH_FAILED
833 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
836 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
837 11: stw r3,VCPU_LAST_INST(r9)
839 /* these are volatile across C function calls */
846 /* If this is a page table miss then see if it's theirs or ours */
847 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
849 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
851 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
853 /* See if this is a leftover HDEC interrupt */
854 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
860 /* See if this is an hcall we can handle in real mode */
861 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
862 beq hcall_try_real_mode
864 /* Only handle external interrupts here on arch 206 and later */
866 b ext_interrupt_to_host
867 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
869 /* External interrupt ? */
870 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
871 bne+ ext_interrupt_to_host
873 /* External interrupt, first check for host_ipi. If this is
874 * set, we know the host wants us out so let's do it now
879 bgt ext_interrupt_to_host
881 /* Allright, looks like an IPI for the guest, we need to set MER */
882 /* Check if any CPU is heading out to the host, if so head out too */
883 ld r5, HSTATE_KVM_VCORE(r13)
884 lwz r0, VCORE_ENTRY_EXIT(r5)
886 bge ext_interrupt_to_host
888 /* See if there is a pending interrupt for the guest */
890 ld r0, VCPU_PENDING_EXC(r9)
891 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
892 rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
893 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
896 /* And if the guest EE is set, we can deliver immediately, else
897 * we return to the guest with MER set
899 andi. r0, r11, MSR_EE
903 li r10, BOOK3S_INTERRUPT_EXTERNAL
904 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
910 ext_interrupt_to_host:
912 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
913 /* Save more register state */
917 stw r7, VCPU_DSISR(r9)
919 /* don't overwrite fault_dar/fault_dsisr if HDSI */
920 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
922 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
923 std r6, VCPU_FAULT_DAR(r9)
924 stw r7, VCPU_FAULT_DSISR(r9)
926 /* See if it is a machine check */
927 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
928 beq machine_check_realmode
931 /* Save guest CTRL register, set runlatch to 1 */
932 6: mfspr r6,SPRN_CTRLF
939 /* Read the guest SLB and save it away */
940 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
946 andis. r0,r8,SLB_ESID_V@h
948 add r8,r8,r6 /* put index in */
950 std r8,VCPU_SLB_E(r7)
951 std r3,VCPU_SLB_V(r7)
952 addi r7,r7,VCPU_SLB_SIZE
956 stw r5,VCPU_SLB_MAX(r9)
959 * Save the guest PURR/SPURR
967 std r6,VCPU_SPURR(r9)
972 * Restore host PURR/SPURR and add guest times
973 * so that the time in the guest gets accounted.
975 ld r3,HSTATE_PURR(r13)
976 ld r4,HSTATE_SPURR(r13)
981 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
989 hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */
992 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
994 * POWER7 guest -> host partition switch code.
995 * We don't have to lock against tlbies but we do
996 * have to coordinate the hardware threads.
998 /* Increment the threads-exiting-guest count in the 0xff00
999 bits of vcore->entry_exit_count */
1001 ld r5,HSTATE_KVM_VCORE(r13)
1002 addi r6,r5,VCORE_ENTRY_EXIT
1010 * At this point we have an interrupt that we have to pass
1011 * up to the kernel or qemu; we can't handle it in real mode.
1012 * Thus we have to do a partition switch, so we have to
1013 * collect the other threads, if we are the first thread
1014 * to take an interrupt. To do this, we set the HDEC to 0,
1015 * which causes an HDEC interrupt in all threads within 2ns
1016 * because the HDEC register is shared between all 4 threads.
1017 * However, we don't need to bother if this is an HDEC
1018 * interrupt, since the other threads will already be on their
1019 * way here in that case.
1021 cmpwi r3,0x100 /* Are we the first here? */
1023 cmpwi r3,1 /* Are any other threads in the guest? */
1025 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1031 * Send an IPI to any napping threads, since an HDEC interrupt
1032 * doesn't wake CPUs up from nap.
1034 lwz r3,VCORE_NAPPING_THREADS(r5)
1035 lwz r4,VCPU_PTID(r9)
1038 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
1040 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
1044 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1047 stbcix r0,r7,r8 /* trigger the IPI */
1049 addi r6,r6,PACA_SIZE
1052 /* Secondary threads wait for primary to do partition switch */
1053 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
1054 ld r5,HSTATE_KVM_VCORE(r13)
1055 lwz r3,VCPU_PTID(r9)
1059 13: lbz r3,VCORE_IN_GUEST(r5)
1065 /* Primary thread waits for all the secondaries to exit guest */
1066 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1073 /* Primary thread switches back to host partition */
1074 ld r6,KVM_HOST_SDR1(r4)
1075 lwz r7,KVM_HOST_LPID(r4)
1076 li r8,LPID_RSVD /* switch to reserved LPID */
1079 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1083 /* Subtract timebase offset from timebase */
1084 ld r8,VCORE_TB_OFFSET(r5)
1087 mftb r6 /* current host timebase */
1089 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1090 mftb r7 /* check if lower 24 bits overflowed */
1095 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1099 17: ld r0, VCORE_PCR(r5)
1105 /* Signal secondary CPUs to continue */
1106 stb r0,VCORE_IN_GUEST(r5)
1107 lis r8,0x7fff /* MAX_INT@h */
1110 16: ld r8,KVM_HOST_LPCR(r4)
1116 * PPC970 guest -> host partition switch code.
1117 * We have to lock against concurrent tlbies, and
1118 * we have to flush the whole TLB.
1120 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
1122 /* Take the guest's tlbie_lock */
1123 #ifdef __BIG_ENDIAN__
1124 lwz r8,PACA_LOCK_TOKEN(r13)
1126 lwz r8,PACAPACAINDEX(r13)
1128 addi r3,r4,KVM_TLBIE_LOCK
1136 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1138 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1142 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1145 stw r0,0(r3) /* drop guest tlbie_lock */
1147 /* invalidate the whole TLB */
1156 /* take native_tlbie_lock */
1157 ld r3,toc_tlbie_lock@toc(2)
1165 ld r6,KVM_HOST_SDR1(r4)
1166 mtspr SPRN_SDR1,r6 /* switch to host page table */
1168 /* Set up host HID4 value */
1173 stw r0,0(r3) /* drop native_tlbie_lock */
1175 lis r8,0x7fff /* MAX_INT@h */
1178 /* Disable HDEC interrupts */
1181 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1191 /* load host SLB entries */
1192 33: ld r8,PACA_SLBSHADOWPTR(r13)
1194 .rept SLB_NUM_BOLTED
1195 ld r5,SLBSHADOW_SAVEAREA(r8)
1196 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1197 andis. r7,r5,SLB_ESID_V@h
1208 std r5,VCPU_DEC_EXPIRES(r9)
1210 /* Save and reset AMR and UAMOR before turning on the MMU */
1215 std r6,VCPU_UAMOR(r9)
1218 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1220 /* Unset guest mode */
1221 li r0, KVM_GUEST_MODE_NONE
1222 stb r0, HSTATE_IN_GUEST(r13)
1224 /* Switch DSCR back to host value */
1227 ld r7, HSTATE_DSCR(r13)
1228 std r8, VCPU_DSCR(r9)
1230 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1232 /* Save non-volatile GPRs */
1233 std r14, VCPU_GPR(R14)(r9)
1234 std r15, VCPU_GPR(R15)(r9)
1235 std r16, VCPU_GPR(R16)(r9)
1236 std r17, VCPU_GPR(R17)(r9)
1237 std r18, VCPU_GPR(R18)(r9)
1238 std r19, VCPU_GPR(R19)(r9)
1239 std r20, VCPU_GPR(R20)(r9)
1240 std r21, VCPU_GPR(R21)(r9)
1241 std r22, VCPU_GPR(R22)(r9)
1242 std r23, VCPU_GPR(R23)(r9)
1243 std r24, VCPU_GPR(R24)(r9)
1244 std r25, VCPU_GPR(R25)(r9)
1245 std r26, VCPU_GPR(R26)(r9)
1246 std r27, VCPU_GPR(R27)(r9)
1247 std r28, VCPU_GPR(R28)(r9)
1248 std r29, VCPU_GPR(R29)(r9)
1249 std r30, VCPU_GPR(R30)(r9)
1250 std r31, VCPU_GPR(R31)(r9)
1253 mfspr r3, SPRN_SPRG0
1254 mfspr r4, SPRN_SPRG1
1255 mfspr r5, SPRN_SPRG2
1256 mfspr r6, SPRN_SPRG3
1257 std r3, VCPU_SPRG0(r9)
1258 std r4, VCPU_SPRG1(r9)
1259 std r5, VCPU_SPRG2(r9)
1260 std r6, VCPU_SPRG3(r9)
1266 /* Increment yield count if they have a VPA */
1267 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1270 lwz r3, LPPACA_YIELDCOUNT(r8)
1272 stw r3, LPPACA_YIELDCOUNT(r8)
1274 stb r3, VCPU_VPA_DIRTY(r9)
1276 /* Save PMU registers if requested */
1277 /* r8 and cr0.eq are live here */
1279 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1280 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1281 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1282 mfspr r6, SPRN_MMCRA
1284 /* On P7, clear MMCRA in order to disable SDAR updates */
1286 mtspr SPRN_MMCRA, r7
1287 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1289 beq 21f /* if no VPA, save PMU stuff anyway */
1290 lbz r7, LPPACA_PMCINUSE(r8)
1291 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1293 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1295 21: mfspr r5, SPRN_MMCR1
1298 std r4, VCPU_MMCR(r9)
1299 std r5, VCPU_MMCR + 8(r9)
1300 std r6, VCPU_MMCR + 16(r9)
1301 std r7, VCPU_SIAR(r9)
1302 std r8, VCPU_SDAR(r9)
1310 mfspr r10, SPRN_PMC7
1311 mfspr r11, SPRN_PMC8
1312 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1313 stw r3, VCPU_PMC(r9)
1314 stw r4, VCPU_PMC + 4(r9)
1315 stw r5, VCPU_PMC + 8(r9)
1316 stw r6, VCPU_PMC + 12(r9)
1317 stw r7, VCPU_PMC + 16(r9)
1318 stw r8, VCPU_PMC + 20(r9)
1320 stw r10, VCPU_PMC + 24(r9)
1321 stw r11, VCPU_PMC + 28(r9)
1322 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1324 ld r0, 112+PPC_LR_STKOFF(r1)
1329 ld r5,HSTATE_KVM_VCORE(r13)
1331 13: lbz r3,VCORE_IN_GUEST(r5)
1335 li r0, KVM_GUEST_MODE_NONE
1336 stb r0, HSTATE_IN_GUEST(r13)
1337 ld r11,PACA_SLBSHADOWPTR(r13)
1339 .rept SLB_NUM_BOLTED
1340 ld r5,SLBSHADOW_SAVEAREA(r11)
1341 ld r6,SLBSHADOW_SAVEAREA+8(r11)
1342 andis. r7,r5,SLB_ESID_V@h
1350 * Check whether an HDSI is an HPTE not found fault or something else.
1351 * If it is an HPTE not found fault that is due to the guest accessing
1352 * a page that they have mapped but which we have paged out, then
1353 * we continue on with the guest exit path. In all other cases,
1354 * reflect the HDSI to the guest as a DSI.
1358 mfspr r6, SPRN_HDSISR
1359 /* HPTE not found fault or protection fault? */
1360 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1361 beq 1f /* if not, send it to the guest */
1362 andi. r0, r11, MSR_DR /* data relocation enabled? */
1365 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1366 bne 1f /* if no SLB entry found */
1367 4: std r4, VCPU_FAULT_DAR(r9)
1368 stw r6, VCPU_FAULT_DSISR(r9)
1370 /* Search the hash table. */
1371 mr r3, r9 /* vcpu pointer */
1372 li r7, 1 /* data fault */
1373 bl .kvmppc_hpte_hv_fault
1374 ld r9, HSTATE_KVM_VCPU(r13)
1376 ld r11, VCPU_MSR(r9)
1377 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1378 cmpdi r3, 0 /* retry the instruction */
1380 cmpdi r3, -1 /* handle in kernel mode */
1382 cmpdi r3, -2 /* MMIO emulation; need instr word */
1385 /* Synthesize a DSI for the guest */
1386 ld r4, VCPU_FAULT_DAR(r9)
1388 1: mtspr SPRN_DAR, r4
1389 mtspr SPRN_DSISR, r6
1390 mtspr SPRN_SRR0, r10
1391 mtspr SPRN_SRR1, r11
1392 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1393 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1395 fast_interrupt_c_return:
1396 6: ld r7, VCPU_CTR(r9)
1397 lwz r8, VCPU_XER(r9)
1403 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1404 ld r5, KVM_VRMA_SLB_V(r5)
1407 /* If this is for emulated MMIO, load the instruction word */
1408 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1410 /* Set guest mode to 'jump over instruction' so if lwz faults
1411 * we'll just continue at the next IP. */
1412 li r0, KVM_GUEST_MODE_SKIP
1413 stb r0, HSTATE_IN_GUEST(r13)
1415 /* Do the access with MSR:DR enabled */
1417 ori r4, r3, MSR_DR /* Enable paging for data */
1422 /* Store the result */
1423 stw r8, VCPU_LAST_INST(r9)
1425 /* Unset guest mode. */
1426 li r0, KVM_GUEST_MODE_HOST_HV
1427 stb r0, HSTATE_IN_GUEST(r13)
1431 * Similarly for an HISI, reflect it to the guest as an ISI unless
1432 * it is an HPTE not found fault for a page that we have paged out.
1435 andis. r0, r11, SRR1_ISI_NOPT@h
1437 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1440 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1441 bne 1f /* if no SLB entry found */
1443 /* Search the hash table. */
1444 mr r3, r9 /* vcpu pointer */
1447 li r7, 0 /* instruction fault */
1448 bl .kvmppc_hpte_hv_fault
1449 ld r9, HSTATE_KVM_VCPU(r13)
1451 ld r11, VCPU_MSR(r9)
1452 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1453 cmpdi r3, 0 /* retry the instruction */
1454 beq fast_interrupt_c_return
1455 cmpdi r3, -1 /* handle in kernel mode */
1458 /* Synthesize an ISI for the guest */
1460 1: mtspr SPRN_SRR0, r10
1461 mtspr SPRN_SRR1, r11
1462 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1463 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1465 b fast_interrupt_c_return
1467 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1468 ld r5, KVM_VRMA_SLB_V(r6)
1472 * Try to handle an hcall in real mode.
1473 * Returns to the guest if we handle it, or continues on up to
1474 * the kernel if we can't (i.e. if we don't have a handler for
1475 * it, or if the handler returns H_TOO_HARD).
1477 .globl hcall_try_real_mode
1478 hcall_try_real_mode:
1479 ld r3,VCPU_GPR(R3)(r9)
1481 /* sc 1 from userspace - reflect to guest syscall */
1482 bne sc_1_fast_return
1484 cmpldi r3,hcall_real_table_end - hcall_real_table
1486 LOAD_REG_ADDR(r4, hcall_real_table)
1492 mr r3,r9 /* get vcpu pointer */
1493 ld r4,VCPU_GPR(R4)(r9)
1496 beq hcall_real_fallback
1497 ld r4,HSTATE_KVM_VCPU(r13)
1498 std r3,VCPU_GPR(R3)(r4)
1506 li r10, BOOK3S_INTERRUPT_SYSCALL
1507 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1512 /* We've attempted a real mode hcall, but it's punted it back
1513 * to userspace. We need to restore some clobbered volatiles
1514 * before resuming the pass-it-to-qemu path */
1515 hcall_real_fallback:
1516 li r12,BOOK3S_INTERRUPT_SYSCALL
1517 ld r9, HSTATE_KVM_VCPU(r13)
1521 .globl hcall_real_table
1523 .long 0 /* 0 - unused */
1524 .long .kvmppc_h_remove - hcall_real_table
1525 .long .kvmppc_h_enter - hcall_real_table
1526 .long .kvmppc_h_read - hcall_real_table
1527 .long 0 /* 0x10 - H_CLEAR_MOD */
1528 .long 0 /* 0x14 - H_CLEAR_REF */
1529 .long .kvmppc_h_protect - hcall_real_table
1530 .long 0 /* 0x1c - H_GET_TCE */
1531 .long .kvmppc_h_put_tce - hcall_real_table
1532 .long 0 /* 0x24 - H_SET_SPRG0 */
1533 .long .kvmppc_h_set_dabr - hcall_real_table
1548 #ifdef CONFIG_KVM_XICS
1549 .long .kvmppc_rm_h_eoi - hcall_real_table
1550 .long .kvmppc_rm_h_cppr - hcall_real_table
1551 .long .kvmppc_rm_h_ipi - hcall_real_table
1552 .long 0 /* 0x70 - H_IPOLL */
1553 .long .kvmppc_rm_h_xirr - hcall_real_table
1555 .long 0 /* 0x64 - H_EOI */
1556 .long 0 /* 0x68 - H_CPPR */
1557 .long 0 /* 0x6c - H_IPI */
1558 .long 0 /* 0x70 - H_IPOLL */
1559 .long 0 /* 0x74 - H_XIRR */
1587 .long .kvmppc_h_cede - hcall_real_table
1604 .long .kvmppc_h_bulk_remove - hcall_real_table
1605 hcall_real_table_end:
1611 _GLOBAL(kvmppc_h_set_dabr)
1612 std r4,VCPU_DABR(r3)
1613 /* Work around P7 bug where DABR can get corrupted on mtspr */
1614 1: mtspr SPRN_DABR,r4
1622 _GLOBAL(kvmppc_h_cede)
1624 std r11,VCPU_MSR(r3)
1626 stb r0,VCPU_CEDED(r3)
1627 sync /* order setting ceded vs. testing prodded */
1628 lbz r5,VCPU_PRODDED(r3)
1630 bne kvm_cede_prodded
1631 li r0,0 /* set trap to 0 to say hcall is handled */
1632 stw r0,VCPU_TRAP(r3)
1634 std r0,VCPU_GPR(R3)(r3)
1636 b kvm_cede_exit /* just send it up to host on 970 */
1637 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1640 * Set our bit in the bitmask of napping threads unless all the
1641 * other threads are already napping, in which case we send this
1644 ld r5,HSTATE_KVM_VCORE(r13)
1645 lwz r6,VCPU_PTID(r3)
1646 lwz r8,VCORE_ENTRY_EXIT(r5)
1650 addi r6,r5,VCORE_NAPPING_THREADS
1659 stb r0,HSTATE_NAPPING(r13)
1660 /* order napping_threads update vs testing entry_exit_count */
1663 lwz r7,VCORE_ENTRY_EXIT(r5)
1665 bge 33f /* another thread already exiting */
1668 * Although not specifically required by the architecture, POWER7
1669 * preserves the following registers in nap mode, even if an SMT mode
1670 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1671 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1673 /* Save non-volatile GPRs */
1674 std r14, VCPU_GPR(R14)(r3)
1675 std r15, VCPU_GPR(R15)(r3)
1676 std r16, VCPU_GPR(R16)(r3)
1677 std r17, VCPU_GPR(R17)(r3)
1678 std r18, VCPU_GPR(R18)(r3)
1679 std r19, VCPU_GPR(R19)(r3)
1680 std r20, VCPU_GPR(R20)(r3)
1681 std r21, VCPU_GPR(R21)(r3)
1682 std r22, VCPU_GPR(R22)(r3)
1683 std r23, VCPU_GPR(R23)(r3)
1684 std r24, VCPU_GPR(R24)(r3)
1685 std r25, VCPU_GPR(R25)(r3)
1686 std r26, VCPU_GPR(R26)(r3)
1687 std r27, VCPU_GPR(R27)(r3)
1688 std r28, VCPU_GPR(R28)(r3)
1689 std r29, VCPU_GPR(R29)(r3)
1690 std r30, VCPU_GPR(R30)(r3)
1691 std r31, VCPU_GPR(R31)(r3)
1697 * Take a nap until a decrementer or external interrupt occurs,
1698 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1701 stb r0,HSTATE_HWTHREAD_REQ(r13)
1703 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
1707 std r0, HSTATE_SCRATCH0(r13)
1709 ld r0, HSTATE_SCRATCH0(r13)
1716 /* get vcpu pointer */
1717 ld r4, HSTATE_KVM_VCPU(r13)
1719 /* Woken by external or decrementer interrupt */
1720 ld r1, HSTATE_HOST_R1(r13)
1722 /* load up FP state */
1726 ld r14, VCPU_GPR(R14)(r4)
1727 ld r15, VCPU_GPR(R15)(r4)
1728 ld r16, VCPU_GPR(R16)(r4)
1729 ld r17, VCPU_GPR(R17)(r4)
1730 ld r18, VCPU_GPR(R18)(r4)
1731 ld r19, VCPU_GPR(R19)(r4)
1732 ld r20, VCPU_GPR(R20)(r4)
1733 ld r21, VCPU_GPR(R21)(r4)
1734 ld r22, VCPU_GPR(R22)(r4)
1735 ld r23, VCPU_GPR(R23)(r4)
1736 ld r24, VCPU_GPR(R24)(r4)
1737 ld r25, VCPU_GPR(R25)(r4)
1738 ld r26, VCPU_GPR(R26)(r4)
1739 ld r27, VCPU_GPR(R27)(r4)
1740 ld r28, VCPU_GPR(R28)(r4)
1741 ld r29, VCPU_GPR(R29)(r4)
1742 ld r30, VCPU_GPR(R30)(r4)
1743 ld r31, VCPU_GPR(R31)(r4)
1745 /* clear our bit in vcore->napping_threads */
1746 33: ld r5,HSTATE_KVM_VCORE(r13)
1747 lwz r3,VCPU_PTID(r4)
1750 addi r6,r5,VCORE_NAPPING_THREADS
1756 stb r0,HSTATE_NAPPING(r13)
1758 /* Check the wake reason in SRR1 to see why we got here */
1760 rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */
1761 cmpwi r3, 4 /* was it an external interrupt? */
1762 li r12, BOOK3S_INTERRUPT_EXTERNAL
1765 ld r11, VCPU_MSR(r9)
1766 beq do_ext_interrupt /* if so */
1768 /* see if any other thread is already exiting */
1769 lwz r0,VCORE_ENTRY_EXIT(r5)
1771 blt kvmppc_cede_reentry /* if not go back to guest */
1773 /* some threads are exiting, so go to the guest exit path */
1774 b hcall_real_fallback
1776 /* cede when already previously prodded case */
1779 stb r0,VCPU_PRODDED(r3)
1780 sync /* order testing prodded vs. clearing ceded */
1781 stb r0,VCPU_CEDED(r3)
1785 /* we've ceded but we want to give control to the host */
1787 b hcall_real_fallback
1789 /* Try to handle a machine check in real mode */
1790 machine_check_realmode:
1791 mr r3, r9 /* get vcpu pointer */
1792 bl .kvmppc_realmode_machine_check
1794 cmpdi r3, 0 /* continue exiting from guest? */
1795 ld r9, HSTATE_KVM_VCPU(r13)
1796 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1798 /* If not, deliver a machine check. SRR0/1 are already set */
1799 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
1800 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1802 b fast_interrupt_c_return
1805 * Determine what sort of external interrupt is pending (if any).
1807 * 0 if no interrupt is pending
1808 * 1 if an interrupt is pending that needs to be handled by the host
1809 * -1 if there was a guest wakeup IPI (which has now been cleared)
1812 /* see if a host IPI is pending */
1814 lbz r0, HSTATE_HOST_IPI(r13)
1818 /* Now read the interrupt from the ICP */
1819 ld r6, HSTATE_XICS_PHYS(r13)
1824 rlwinm. r3, r0, 0, 0xffffff
1826 beq 1f /* if nothing pending in the ICP */
1828 /* We found something in the ICP...
1830 * If it's not an IPI, stash it in the PACA and return to
1831 * the host, we don't (yet) handle directing real external
1832 * interrupts directly to the guest
1834 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
1838 /* It's an IPI, clear the MFRR and EOI it */
1841 stbcix r3, r6, r8 /* clear the IPI */
1842 stwcix r0, r6, r7 /* EOI it */
1845 /* We need to re-check host IPI now in case it got set in the
1846 * meantime. If it's clear, we bounce the interrupt to the
1849 lbz r0, HSTATE_HOST_IPI(r13)
1853 /* OK, it's an IPI for us */
1857 42: /* It's not an IPI and it's for the host, stash it in the PACA
1858 * before exit, it will be picked up by the host ICP driver
1860 stw r0, HSTATE_SAVED_XIRR(r13)
1863 43: /* We raced with the host, we need to resend that IPI, bummer */
1865 stbcix r0, r6, r8 /* set the IPI */
1870 * Save away FP, VMX and VSX registers.
1872 * N.B. r30 and r31 are volatile across this function,
1873 * thus it is not callable from C.
1880 #ifdef CONFIG_ALTIVEC
1882 oris r8,r8,MSR_VEC@h
1883 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1887 oris r8,r8,MSR_VSX@h
1888 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1892 addi r3,r3,VCPU_FPRS
1894 #ifdef CONFIG_ALTIVEC
1896 addi r3,r31,VCPU_VRS
1898 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1900 mfspr r6,SPRN_VRSAVE
1901 stw r6,VCPU_VRSAVE(r3)
1908 * Load up FP, VMX and VSX registers
1910 * N.B. r30 and r31 are volatile across this function,
1911 * thus it is not callable from C.
1918 #ifdef CONFIG_ALTIVEC
1920 oris r8,r8,MSR_VEC@h
1921 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1925 oris r8,r8,MSR_VSX@h
1926 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1930 addi r3,r4,VCPU_FPRS
1932 #ifdef CONFIG_ALTIVEC
1934 addi r3,r31,VCPU_VRS
1936 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1938 lwz r7,VCPU_VRSAVE(r4)
1939 mtspr SPRN_VRSAVE,r7
1945 * We come here if we get any exception or interrupt while we are
1946 * executing host real mode code while in guest MMU context.
1947 * For now just spin, but we should do something better.
1949 kvmppc_bad_host_intr: