Pileus Git - ~andy/linux/blob - arch/powerpc/kvm/book3s_64_emulate.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License, version 2, as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program; if not, write to the Free Software
  13  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  14  *
  15  * Copyright SUSE Linux Products GmbH 2009
  16  *
  17  * Authors: Alexander Graf <agraf@suse.de>
  18  */
  19
  20 #include <asm/kvm_ppc.h>
  21 #include <asm/disassemble.h>
  22 #include <asm/kvm_book3s.h>
  23 #include <asm/reg.h>
  24
  25 #define OP_19_XOP_RFID          18
  26 #define OP_19_XOP_RFI           50
  27
  28 #define OP_31_XOP_MFMSR         83
  29 #define OP_31_XOP_MTMSR         146
  30 #define OP_31_XOP_MTMSRD        178
  31 #define OP_31_XOP_MTSR          210
  32 #define OP_31_XOP_MTSRIN        242
  33 #define OP_31_XOP_TLBIEL        274
  34 #define OP_31_XOP_TLBIE         306
  35 #define OP_31_XOP_SLBMTE        402
  36 #define OP_31_XOP_SLBIE         434
  37 #define OP_31_XOP_SLBIA         498
  38 #define OP_31_XOP_MFSRIN        659
  39 #define OP_31_XOP_SLBMFEV       851
  40 #define OP_31_XOP_EIOIO         854
  41 #define OP_31_XOP_SLBMFEE       915
  42
  43 /* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */
  44 #define OP_31_XOP_DCBZ          1010
  45
  46 #define SPRN_GQR0               912
  47 #define SPRN_GQR1               913
  48 #define SPRN_GQR2               914
  49 #define SPRN_GQR3               915
  50 #define SPRN_GQR4               916
  51 #define SPRN_GQR5               917
  52 #define SPRN_GQR6               918
  53 #define SPRN_GQR7               919
  54
  55 int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
  56                            unsigned int inst, int *advance)
  57 {
  58         int emulated = EMULATE_DONE;
  59
  60         switch (get_op(inst)) {
  61         case 19:
  62                 switch (get_xop(inst)) {
  63                 case OP_19_XOP_RFID:
  64                 case OP_19_XOP_RFI:
  65                         vcpu->arch.pc = vcpu->arch.srr0;
  66                         kvmppc_set_msr(vcpu, vcpu->arch.srr1);
  67                         *advance = 0;
  68                         break;
  69
  70                 default:
  71                         emulated = EMULATE_FAIL;
  72                         break;
  73                 }
  74                 break;
  75         case 31:
  76                 switch (get_xop(inst)) {
  77                 case OP_31_XOP_MFMSR:
  78                         kvmppc_set_gpr(vcpu, get_rt(inst), vcpu->arch.msr);
  79                         break;
  80                 case OP_31_XOP_MTMSRD:
  81                 {
  82                         ulong rs = kvmppc_get_gpr(vcpu, get_rs(inst));
  83                         if (inst & 0x10000) {
  84                                 vcpu->arch.msr &= ~(MSR_RI | MSR_EE);
  85                                 vcpu->arch.msr |= rs & (MSR_RI | MSR_EE);
  86                         } else
  87                                 kvmppc_set_msr(vcpu, rs);
  88                         break;
  89                 }
  90                 case OP_31_XOP_MTMSR:
  91                         kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, get_rs(inst)));
  92                         break;
  93                 case OP_31_XOP_MFSRIN:
  94                 {
  95                         int srnum;
  96
  97                         srnum = (kvmppc_get_gpr(vcpu, get_rb(inst)) >> 28) & 0xf;
  98                         if (vcpu->arch.mmu.mfsrin) {
  99                                 u32 sr;
 100                                 sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
 101                                 kvmppc_set_gpr(vcpu, get_rt(inst), sr);
 102                         }
 103                         break;
 104                 }
 105                 case OP_31_XOP_MTSR:
 106                         vcpu->arch.mmu.mtsrin(vcpu,
 107                                 (inst >> 16) & 0xf,
 108                                 kvmppc_get_gpr(vcpu, get_rs(inst)));
 109                         break;
 110                 case OP_31_XOP_MTSRIN:
 111                         vcpu->arch.mmu.mtsrin(vcpu,
 112                                 (kvmppc_get_gpr(vcpu, get_rb(inst)) >> 28) & 0xf,
 113                                 kvmppc_get_gpr(vcpu, get_rs(inst)));
 114                         break;
 115                 case OP_31_XOP_TLBIE:
 116                 case OP_31_XOP_TLBIEL:
 117                 {
 118                         bool large = (inst & 0x00200000) ? true : false;
 119                         ulong addr = kvmppc_get_gpr(vcpu, get_rb(inst));
 120                         vcpu->arch.mmu.tlbie(vcpu, addr, large);
 121                         break;
 122                 }
 123                 case OP_31_XOP_EIOIO:
 124                         break;
 125                 case OP_31_XOP_SLBMTE:
 126                         if (!vcpu->arch.mmu.slbmte)
 127                                 return EMULATE_FAIL;
 128
 129                         vcpu->arch.mmu.slbmte(vcpu,
 130                                         kvmppc_get_gpr(vcpu, get_rs(inst)),
 131                                         kvmppc_get_gpr(vcpu, get_rb(inst)));
 132                         break;
 133                 case OP_31_XOP_SLBIE:
 134                         if (!vcpu->arch.mmu.slbie)
 135                                 return EMULATE_FAIL;
 136
 137                         vcpu->arch.mmu.slbie(vcpu,
 138                                         kvmppc_get_gpr(vcpu, get_rb(inst)));
 139                         break;
 140                 case OP_31_XOP_SLBIA:
 141                         if (!vcpu->arch.mmu.slbia)
 142                                 return EMULATE_FAIL;
 143
 144                         vcpu->arch.mmu.slbia(vcpu);
 145                         break;
 146                 case OP_31_XOP_SLBMFEE:
 147                         if (!vcpu->arch.mmu.slbmfee) {
 148                                 emulated = EMULATE_FAIL;
 149                         } else {
 150                                 ulong t, rb;
 151
 152                                 rb = kvmppc_get_gpr(vcpu, get_rb(inst));
 153                                 t = vcpu->arch.mmu.slbmfee(vcpu, rb);
 154                                 kvmppc_set_gpr(vcpu, get_rt(inst), t);
 155                         }
 156                         break;
 157                 case OP_31_XOP_SLBMFEV:
 158                         if (!vcpu->arch.mmu.slbmfev) {
 159                                 emulated = EMULATE_FAIL;
 160                         } else {
 161                                 ulong t, rb;
 162
 163                                 rb = kvmppc_get_gpr(vcpu, get_rb(inst));
 164                                 t = vcpu->arch.mmu.slbmfev(vcpu, rb);
 165                                 kvmppc_set_gpr(vcpu, get_rt(inst), t);
 166                         }
 167                         break;
 168                 case OP_31_XOP_DCBZ:
 169                 {
 170                         ulong rb = kvmppc_get_gpr(vcpu, get_rb(inst));
 171                         ulong ra = 0;
 172                         ulong addr, vaddr;
 173                         u32 zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
 174
 175                         if (get_ra(inst))
 176                                 ra = kvmppc_get_gpr(vcpu, get_ra(inst));
 177
 178                         addr = (ra + rb) & ~31ULL;
 179                         if (!(vcpu->arch.msr & MSR_SF))
 180                                 addr &= 0xffffffff;
 181                         vaddr = addr;
 182
 183                         if (kvmppc_st(vcpu, &addr, 32, zeros, true)) {
 184                                 vcpu->arch.dear = vaddr;
 185                                 vcpu->arch.fault_dear = vaddr;
 186                                 to_book3s(vcpu)->dsisr = DSISR_PROTFAULT |
 187                                                       DSISR_ISSTORE;
 188                                 kvmppc_book3s_queue_irqprio(vcpu,
 189                                         BOOK3S_INTERRUPT_DATA_STORAGE);
 190                                 kvmppc_mmu_pte_flush(vcpu, vaddr, ~0xFFFULL);
 191                         }
 192
 193                         break;
 194                 }
 195                 default:
 196                         emulated = EMULATE_FAIL;
 197                 }
 198                 break;
 199         default:
 200                 emulated = EMULATE_FAIL;
 201         }
 202
 203         return emulated;
 204 }
 205
 206 void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat, bool upper,
 207                     u32 val)
 208 {
 209         if (upper) {
 210                 /* Upper BAT */
 211                 u32 bl = (val >> 2) & 0x7ff;
 212                 bat->bepi_mask = (~bl << 17);
 213                 bat->bepi = val & 0xfffe0000;
 214                 bat->vs = (val & 2) ? 1 : 0;
 215                 bat->vp = (val & 1) ? 1 : 0;
 216                 bat->raw = (bat->raw & 0xffffffff00000000ULL) | val;
 217         } else {
 218                 /* Lower BAT */
 219                 bat->brpn = val & 0xfffe0000;
 220                 bat->wimg = (val >> 3) & 0xf;
 221                 bat->pp = val & 3;
 222                 bat->raw = (bat->raw & 0x00000000ffffffffULL) | ((u64)val << 32);
 223         }
 224 }
 225
 226 static void kvmppc_write_bat(struct kvm_vcpu *vcpu, int sprn, u32 val)
 227 {
 228         struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
 229         struct kvmppc_bat *bat;
 230
 231         switch (sprn) {
 232         case SPRN_IBAT0U ... SPRN_IBAT3L:
 233                 bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2];
 234                 break;
 235         case SPRN_IBAT4U ... SPRN_IBAT7L:
 236                 bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT4U) / 2];
 237                 break;
 238         case SPRN_DBAT0U ... SPRN_DBAT3L:
 239                 bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2];
 240                 break;
 241         case SPRN_DBAT4U ... SPRN_DBAT7L:
 242                 bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT4U) / 2];
 243                 break;
 244         default:
 245                 BUG();
 246         }
 247
 248         kvmppc_set_bat(vcpu, bat, !(sprn % 2), val);
 249 }
 250
 251 int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs)
 252 {
 253         int emulated = EMULATE_DONE;
 254         ulong spr_val = kvmppc_get_gpr(vcpu, rs);
 255
 256         switch (sprn) {
 257         case SPRN_SDR1:
 258                 to_book3s(vcpu)->sdr1 = spr_val;
 259                 break;
 260         case SPRN_DSISR:
 261                 to_book3s(vcpu)->dsisr = spr_val;
 262                 break;
 263         case SPRN_DAR:
 264                 vcpu->arch.dear = spr_val;
 265                 break;
 266         case SPRN_HIOR:
 267                 to_book3s(vcpu)->hior = spr_val;
 268                 break;
 269         case SPRN_IBAT0U ... SPRN_IBAT3L:
 270         case SPRN_IBAT4U ... SPRN_IBAT7L:
 271         case SPRN_DBAT0U ... SPRN_DBAT3L:
 272         case SPRN_DBAT4U ... SPRN_DBAT7L:
 273                 kvmppc_write_bat(vcpu, sprn, (u32)spr_val);
 274                 /* BAT writes happen so rarely that we're ok to flush
 275                  * everything here */
 276                 kvmppc_mmu_pte_flush(vcpu, 0, 0);
 277                 break;
 278         case SPRN_HID0:
 279                 to_book3s(vcpu)->hid[0] = spr_val;
 280                 break;
 281         case SPRN_HID1:
 282                 to_book3s(vcpu)->hid[1] = spr_val;
 283                 break;
 284         case SPRN_HID2:
 285                 to_book3s(vcpu)->hid[2] = spr_val;
 286                 break;
 287         case SPRN_HID2_GEKKO:
 288                 to_book3s(vcpu)->hid[2] = spr_val;
 289                 /* HID2.PSE controls paired single on gekko */
 290                 switch (vcpu->arch.pvr) {
 291                 case 0x00080200:        /* lonestar 2.0 */
 292                 case 0x00088202:        /* lonestar 2.2 */
 293                 case 0x70000100:        /* gekko 1.0 */
 294                 case 0x00080100:        /* gekko 2.0 */
 295                 case 0x00083203:        /* gekko 2.3a */
 296                 case 0x00083213:        /* gekko 2.3b */
 297                 case 0x00083204:        /* gekko 2.4 */
 298                 case 0x00083214:        /* gekko 2.4e (8SE) - retail HW2 */
 299                         if (spr_val & (1 << 29)) { /* HID2.PSE */
 300                                 vcpu->arch.hflags |= BOOK3S_HFLAG_PAIRED_SINGLE;
 301                                 kvmppc_giveup_ext(vcpu, MSR_FP);
 302                         } else {
 303                                 vcpu->arch.hflags &= ~BOOK3S_HFLAG_PAIRED_SINGLE;
 304                         }
 305                         break;
 306                 }
 307                 break;
 308         case SPRN_HID4:
 309         case SPRN_HID4_GEKKO:
 310                 to_book3s(vcpu)->hid[4] = spr_val;
 311                 break;
 312         case SPRN_HID5:
 313                 to_book3s(vcpu)->hid[5] = spr_val;
 314                 /* guest HID5 set can change is_dcbz32 */
 315                 if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
 316                     (mfmsr() & MSR_HV))
 317                         vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
 318                 break;
 319         case SPRN_GQR0:
 320         case SPRN_GQR1:
 321         case SPRN_GQR2:
 322         case SPRN_GQR3:
 323         case SPRN_GQR4:
 324         case SPRN_GQR5:
 325         case SPRN_GQR6:
 326         case SPRN_GQR7:
 327                 to_book3s(vcpu)->gqr[sprn - SPRN_GQR0] = spr_val;
 328                 break;
 329         case SPRN_ICTC:
 330         case SPRN_THRM1:
 331         case SPRN_THRM2:
 332         case SPRN_THRM3:
 333         case SPRN_CTRLF:
 334         case SPRN_CTRLT:
 335         case SPRN_L2CR:
 336         case SPRN_MMCR0_GEKKO:
 337         case SPRN_MMCR1_GEKKO:
 338         case SPRN_PMC1_GEKKO:
 339         case SPRN_PMC2_GEKKO:
 340         case SPRN_PMC3_GEKKO:
 341         case SPRN_PMC4_GEKKO:
 342         case SPRN_WPAR_GEKKO:
 343                 break;
 344         default:
 345                 printk(KERN_INFO "KVM: invalid SPR write: %d\n", sprn);
 346 #ifndef DEBUG_SPR
 347                 emulated = EMULATE_FAIL;
 348 #endif
 349                 break;
 350         }
 351
 352         return emulated;
 353 }
 354
 355 int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
 356 {
 357         int emulated = EMULATE_DONE;
 358
 359         switch (sprn) {
 360         case SPRN_SDR1:
 361                 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->sdr1);
 362                 break;
 363         case SPRN_DSISR:
 364                 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->dsisr);
 365                 break;
 366         case SPRN_DAR:
 367                 kvmppc_set_gpr(vcpu, rt, vcpu->arch.dear);
 368                 break;
 369         case SPRN_HIOR:
 370                 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hior);
 371                 break;
 372         case SPRN_HID0:
 373                 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[0]);
 374                 break;
 375         case SPRN_HID1:
 376                 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[1]);
 377                 break;
 378         case SPRN_HID2:
 379         case SPRN_HID2_GEKKO:
 380                 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[2]);
 381                 break;
 382         case SPRN_HID4:
 383         case SPRN_HID4_GEKKO:
 384                 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[4]);
 385                 break;
 386         case SPRN_HID5:
 387                 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[5]);
 388                 break;
 389         case SPRN_GQR0:
 390         case SPRN_GQR1:
 391         case SPRN_GQR2:
 392         case SPRN_GQR3:
 393         case SPRN_GQR4:
 394         case SPRN_GQR5:
 395         case SPRN_GQR6:
 396         case SPRN_GQR7:
 397                 kvmppc_set_gpr(vcpu, rt,
 398                                to_book3s(vcpu)->gqr[sprn - SPRN_GQR0]);
 399                 break;
 400         case SPRN_THRM1:
 401         case SPRN_THRM2:
 402         case SPRN_THRM3:
 403         case SPRN_CTRLF:
 404         case SPRN_CTRLT:
 405         case SPRN_L2CR:
 406         case SPRN_MMCR0_GEKKO:
 407         case SPRN_MMCR1_GEKKO:
 408         case SPRN_PMC1_GEKKO:
 409         case SPRN_PMC2_GEKKO:
 410         case SPRN_PMC3_GEKKO:
 411         case SPRN_PMC4_GEKKO:
 412         case SPRN_WPAR_GEKKO:
 413                 kvmppc_set_gpr(vcpu, rt, 0);
 414                 break;
 415         default:
 416                 printk(KERN_INFO "KVM: invalid SPR read: %d\n", sprn);
 417 #ifndef DEBUG_SPR
 418                 emulated = EMULATE_FAIL;
 419 #endif
 420                 break;
 421         }
 422
 423         return emulated;
 424 }
 425