2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37 #include <linux/ratelimit.h>
39 #include <asm/emulated_ops.h>
40 #include <asm/pgtable.h>
41 #include <asm/uaccess.h>
42 #include <asm/system.h>
44 #include <asm/machdep.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/backlight.h>
54 #include <asm/firmware.h>
55 #include <asm/processor.h>
57 #include <asm/kexec.h>
58 #include <asm/ppc-opcode.h>
60 #include <asm/fadump.h>
62 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
63 int (*__debugger)(struct pt_regs *regs) __read_mostly;
64 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
65 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
66 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
67 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
68 int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly;
69 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
71 EXPORT_SYMBOL(__debugger);
72 EXPORT_SYMBOL(__debugger_ipi);
73 EXPORT_SYMBOL(__debugger_bpt);
74 EXPORT_SYMBOL(__debugger_sstep);
75 EXPORT_SYMBOL(__debugger_iabr_match);
76 EXPORT_SYMBOL(__debugger_dabr_match);
77 EXPORT_SYMBOL(__debugger_fault_handler);
81 * Trap & Exception support
84 #ifdef CONFIG_PMAC_BACKLIGHT
85 static void pmac_backlight_unblank(void)
87 mutex_lock(&pmac_backlight_mutex);
89 struct backlight_properties *props;
91 props = &pmac_backlight->props;
92 props->brightness = props->max_brightness;
93 props->power = FB_BLANK_UNBLANK;
94 backlight_update_status(pmac_backlight);
96 mutex_unlock(&pmac_backlight_mutex);
99 static inline void pmac_backlight_unblank(void) { }
102 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
103 static int die_owner = -1;
104 static unsigned int die_nest_count;
105 static int die_counter;
107 static unsigned __kprobes long oops_begin(struct pt_regs *regs)
117 /* racy, but better than risking deadlock. */
118 raw_local_irq_save(flags);
119 cpu = smp_processor_id();
120 if (!arch_spin_trylock(&die_lock)) {
121 if (cpu == die_owner)
122 /* nested oops. should stop eventually */;
124 arch_spin_lock(&die_lock);
130 if (machine_is(powermac))
131 pmac_backlight_unblank();
135 static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
140 add_taint(TAINT_DIE);
145 /* Nest count reaches zero, release the lock. */
146 arch_spin_unlock(&die_lock);
147 raw_local_irq_restore(flags);
149 crash_fadump(regs, "die oops");
152 * A system reset (0x100) is a request to dump, so we always send
153 * it through the crashdump code.
155 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
159 * We aren't the primary crash CPU. We need to send it
160 * to a holding pattern to avoid it ending up in the panic
163 crash_kexec_secondary(regs);
170 * While our oops output is serialised by a spinlock, output
171 * from panic() called below can race and corrupt it. If we
172 * know we are going to panic, delay for 1 second so we have a
173 * chance to get clean backtraces from all CPUs that are oopsing.
175 if (in_interrupt() || panic_on_oops || !current->pid ||
176 is_global_init(current)) {
177 mdelay(MSEC_PER_SEC);
181 panic("Fatal exception in interrupt");
183 panic("Fatal exception");
187 static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
189 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
190 #ifdef CONFIG_PREEMPT
194 printk("SMP NR_CPUS=%d ", NR_CPUS);
196 #ifdef CONFIG_DEBUG_PAGEALLOC
197 printk("DEBUG_PAGEALLOC ");
202 printk("%s\n", ppc_md.name ? ppc_md.name : "");
204 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
213 void die(const char *str, struct pt_regs *regs, long err)
215 unsigned long flags = oops_begin(regs);
217 if (__die(str, regs, err))
219 oops_end(flags, regs, err);
222 void user_single_step_siginfo(struct task_struct *tsk,
223 struct pt_regs *regs, siginfo_t *info)
225 memset(info, 0, sizeof(*info));
226 info->si_signo = SIGTRAP;
227 info->si_code = TRAP_TRACE;
228 info->si_addr = (void __user *)regs->nip;
231 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
234 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
235 "at %08lx nip %08lx lr %08lx code %x\n";
236 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
237 "at %016lx nip %016lx lr %016lx code %x\n";
239 if (!user_mode(regs)) {
240 die("Exception in kernel mode", regs, signr);
244 if (show_unhandled_signals && unhandled_signal(current, signr)) {
245 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
246 current->comm, current->pid, signr,
247 addr, regs->nip, regs->link, code);
250 memset(&info, 0, sizeof(info));
251 info.si_signo = signr;
253 info.si_addr = (void __user *) addr;
254 force_sig_info(signr, &info, current);
258 void system_reset_exception(struct pt_regs *regs)
260 /* See if any machine dependent calls */
261 if (ppc_md.system_reset_exception) {
262 if (ppc_md.system_reset_exception(regs))
266 die("System Reset", regs, SIGABRT);
268 /* Must die if the interrupt is not recoverable */
269 if (!(regs->msr & MSR_RI))
270 panic("Unrecoverable System Reset");
272 /* What should we do here? We could issue a shutdown or hard reset. */
277 * I/O accesses can cause machine checks on powermacs.
278 * Check if the NIP corresponds to the address of a sync
279 * instruction for which there is an entry in the exception
281 * Note that the 601 only takes a machine check on TEA
282 * (transfer error ack) signal assertion, and does not
283 * set any of the top 16 bits of SRR1.
286 static inline int check_io_access(struct pt_regs *regs)
289 unsigned long msr = regs->msr;
290 const struct exception_table_entry *entry;
291 unsigned int *nip = (unsigned int *)regs->nip;
293 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
294 && (entry = search_exception_tables(regs->nip)) != NULL) {
296 * Check that it's a sync instruction, or somewhere
297 * in the twi; isync; nop sequence that inb/inw/inl uses.
298 * As the address is in the exception table
299 * we should be able to read the instr there.
300 * For the debug message, we look at the preceding
303 if (*nip == 0x60000000) /* nop */
305 else if (*nip == 0x4c00012c) /* isync */
307 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
312 rb = (*nip >> 11) & 0x1f;
313 printk(KERN_DEBUG "%s bad port %lx at %p\n",
314 (*nip & 0x100)? "OUT to": "IN from",
315 regs->gpr[rb] - _IO_BASE, nip);
317 regs->nip = entry->fixup;
321 #endif /* CONFIG_PPC32 */
325 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
326 /* On 4xx, the reason for the machine check or program exception
328 #define get_reason(regs) ((regs)->dsisr)
329 #ifndef CONFIG_FSL_BOOKE
330 #define get_mc_reason(regs) ((regs)->dsisr)
332 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
334 #define REASON_FP ESR_FP
335 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
336 #define REASON_PRIVILEGED ESR_PPR
337 #define REASON_TRAP ESR_PTR
339 /* single-step stuff */
340 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
341 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
344 /* On non-4xx, the reason for the machine check or program
345 exception is in the MSR. */
346 #define get_reason(regs) ((regs)->msr)
347 #define get_mc_reason(regs) ((regs)->msr)
348 #define REASON_FP 0x100000
349 #define REASON_ILLEGAL 0x80000
350 #define REASON_PRIVILEGED 0x40000
351 #define REASON_TRAP 0x20000
353 #define single_stepping(regs) ((regs)->msr & MSR_SE)
354 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
357 #if defined(CONFIG_4xx)
358 int machine_check_4xx(struct pt_regs *regs)
360 unsigned long reason = get_mc_reason(regs);
362 if (reason & ESR_IMCP) {
363 printk("Instruction");
364 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
367 printk(" machine check in kernel mode.\n");
372 int machine_check_440A(struct pt_regs *regs)
374 unsigned long reason = get_mc_reason(regs);
376 printk("Machine check in kernel mode.\n");
377 if (reason & ESR_IMCP){
378 printk("Instruction Synchronous Machine Check exception\n");
379 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
382 u32 mcsr = mfspr(SPRN_MCSR);
384 printk("Instruction Read PLB Error\n");
386 printk("Data Read PLB Error\n");
388 printk("Data Write PLB Error\n");
389 if (mcsr & MCSR_TLBP)
390 printk("TLB Parity Error\n");
391 if (mcsr & MCSR_ICP){
392 flush_instruction_cache();
393 printk("I-Cache Parity Error\n");
395 if (mcsr & MCSR_DCSP)
396 printk("D-Cache Search Parity Error\n");
397 if (mcsr & MCSR_DCFP)
398 printk("D-Cache Flush Parity Error\n");
399 if (mcsr & MCSR_IMPE)
400 printk("Machine Check exception is imprecise\n");
403 mtspr(SPRN_MCSR, mcsr);
408 int machine_check_47x(struct pt_regs *regs)
410 unsigned long reason = get_mc_reason(regs);
413 printk(KERN_ERR "Machine check in kernel mode.\n");
414 if (reason & ESR_IMCP) {
416 "Instruction Synchronous Machine Check exception\n");
417 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
420 mcsr = mfspr(SPRN_MCSR);
422 printk(KERN_ERR "Instruction Read PLB Error\n");
424 printk(KERN_ERR "Data Read PLB Error\n");
426 printk(KERN_ERR "Data Write PLB Error\n");
427 if (mcsr & MCSR_TLBP)
428 printk(KERN_ERR "TLB Parity Error\n");
429 if (mcsr & MCSR_ICP) {
430 flush_instruction_cache();
431 printk(KERN_ERR "I-Cache Parity Error\n");
433 if (mcsr & MCSR_DCSP)
434 printk(KERN_ERR "D-Cache Search Parity Error\n");
435 if (mcsr & PPC47x_MCSR_GPR)
436 printk(KERN_ERR "GPR Parity Error\n");
437 if (mcsr & PPC47x_MCSR_FPR)
438 printk(KERN_ERR "FPR Parity Error\n");
439 if (mcsr & PPC47x_MCSR_IPR)
440 printk(KERN_ERR "Machine Check exception is imprecise\n");
443 mtspr(SPRN_MCSR, mcsr);
447 #elif defined(CONFIG_E500)
448 int machine_check_e500mc(struct pt_regs *regs)
450 unsigned long mcsr = mfspr(SPRN_MCSR);
451 unsigned long reason = mcsr;
454 if (reason & MCSR_LD) {
455 recoverable = fsl_rio_mcheck_exception(regs);
456 if (recoverable == 1)
460 printk("Machine check in kernel mode.\n");
461 printk("Caused by (from MCSR=%lx): ", reason);
463 if (reason & MCSR_MCP)
464 printk("Machine Check Signal\n");
466 if (reason & MCSR_ICPERR) {
467 printk("Instruction Cache Parity Error\n");
470 * This is recoverable by invalidating the i-cache.
472 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
473 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
477 * This will generally be accompanied by an instruction
478 * fetch error report -- only treat MCSR_IF as fatal
479 * if it wasn't due to an L1 parity error.
484 if (reason & MCSR_DCPERR_MC) {
485 printk("Data Cache Parity Error\n");
488 * In write shadow mode we auto-recover from the error, but it
489 * may still get logged and cause a machine check. We should
490 * only treat the non-write shadow case as non-recoverable.
492 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
496 if (reason & MCSR_L2MMU_MHIT) {
497 printk("Hit on multiple TLB entries\n");
501 if (reason & MCSR_NMI)
502 printk("Non-maskable interrupt\n");
504 if (reason & MCSR_IF) {
505 printk("Instruction Fetch Error Report\n");
509 if (reason & MCSR_LD) {
510 printk("Load Error Report\n");
514 if (reason & MCSR_ST) {
515 printk("Store Error Report\n");
519 if (reason & MCSR_LDG) {
520 printk("Guarded Load Error Report\n");
524 if (reason & MCSR_TLBSYNC)
525 printk("Simultaneous tlbsync operations\n");
527 if (reason & MCSR_BSL2_ERR) {
528 printk("Level 2 Cache Error\n");
532 if (reason & MCSR_MAV) {
535 addr = mfspr(SPRN_MCAR);
536 addr |= (u64)mfspr(SPRN_MCARU) << 32;
538 printk("Machine Check %s Address: %#llx\n",
539 reason & MCSR_MEA ? "Effective" : "Physical", addr);
543 mtspr(SPRN_MCSR, mcsr);
544 return mfspr(SPRN_MCSR) == 0 && recoverable;
547 int machine_check_e500(struct pt_regs *regs)
549 unsigned long reason = get_mc_reason(regs);
551 if (reason & MCSR_BUS_RBERR) {
552 if (fsl_rio_mcheck_exception(regs))
556 printk("Machine check in kernel mode.\n");
557 printk("Caused by (from MCSR=%lx): ", reason);
559 if (reason & MCSR_MCP)
560 printk("Machine Check Signal\n");
561 if (reason & MCSR_ICPERR)
562 printk("Instruction Cache Parity Error\n");
563 if (reason & MCSR_DCP_PERR)
564 printk("Data Cache Push Parity Error\n");
565 if (reason & MCSR_DCPERR)
566 printk("Data Cache Parity Error\n");
567 if (reason & MCSR_BUS_IAERR)
568 printk("Bus - Instruction Address Error\n");
569 if (reason & MCSR_BUS_RAERR)
570 printk("Bus - Read Address Error\n");
571 if (reason & MCSR_BUS_WAERR)
572 printk("Bus - Write Address Error\n");
573 if (reason & MCSR_BUS_IBERR)
574 printk("Bus - Instruction Data Error\n");
575 if (reason & MCSR_BUS_RBERR)
576 printk("Bus - Read Data Bus Error\n");
577 if (reason & MCSR_BUS_WBERR)
578 printk("Bus - Read Data Bus Error\n");
579 if (reason & MCSR_BUS_IPERR)
580 printk("Bus - Instruction Parity Error\n");
581 if (reason & MCSR_BUS_RPERR)
582 printk("Bus - Read Parity Error\n");
587 int machine_check_generic(struct pt_regs *regs)
591 #elif defined(CONFIG_E200)
592 int machine_check_e200(struct pt_regs *regs)
594 unsigned long reason = get_mc_reason(regs);
596 printk("Machine check in kernel mode.\n");
597 printk("Caused by (from MCSR=%lx): ", reason);
599 if (reason & MCSR_MCP)
600 printk("Machine Check Signal\n");
601 if (reason & MCSR_CP_PERR)
602 printk("Cache Push Parity Error\n");
603 if (reason & MCSR_CPERR)
604 printk("Cache Parity Error\n");
605 if (reason & MCSR_EXCP_ERR)
606 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
607 if (reason & MCSR_BUS_IRERR)
608 printk("Bus - Read Bus Error on instruction fetch\n");
609 if (reason & MCSR_BUS_DRERR)
610 printk("Bus - Read Bus Error on data load\n");
611 if (reason & MCSR_BUS_WRERR)
612 printk("Bus - Write Bus Error on buffered store or cache line push\n");
617 int machine_check_generic(struct pt_regs *regs)
619 unsigned long reason = get_mc_reason(regs);
621 printk("Machine check in kernel mode.\n");
622 printk("Caused by (from SRR1=%lx): ", reason);
623 switch (reason & 0x601F0000) {
625 printk("Machine check signal\n");
627 case 0: /* for 601 */
629 case 0x140000: /* 7450 MSS error and TEA */
630 printk("Transfer error ack signal\n");
633 printk("Data parity error signal\n");
636 printk("Address parity error signal\n");
639 printk("L1 Data Cache error\n");
642 printk("L1 Instruction Cache error\n");
645 printk("L2 data cache parity error\n");
648 printk("Unknown values in msr\n");
652 #endif /* everything else */
654 void machine_check_exception(struct pt_regs *regs)
658 __get_cpu_var(irq_stat).mce_exceptions++;
660 /* See if any machine dependent calls. In theory, we would want
661 * to call the CPU first, and call the ppc_md. one if the CPU
662 * one returns a positive number. However there is existing code
663 * that assumes the board gets a first chance, so let's keep it
664 * that way for now and fix things later. --BenH.
666 if (ppc_md.machine_check_exception)
667 recover = ppc_md.machine_check_exception(regs);
668 else if (cur_cpu_spec->machine_check)
669 recover = cur_cpu_spec->machine_check(regs);
674 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
675 /* the qspan pci read routines can cause machine checks -- Cort
677 * yuck !!! that totally needs to go away ! There are better ways
678 * to deal with that than having a wart in the mcheck handler.
681 bad_page_fault(regs, regs->dar, SIGBUS);
685 if (debugger_fault_handler(regs))
688 if (check_io_access(regs))
691 die("Machine check", regs, SIGBUS);
693 /* Must die if the interrupt is not recoverable */
694 if (!(regs->msr & MSR_RI))
695 panic("Unrecoverable Machine check");
698 void SMIException(struct pt_regs *regs)
700 die("System Management Interrupt", regs, SIGABRT);
703 void unknown_exception(struct pt_regs *regs)
705 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
706 regs->nip, regs->msr, regs->trap);
708 _exception(SIGTRAP, regs, 0, 0);
711 void instruction_breakpoint_exception(struct pt_regs *regs)
713 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
714 5, SIGTRAP) == NOTIFY_STOP)
716 if (debugger_iabr_match(regs))
718 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
721 void RunModeException(struct pt_regs *regs)
723 _exception(SIGTRAP, regs, 0, 0);
726 void __kprobes single_step_exception(struct pt_regs *regs)
728 clear_single_step(regs);
730 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
731 5, SIGTRAP) == NOTIFY_STOP)
733 if (debugger_sstep(regs))
736 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
740 * After we have successfully emulated an instruction, we have to
741 * check if the instruction was being single-stepped, and if so,
742 * pretend we got a single-step exception. This was pointed out
743 * by Kumar Gala. -- paulus
745 static void emulate_single_step(struct pt_regs *regs)
747 if (single_stepping(regs))
748 single_step_exception(regs);
751 static inline int __parse_fpscr(unsigned long fpscr)
755 /* Invalid operation */
756 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
760 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
764 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
768 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
772 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
778 static void parse_fpe(struct pt_regs *regs)
782 flush_fp_to_thread(current);
784 code = __parse_fpscr(current->thread.fpscr.val);
786 _exception(SIGFPE, regs, code, regs->nip);
790 * Illegal instruction emulation support. Originally written to
791 * provide the PVR to user applications using the mfspr rd, PVR.
792 * Return non-zero if we can't emulate, or -EFAULT if the associated
793 * memory access caused an access fault. Return zero on success.
795 * There are a couple of ways to do this, either "decode" the instruction
796 * or directly match lots of bits. In this case, matching lots of
797 * bits is faster and easier.
800 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
802 u8 rT = (instword >> 21) & 0x1f;
803 u8 rA = (instword >> 16) & 0x1f;
804 u8 NB_RB = (instword >> 11) & 0x1f;
809 /* Early out if we are an invalid form of lswx */
810 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
811 if ((rT == rA) || (rT == NB_RB))
814 EA = (rA == 0) ? 0 : regs->gpr[rA];
816 switch (instword & PPC_INST_STRING_MASK) {
820 num_bytes = regs->xer & 0x7f;
824 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
830 while (num_bytes != 0)
833 u32 shift = 8 * (3 - (pos & 0x3));
835 switch ((instword & PPC_INST_STRING_MASK)) {
838 if (get_user(val, (u8 __user *)EA))
840 /* first time updating this reg,
844 regs->gpr[rT] |= val << shift;
848 val = regs->gpr[rT] >> shift;
849 if (put_user(val, (u8 __user *)EA))
853 /* move EA to next address */
857 /* manage our position within the register */
868 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
873 ra = (instword >> 16) & 0x1f;
874 rs = (instword >> 21) & 0x1f;
877 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
878 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
879 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
885 static int emulate_isel(struct pt_regs *regs, u32 instword)
887 u8 rT = (instword >> 21) & 0x1f;
888 u8 rA = (instword >> 16) & 0x1f;
889 u8 rB = (instword >> 11) & 0x1f;
890 u8 BC = (instword >> 6) & 0x1f;
894 tmp = (rA == 0) ? 0 : regs->gpr[rA];
895 bit = (regs->ccr >> (31 - BC)) & 0x1;
897 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
902 static int emulate_instruction(struct pt_regs *regs)
907 if (!user_mode(regs) || (regs->msr & MSR_LE))
909 CHECK_FULL_REGS(regs);
911 if (get_user(instword, (u32 __user *)(regs->nip)))
914 /* Emulate the mfspr rD, PVR. */
915 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
916 PPC_WARN_EMULATED(mfpvr, regs);
917 rd = (instword >> 21) & 0x1f;
918 regs->gpr[rd] = mfspr(SPRN_PVR);
922 /* Emulating the dcba insn is just a no-op. */
923 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
924 PPC_WARN_EMULATED(dcba, regs);
928 /* Emulate the mcrxr insn. */
929 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
930 int shift = (instword >> 21) & 0x1c;
931 unsigned long msk = 0xf0000000UL >> shift;
933 PPC_WARN_EMULATED(mcrxr, regs);
934 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
935 regs->xer &= ~0xf0000000UL;
939 /* Emulate load/store string insn. */
940 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
941 PPC_WARN_EMULATED(string, regs);
942 return emulate_string_inst(regs, instword);
945 /* Emulate the popcntb (Population Count Bytes) instruction. */
946 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
947 PPC_WARN_EMULATED(popcntb, regs);
948 return emulate_popcntb_inst(regs, instword);
951 /* Emulate isel (Integer Select) instruction */
952 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
953 PPC_WARN_EMULATED(isel, regs);
954 return emulate_isel(regs, instword);
958 /* Emulate the mfspr rD, DSCR. */
959 if (((instword & PPC_INST_MFSPR_DSCR_MASK) == PPC_INST_MFSPR_DSCR) &&
960 cpu_has_feature(CPU_FTR_DSCR)) {
961 PPC_WARN_EMULATED(mfdscr, regs);
962 rd = (instword >> 21) & 0x1f;
963 regs->gpr[rd] = mfspr(SPRN_DSCR);
966 /* Emulate the mtspr DSCR, rD. */
967 if (((instword & PPC_INST_MTSPR_DSCR_MASK) == PPC_INST_MTSPR_DSCR) &&
968 cpu_has_feature(CPU_FTR_DSCR)) {
969 PPC_WARN_EMULATED(mtdscr, regs);
970 rd = (instword >> 21) & 0x1f;
971 mtspr(SPRN_DSCR, regs->gpr[rd]);
972 current->thread.dscr_inherit = 1;
980 int is_valid_bugaddr(unsigned long addr)
982 return is_kernel_addr(addr);
985 void __kprobes program_check_exception(struct pt_regs *regs)
987 unsigned int reason = get_reason(regs);
988 extern int do_mathemu(struct pt_regs *regs);
990 /* We can now get here via a FP Unavailable exception if the core
991 * has no FPU, in that case the reason flags will be 0 */
993 if (reason & REASON_FP) {
994 /* IEEE FP exception */
998 if (reason & REASON_TRAP) {
999 /* Debugger is first in line to stop recursive faults in
1000 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1001 if (debugger_bpt(regs))
1004 /* trap exception */
1005 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1009 if (!(regs->msr & MSR_PR) && /* not user-mode */
1010 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1014 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1020 #ifdef CONFIG_MATH_EMULATION
1021 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1022 * but there seems to be a hardware bug on the 405GP (RevD)
1023 * that means ESR is sometimes set incorrectly - either to
1024 * ESR_DST (!?) or 0. In the process of chasing this with the
1025 * hardware people - not sure if it can happen on any illegal
1026 * instruction or only on FP instructions, whether there is a
1027 * pattern to occurrences etc. -dgibson 31/Mar/2003 */
1028 switch (do_mathemu(regs)) {
1030 emulate_single_step(regs);
1034 code = __parse_fpscr(current->thread.fpscr.val);
1035 _exception(SIGFPE, regs, code, regs->nip);
1039 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1042 /* fall through on any other errors */
1043 #endif /* CONFIG_MATH_EMULATION */
1045 /* Try to emulate it if we should. */
1046 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1047 switch (emulate_instruction(regs)) {
1050 emulate_single_step(regs);
1053 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1058 if (reason & REASON_PRIVILEGED)
1059 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1061 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1064 void alignment_exception(struct pt_regs *regs)
1066 int sig, code, fixed = 0;
1068 /* we don't implement logging of alignment exceptions */
1069 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1070 fixed = fix_alignment(regs);
1073 regs->nip += 4; /* skip over emulated instruction */
1074 emulate_single_step(regs);
1078 /* Operand address was bad */
1079 if (fixed == -EFAULT) {
1086 if (user_mode(regs))
1087 _exception(sig, regs, code, regs->dar);
1089 bad_page_fault(regs, regs->dar, sig);
1092 void StackOverflow(struct pt_regs *regs)
1094 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1095 current, regs->gpr[1]);
1098 panic("kernel stack overflow");
1101 void nonrecoverable_exception(struct pt_regs *regs)
1103 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1104 regs->nip, regs->msr);
1106 die("nonrecoverable exception", regs, SIGKILL);
1109 void trace_syscall(struct pt_regs *regs)
1111 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
1112 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
1113 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
1116 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1118 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1119 "%lx at %lx\n", regs->trap, regs->nip);
1120 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1123 void altivec_unavailable_exception(struct pt_regs *regs)
1125 if (user_mode(regs)) {
1126 /* A user program has executed an altivec instruction,
1127 but this kernel doesn't support altivec. */
1128 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1132 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1133 "%lx at %lx\n", regs->trap, regs->nip);
1134 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1137 void vsx_unavailable_exception(struct pt_regs *regs)
1139 if (user_mode(regs)) {
1140 /* A user program has executed an vsx instruction,
1141 but this kernel doesn't support vsx. */
1142 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1146 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1147 "%lx at %lx\n", regs->trap, regs->nip);
1148 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1151 void performance_monitor_exception(struct pt_regs *regs)
1153 __get_cpu_var(irq_stat).pmu_irqs++;
1159 void SoftwareEmulation(struct pt_regs *regs)
1161 extern int do_mathemu(struct pt_regs *);
1162 extern int Soft_emulate_8xx(struct pt_regs *);
1163 #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
1167 CHECK_FULL_REGS(regs);
1169 if (!user_mode(regs)) {
1171 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
1174 #ifdef CONFIG_MATH_EMULATION
1175 errcode = do_mathemu(regs);
1177 PPC_WARN_EMULATED(math, regs);
1181 emulate_single_step(regs);
1185 code = __parse_fpscr(current->thread.fpscr.val);
1186 _exception(SIGFPE, regs, code, regs->nip);
1190 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1193 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1197 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1198 errcode = Soft_emulate_8xx(regs);
1200 PPC_WARN_EMULATED(8xx, regs);
1204 emulate_single_step(regs);
1207 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1210 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1214 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1217 #endif /* CONFIG_8xx */
1219 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1220 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1224 * Determine the cause of the debug event, clear the
1225 * event flags and send a trap to the handler. Torez
1227 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1228 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1229 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1230 current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1232 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1235 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1236 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1237 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1240 } else if (debug_status & DBSR_IAC1) {
1241 current->thread.dbcr0 &= ~DBCR0_IAC1;
1242 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1243 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1246 } else if (debug_status & DBSR_IAC2) {
1247 current->thread.dbcr0 &= ~DBCR0_IAC2;
1248 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1251 } else if (debug_status & DBSR_IAC3) {
1252 current->thread.dbcr0 &= ~DBCR0_IAC3;
1253 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1254 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1257 } else if (debug_status & DBSR_IAC4) {
1258 current->thread.dbcr0 &= ~DBCR0_IAC4;
1259 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1264 * At the point this routine was called, the MSR(DE) was turned off.
1265 * Check all other debug flags and see if that bit needs to be turned
1268 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
1269 regs->msr |= MSR_DE;
1271 /* Make sure the IDM flag is off */
1272 current->thread.dbcr0 &= ~DBCR0_IDM;
1275 mtspr(SPRN_DBCR0, current->thread.dbcr0);
1278 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1280 current->thread.dbsr = debug_status;
1282 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1283 * on server, it stops on the target of the branch. In order to simulate
1284 * the server behaviour, we thus restart right away with a single step
1285 * instead of stopping here when hitting a BT
1287 if (debug_status & DBSR_BT) {
1288 regs->msr &= ~MSR_DE;
1291 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1292 /* Clear the BT event */
1293 mtspr(SPRN_DBSR, DBSR_BT);
1295 /* Do the single step trick only when coming from userspace */
1296 if (user_mode(regs)) {
1297 current->thread.dbcr0 &= ~DBCR0_BT;
1298 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1299 regs->msr |= MSR_DE;
1303 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1304 5, SIGTRAP) == NOTIFY_STOP) {
1307 if (debugger_sstep(regs))
1309 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1310 regs->msr &= ~MSR_DE;
1312 /* Disable instruction completion */
1313 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1314 /* Clear the instruction completion event */
1315 mtspr(SPRN_DBSR, DBSR_IC);
1317 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1318 5, SIGTRAP) == NOTIFY_STOP) {
1322 if (debugger_sstep(regs))
1325 if (user_mode(regs)) {
1326 current->thread.dbcr0 &= ~DBCR0_IC;
1327 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
1328 current->thread.dbcr1))
1329 regs->msr |= MSR_DE;
1331 /* Make sure the IDM bit is off */
1332 current->thread.dbcr0 &= ~DBCR0_IDM;
1335 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1337 handle_debug(regs, debug_status);
1339 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1341 #if !defined(CONFIG_TAU_INT)
1342 void TAUException(struct pt_regs *regs)
1344 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1345 regs->nip, regs->msr, regs->trap, print_tainted());
1347 #endif /* CONFIG_INT_TAU */
1349 #ifdef CONFIG_ALTIVEC
1350 void altivec_assist_exception(struct pt_regs *regs)
1354 if (!user_mode(regs)) {
1355 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1356 " at %lx\n", regs->nip);
1357 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1360 flush_altivec_to_thread(current);
1362 PPC_WARN_EMULATED(altivec, regs);
1363 err = emulate_altivec(regs);
1365 regs->nip += 4; /* skip emulated instruction */
1366 emulate_single_step(regs);
1370 if (err == -EFAULT) {
1371 /* got an error reading the instruction */
1372 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1374 /* didn't recognize the instruction */
1375 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1376 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1377 "in %s at %lx\n", current->comm, regs->nip);
1378 current->thread.vscr.u[3] |= 0x10000;
1381 #endif /* CONFIG_ALTIVEC */
1384 void vsx_assist_exception(struct pt_regs *regs)
1386 if (!user_mode(regs)) {
1387 printk(KERN_EMERG "VSX assist exception in kernel mode"
1388 " at %lx\n", regs->nip);
1389 die("Kernel VSX assist exception", regs, SIGILL);
1392 flush_vsx_to_thread(current);
1393 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
1394 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1396 #endif /* CONFIG_VSX */
1398 #ifdef CONFIG_FSL_BOOKE
1399 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1400 unsigned long error_code)
1402 /* We treat cache locking instructions from the user
1403 * as priv ops, in the future we could try to do
1406 if (error_code & (ESR_DLK|ESR_ILK))
1407 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1410 #endif /* CONFIG_FSL_BOOKE */
1413 void SPEFloatingPointException(struct pt_regs *regs)
1415 extern int do_spe_mathemu(struct pt_regs *regs);
1416 unsigned long spefscr;
1421 flush_spe_to_thread(current);
1423 spefscr = current->thread.spefscr;
1424 fpexc_mode = current->thread.fpexc_mode;
1426 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1429 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1432 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1434 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1437 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1440 err = do_spe_mathemu(regs);
1442 regs->nip += 4; /* skip emulated instruction */
1443 emulate_single_step(regs);
1447 if (err == -EFAULT) {
1448 /* got an error reading the instruction */
1449 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1450 } else if (err == -EINVAL) {
1451 /* didn't recognize the instruction */
1452 printk(KERN_ERR "unrecognized spe instruction "
1453 "in %s at %lx\n", current->comm, regs->nip);
1455 _exception(SIGFPE, regs, code, regs->nip);
1461 void SPEFloatingPointRoundException(struct pt_regs *regs)
1463 extern int speround_handler(struct pt_regs *regs);
1467 if (regs->msr & MSR_SPE)
1468 giveup_spe(current);
1472 err = speround_handler(regs);
1474 regs->nip += 4; /* skip emulated instruction */
1475 emulate_single_step(regs);
1479 if (err == -EFAULT) {
1480 /* got an error reading the instruction */
1481 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1482 } else if (err == -EINVAL) {
1483 /* didn't recognize the instruction */
1484 printk(KERN_ERR "unrecognized spe instruction "
1485 "in %s at %lx\n", current->comm, regs->nip);
1487 _exception(SIGFPE, regs, 0, regs->nip);
1494 * We enter here if we get an unrecoverable exception, that is, one
1495 * that happened at a point where the RI (recoverable interrupt) bit
1496 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1497 * we therefore lost state by taking this exception.
1499 void unrecoverable_exception(struct pt_regs *regs)
1501 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1502 regs->trap, regs->nip);
1503 die("Unrecoverable exception", regs, SIGABRT);
1506 #ifdef CONFIG_BOOKE_WDT
1508 * Default handler for a Watchdog exception,
1509 * spins until a reboot occurs
1511 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1513 /* Generic WatchdogHandler, implement your own */
1514 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1518 void WatchdogException(struct pt_regs *regs)
1520 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1521 WatchdogHandler(regs);
1526 * We enter here if we discover during exception entry that we are
1527 * running in supervisor mode with a userspace value in the stack pointer.
1529 void kernel_bad_stack(struct pt_regs *regs)
1531 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1532 regs->gpr[1], regs->nip);
1533 die("Bad kernel stack pointer", regs, SIGABRT);
1536 void __init trap_init(void)
1541 #ifdef CONFIG_PPC_EMULATED_STATS
1543 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1545 struct ppc_emulated ppc_emulated = {
1546 #ifdef CONFIG_ALTIVEC
1547 WARN_EMULATED_SETUP(altivec),
1549 WARN_EMULATED_SETUP(dcba),
1550 WARN_EMULATED_SETUP(dcbz),
1551 WARN_EMULATED_SETUP(fp_pair),
1552 WARN_EMULATED_SETUP(isel),
1553 WARN_EMULATED_SETUP(mcrxr),
1554 WARN_EMULATED_SETUP(mfpvr),
1555 WARN_EMULATED_SETUP(multiple),
1556 WARN_EMULATED_SETUP(popcntb),
1557 WARN_EMULATED_SETUP(spe),
1558 WARN_EMULATED_SETUP(string),
1559 WARN_EMULATED_SETUP(unaligned),
1560 #ifdef CONFIG_MATH_EMULATION
1561 WARN_EMULATED_SETUP(math),
1562 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1563 WARN_EMULATED_SETUP(8xx),
1566 WARN_EMULATED_SETUP(vsx),
1569 WARN_EMULATED_SETUP(mfdscr),
1570 WARN_EMULATED_SETUP(mtdscr),
1574 u32 ppc_warn_emulated;
1576 void ppc_warn_emulated_print(const char *type)
1578 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1582 static int __init ppc_warn_emulated_init(void)
1584 struct dentry *dir, *d;
1586 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1588 if (!powerpc_debugfs_root)
1591 dir = debugfs_create_dir("emulated_instructions",
1592 powerpc_debugfs_root);
1596 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1597 &ppc_warn_emulated);
1601 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1602 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1603 (u32 *)&entries[i].val.counter);
1611 debugfs_remove_recursive(dir);
1615 device_initcall(ppc_warn_emulated_init);
1617 #endif /* CONFIG_PPC_EMULATED_STATS */