Pileus Git - ~andy/linux/blob - arch/powerpc/kernel/fpu.S

   1 /*
   2  *  FPU support code, moved here from head.S so that it can be used
   3  *  by chips which use other head-whatever.S files.
   4  *
   5  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   6  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *    Copyright (C) 1996 Paul Mackerras.
   8  *    Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
   9  *
  10  *  This program is free software; you can redistribute it and/or
  11  *  modify it under the terms of the GNU General Public License
  12  *  as published by the Free Software Foundation; either version
  13  *  2 of the License, or (at your option) any later version.
  14  *
  15  */
  16
  17 #include <asm/reg.h>
  18 #include <asm/page.h>
  19 #include <asm/mmu.h>
  20 #include <asm/pgtable.h>
  21 #include <asm/cputable.h>
  22 #include <asm/cache.h>
  23 #include <asm/thread_info.h>
  24 #include <asm/ppc_asm.h>
  25 #include <asm/asm-offsets.h>
  26 #include <asm/ptrace.h>
  27
  28 #ifdef CONFIG_VSX
  29 #define __REST_32FPVSRS(n,c,base)                                       \
  30 BEGIN_FTR_SECTION                                                       \
  31         b       2f;                                                     \
  32 END_FTR_SECTION_IFSET(CPU_FTR_VSX);                                     \
  33         REST_32FPRS(n,base);                                            \
  34         b       3f;                                                     \
  35 2:      REST_32VSRS(n,c,base);                                          \
  36 3:
  37
  38 #define __SAVE_32FPVSRS(n,c,base)                                       \
  39 BEGIN_FTR_SECTION                                                       \
  40         b       2f;                                                     \
  41 END_FTR_SECTION_IFSET(CPU_FTR_VSX);                                     \
  42         SAVE_32FPRS(n,base);                                            \
  43         b       3f;                                                     \
  44 2:      SAVE_32VSRS(n,c,base);                                          \
  45 3:
  46 #else
  47 #define __REST_32FPVSRS(n,b,base)       REST_32FPRS(n, base)
  48 #define __SAVE_32FPVSRS(n,b,base)       SAVE_32FPRS(n, base)
  49 #endif
  50 #define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
  51 #define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
  52
  53 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  54 /* void do_load_up_transact_fpu(struct thread_struct *thread)
  55  *
  56  * This is similar to load_up_fpu but for the transactional version of the FP
  57  * register set.  It doesn't mess with the task MSR or valid flags.
  58  * Furthermore, we don't do lazy FP with TM currently.
  59  */
  60 _GLOBAL(do_load_up_transact_fpu)
  61         mfmsr   r6
  62         ori     r5,r6,MSR_FP
  63 #ifdef CONFIG_VSX
  64 BEGIN_FTR_SECTION
  65         oris    r5,r5,MSR_VSX@h
  66 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
  67 #endif
  68         SYNC
  69         MTMSRD(r5)
  70
  71         addi    r7,r3,THREAD_TRANSACT_FPSTATE
  72         lfd     fr0,FPSTATE_FPSCR(r7)
  73         MTFSF_L(fr0)
  74         REST_32FPVSRS(0, R4, R7)
  75
  76         /* FP/VSX off again */
  77         MTMSRD(r6)
  78         SYNC
  79
  80         blr
  81 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  82
  83 /*
  84  * Load state from memory into FP registers including FPSCR.
  85  * Assumes the caller has enabled FP in the MSR.
  86  */
  87 _GLOBAL(load_fp_state)
  88         lfd     fr0,FPSTATE_FPSCR(r3)
  89         MTFSF_L(fr0)
  90         REST_32FPVSRS(0, R4, R3)
  91         blr
  92
  93 /*
  94  * Store FP state into memory, including FPSCR
  95  * Assumes the caller has enabled FP in the MSR.
  96  */
  97 _GLOBAL(store_fp_state)
  98         SAVE_32FPVSRS(0, R4, R3)
  99         mffs    fr0
 100         stfd    fr0,FPSTATE_FPSCR(r3)
 101         blr
 102
 103 /*
 104  * This task wants to use the FPU now.
 105  * On UP, disable FP for the task which had the FPU previously,
 106  * and save its floating-point registers in its thread_struct.
 107  * Load up this task's FP registers from its thread_struct,
 108  * enable the FPU for the current task and return to the task.
 109  */
 110 _GLOBAL(load_up_fpu)
 111         mfmsr   r5
 112         ori     r5,r5,MSR_FP
 113 #ifdef CONFIG_VSX
 114 BEGIN_FTR_SECTION
 115         oris    r5,r5,MSR_VSX@h
 116 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 117 #endif
 118         SYNC
 119         MTMSRD(r5)                      /* enable use of fpu now */
 120         isync
 121 /*
 122  * For SMP, we don't do lazy FPU switching because it just gets too
 123  * horrendously complex, especially when a task switches from one CPU
 124  * to another.  Instead we call giveup_fpu in switch_to.
 125  */
 126 #ifndef CONFIG_SMP
 127         LOAD_REG_ADDRBASE(r3, last_task_used_math)
 128         toreal(r3)
 129         PPC_LL  r4,ADDROFF(last_task_used_math)(r3)
 130         PPC_LCMPI       0,r4,0
 131         beq     1f
 132         toreal(r4)
 133         addi    r4,r4,THREAD            /* want last_task_used_math->thread */
 134         addi    r8,r4,THREAD_FPSTATE
 135         SAVE_32FPVSRS(0, R5, R8)
 136         mffs    fr0
 137         stfd    fr0,FPSTATE_FPSCR(r8)
 138         PPC_LL  r5,PT_REGS(r4)
 139         toreal(r5)
 140         PPC_LL  r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 141         li      r10,MSR_FP|MSR_FE0|MSR_FE1
 142         andc    r4,r4,r10               /* disable FP for previous task */
 143         PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 144 1:
 145 #endif /* CONFIG_SMP */
 146         /* enable use of FP after return */
 147 #ifdef CONFIG_PPC32
 148         mfspr   r5,SPRN_SPRG_THREAD     /* current task's THREAD (phys) */
 149         lwz     r4,THREAD_FPEXC_MODE(r5)
 150         ori     r9,r9,MSR_FP            /* enable FP for current */
 151         or      r9,r9,r4
 152 #else
 153         ld      r4,PACACURRENT(r13)
 154         addi    r5,r4,THREAD            /* Get THREAD */
 155         lwz     r4,THREAD_FPEXC_MODE(r5)
 156         ori     r12,r12,MSR_FP
 157         or      r12,r12,r4
 158         std     r12,_MSR(r1)
 159 #endif
 160         addi    r7,r5,THREAD_FPSTATE
 161         lfd     fr0,FPSTATE_FPSCR(r7)
 162         MTFSF_L(fr0)
 163         REST_32FPVSRS(0, R4, R7)
 164 #ifndef CONFIG_SMP
 165         subi    r4,r5,THREAD
 166         fromreal(r4)
 167         PPC_STL r4,ADDROFF(last_task_used_math)(r3)
 168 #endif /* CONFIG_SMP */
 169         /* restore registers and return */
 170         /* we haven't used ctr or xer or lr */
 171         blr
 172
 173 /*
 174  * giveup_fpu(tsk)
 175  * Disable FP for the task given as the argument,
 176  * and save the floating-point registers in its thread_struct.
 177  * Enables the FPU for use in the kernel on return.
 178  */
 179 _GLOBAL(giveup_fpu)
 180         mfmsr   r5
 181         ori     r5,r5,MSR_FP
 182 #ifdef CONFIG_VSX
 183 BEGIN_FTR_SECTION
 184         oris    r5,r5,MSR_VSX@h
 185 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 186 #endif
 187         SYNC_601
 188         ISYNC_601
 189         MTMSRD(r5)                      /* enable use of fpu now */
 190         SYNC_601
 191         isync
 192         PPC_LCMPI       0,r3,0
 193         beqlr-                          /* if no previous owner, done */
 194         addi    r3,r3,THREAD            /* want THREAD of task */
 195         PPC_LL  r6,THREAD_FPSAVEAREA(r3)
 196         PPC_LL  r5,PT_REGS(r3)
 197         PPC_LCMPI       0,r6,0
 198         bne     2f
 199         addi    r6,r3,THREAD_FPSTATE
 200 2:      PPC_LCMPI       0,r5,0
 201         SAVE_32FPVSRS(0, R4, R6)
 202         mffs    fr0
 203         stfd    fr0,FPSTATE_FPSCR(r6)
 204         beq     1f
 205         PPC_LL  r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 206         li      r3,MSR_FP|MSR_FE0|MSR_FE1
 207 #ifdef CONFIG_VSX
 208 BEGIN_FTR_SECTION
 209         oris    r3,r3,MSR_VSX@h
 210 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 211 #endif
 212         andc    r4,r4,r3                /* disable FP for previous task */
 213         PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 214 1:
 215 #ifndef CONFIG_SMP
 216         li      r5,0
 217         LOAD_REG_ADDRBASE(r4,last_task_used_math)
 218         PPC_STL r5,ADDROFF(last_task_used_math)(r4)
 219 #endif /* CONFIG_SMP */
 220         blr
 221
 222 /*
 223  * These are used in the alignment trap handler when emulating
 224  * single-precision loads and stores.
 225  */
 226
 227 _GLOBAL(cvt_fd)
 228         lfs     0,0(r3)
 229         stfd    0,0(r4)
 230         blr
 231
 232 _GLOBAL(cvt_df)
 233         lfd     0,0(r3)
 234         stfs    0,0(r4)
 235         blr