Pileus Git - ~andy/linux/blob - arch/powerpc/kernel/fpu.S

   1 /*
   2  *  FPU support code, moved here from head.S so that it can be used
   3  *  by chips which use other head-whatever.S files.
   4  *
   5  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   6  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *    Copyright (C) 1996 Paul Mackerras.
   8  *    Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
   9  *
  10  *  This program is free software; you can redistribute it and/or
  11  *  modify it under the terms of the GNU General Public License
  12  *  as published by the Free Software Foundation; either version
  13  *  2 of the License, or (at your option) any later version.
  14  *
  15  */
  16
  17 #include <asm/reg.h>
  18 #include <asm/page.h>
  19 #include <asm/mmu.h>
  20 #include <asm/pgtable.h>
  21 #include <asm/cputable.h>
  22 #include <asm/cache.h>
  23 #include <asm/thread_info.h>
  24 #include <asm/ppc_asm.h>
  25 #include <asm/asm-offsets.h>
  26 #include <asm/ptrace.h>
  27
  28 #ifdef CONFIG_VSX
  29 #define __REST_32FPVSRS(n,c,base)                                       \
  30 BEGIN_FTR_SECTION                                                       \
  31         b       2f;                                                     \
  32 END_FTR_SECTION_IFSET(CPU_FTR_VSX);                                     \
  33         REST_32FPRS(n,base);                                            \
  34         b       3f;                                                     \
  35 2:      REST_32VSRS(n,c,base);                                          \
  36 3:
  37
  38 #define __SAVE_32FPVSRS(n,c,base)                                       \
  39 BEGIN_FTR_SECTION                                                       \
  40         b       2f;                                                     \
  41 END_FTR_SECTION_IFSET(CPU_FTR_VSX);                                     \
  42         SAVE_32FPRS(n,base);                                            \
  43         b       3f;                                                     \
  44 2:      SAVE_32VSRS(n,c,base);                                          \
  45 3:
  46 #else
  47 #define __REST_32FPVSRS(n,b,base)       REST_32FPRS(n, base)
  48 #define __SAVE_32FPVSRS(n,b,base)       SAVE_32FPRS(n, base)
  49 #endif
  50 #define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
  51 #define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
  52
  53 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  54 /* void do_load_up_transact_fpu(struct thread_struct *thread)
  55  *
  56  * This is similar to load_up_fpu but for the transactional version of the FP
  57  * register set.  It doesn't mess with the task MSR or valid flags.
  58  * Furthermore, we don't do lazy FP with TM currently.
  59  */
  60 _GLOBAL(do_load_up_transact_fpu)
  61         mfmsr   r6
  62         ori     r5,r6,MSR_FP
  63 #ifdef CONFIG_VSX
  64 BEGIN_FTR_SECTION
  65         oris    r5,r5,MSR_VSX@h
  66 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
  67 #endif
  68         SYNC
  69         MTMSRD(r5)
  70
  71         addi    r7,r3,THREAD_TRANSACT_FPSTATE
  72         lfd     fr0,FPSTATE_FPSCR(r7)
  73         MTFSF_L(fr0)
  74         REST_32FPVSRS(0, R4, R7)
  75
  76         /* FP/VSX off again */
  77         MTMSRD(r6)
  78         SYNC
  79
  80         blr
  81 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  82
  83 /*
  84  * This task wants to use the FPU now.
  85  * On UP, disable FP for the task which had the FPU previously,
  86  * and save its floating-point registers in its thread_struct.
  87  * Load up this task's FP registers from its thread_struct,
  88  * enable the FPU for the current task and return to the task.
  89  */
  90 _GLOBAL(load_up_fpu)
  91         mfmsr   r5
  92         ori     r5,r5,MSR_FP
  93 #ifdef CONFIG_VSX
  94 BEGIN_FTR_SECTION
  95         oris    r5,r5,MSR_VSX@h
  96 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
  97 #endif
  98         SYNC
  99         MTMSRD(r5)                      /* enable use of fpu now */
 100         isync
 101 /*
 102  * For SMP, we don't do lazy FPU switching because it just gets too
 103  * horrendously complex, especially when a task switches from one CPU
 104  * to another.  Instead we call giveup_fpu in switch_to.
 105  */
 106 #ifndef CONFIG_SMP
 107         LOAD_REG_ADDRBASE(r3, last_task_used_math)
 108         toreal(r3)
 109         PPC_LL  r4,ADDROFF(last_task_used_math)(r3)
 110         PPC_LCMPI       0,r4,0
 111         beq     1f
 112         toreal(r4)
 113         addi    r4,r4,THREAD            /* want last_task_used_math->thread */
 114         addi    r8,r4,THREAD_FPSTATE
 115         SAVE_32FPVSRS(0, R5, R8)
 116         mffs    fr0
 117         stfd    fr0,FPSTATE_FPSCR(r8)
 118         PPC_LL  r5,PT_REGS(r4)
 119         toreal(r5)
 120         PPC_LL  r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 121         li      r10,MSR_FP|MSR_FE0|MSR_FE1
 122         andc    r4,r4,r10               /* disable FP for previous task */
 123         PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 124 1:
 125 #endif /* CONFIG_SMP */
 126         /* enable use of FP after return */
 127 #ifdef CONFIG_PPC32
 128         mfspr   r5,SPRN_SPRG_THREAD     /* current task's THREAD (phys) */
 129         lwz     r4,THREAD_FPEXC_MODE(r5)
 130         ori     r9,r9,MSR_FP            /* enable FP for current */
 131         or      r9,r9,r4
 132 #else
 133         ld      r4,PACACURRENT(r13)
 134         addi    r5,r4,THREAD            /* Get THREAD */
 135         lwz     r4,THREAD_FPEXC_MODE(r5)
 136         ori     r12,r12,MSR_FP
 137         or      r12,r12,r4
 138         std     r12,_MSR(r1)
 139 #endif
 140         addi    r7,r5,THREAD_FPSTATE
 141         lfd     fr0,FPSTATE_FPSCR(r7)
 142         MTFSF_L(fr0)
 143         REST_32FPVSRS(0, R4, R7)
 144 #ifndef CONFIG_SMP
 145         subi    r4,r5,THREAD
 146         fromreal(r4)
 147         PPC_STL r4,ADDROFF(last_task_used_math)(r3)
 148 #endif /* CONFIG_SMP */
 149         /* restore registers and return */
 150         /* we haven't used ctr or xer or lr */
 151         blr
 152
 153 /*
 154  * giveup_fpu(tsk)
 155  * Disable FP for the task given as the argument,
 156  * and save the floating-point registers in its thread_struct.
 157  * Enables the FPU for use in the kernel on return.
 158  */
 159 _GLOBAL(giveup_fpu)
 160         mfmsr   r5
 161         ori     r5,r5,MSR_FP
 162 #ifdef CONFIG_VSX
 163 BEGIN_FTR_SECTION
 164         oris    r5,r5,MSR_VSX@h
 165 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 166 #endif
 167         SYNC_601
 168         ISYNC_601
 169         MTMSRD(r5)                      /* enable use of fpu now */
 170         SYNC_601
 171         isync
 172         PPC_LCMPI       0,r3,0
 173         beqlr-                          /* if no previous owner, done */
 174         addi    r3,r3,THREAD            /* want THREAD of task */
 175         PPC_LL  r5,PT_REGS(r3)
 176         PPC_LCMPI       0,r5,0
 177         addi    r6,r3,THREAD_FPSTATE
 178         SAVE_32FPVSRS(0, R4, R6)
 179         mffs    fr0
 180         stfd    fr0,FPSTATE_FPSCR(r6)
 181         beq     1f
 182         PPC_LL  r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 183         li      r3,MSR_FP|MSR_FE0|MSR_FE1
 184 #ifdef CONFIG_VSX
 185 BEGIN_FTR_SECTION
 186         oris    r3,r3,MSR_VSX@h
 187 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 188 #endif
 189         andc    r4,r4,r3                /* disable FP for previous task */
 190         PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 191 1:
 192 #ifndef CONFIG_SMP
 193         li      r5,0
 194         LOAD_REG_ADDRBASE(r4,last_task_used_math)
 195         PPC_STL r5,ADDROFF(last_task_used_math)(r4)
 196 #endif /* CONFIG_SMP */
 197         blr
 198
 199 /*
 200  * These are used in the alignment trap handler when emulating
 201  * single-precision loads and stores.
 202  */
 203
 204 _GLOBAL(cvt_fd)
 205         lfs     0,0(r3)
 206         stfd    0,0(r4)
 207         blr
 208
 209 _GLOBAL(cvt_df)
 210         lfd     0,0(r3)
 211         stfs    0,0(r4)
 212         blr