2 * Boot code and exception vectors for Book3E processors
4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/threads.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cputable.h>
18 #include <asm/setup.h>
19 #include <asm/thread_info.h>
20 #include <asm/reg_a2.h>
21 #include <asm/exception-64e.h>
23 #include <asm/irqflags.h>
24 #include <asm/ptrace.h>
25 #include <asm/ppc-opcode.h>
28 /* XXX This will ultimately add space for a special exception save
29 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
30 * when taking special interrupts. For now we don't support that,
31 * special interrupts from within a non-standard level will probably
34 #define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE
36 /* Exception prolog code for all exceptions */
37 #define EXCEPTION_PROLOG(n, type, addition) \
38 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
39 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
40 std r10,PACA_EX##type+EX_R10(r13); \
41 std r11,PACA_EX##type+EX_R11(r13); \
42 mfcr r10; /* save CR */ \
43 addition; /* additional code for that exc. */ \
44 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
45 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
46 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
47 type##_SET_KSTACK; /* get special stack if necessary */\
48 andi. r10,r11,MSR_PR; /* save stack pointer */ \
49 beq 1f; /* branch around if supervisor */ \
50 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
51 1: cmpdi cr1,r1,0; /* check if SP makes sense */ \
52 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
53 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
55 /* Exception type-specific macros */
56 #define GEN_SET_KSTACK \
57 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
58 #define SPRN_GEN_SRR0 SPRN_SRR0
59 #define SPRN_GEN_SRR1 SPRN_SRR1
61 #define CRIT_SET_KSTACK \
62 ld r1,PACA_CRIT_STACK(r13); \
63 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
64 #define SPRN_CRIT_SRR0 SPRN_CSRR0
65 #define SPRN_CRIT_SRR1 SPRN_CSRR1
67 #define DBG_SET_KSTACK \
68 ld r1,PACA_DBG_STACK(r13); \
69 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
70 #define SPRN_DBG_SRR0 SPRN_DSRR0
71 #define SPRN_DBG_SRR1 SPRN_DSRR1
73 #define MC_SET_KSTACK \
74 ld r1,PACA_MC_STACK(r13); \
75 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
76 #define SPRN_MC_SRR0 SPRN_MCSRR0
77 #define SPRN_MC_SRR1 SPRN_MCSRR1
79 #define NORMAL_EXCEPTION_PROLOG(n, addition) \
80 EXCEPTION_PROLOG(n, GEN, addition##_GEN)
82 #define CRIT_EXCEPTION_PROLOG(n, addition) \
83 EXCEPTION_PROLOG(n, CRIT, addition##_CRIT)
85 #define DBG_EXCEPTION_PROLOG(n, addition) \
86 EXCEPTION_PROLOG(n, DBG, addition##_DBG)
88 #define MC_EXCEPTION_PROLOG(n, addition) \
89 EXCEPTION_PROLOG(n, MC, addition##_MC)
92 /* Variants of the "addition" argument for the prolog
94 #define PROLOG_ADDITION_NONE_GEN
95 #define PROLOG_ADDITION_NONE_CRIT
96 #define PROLOG_ADDITION_NONE_DBG
97 #define PROLOG_ADDITION_NONE_MC
99 #define PROLOG_ADDITION_MASKABLE_GEN \
100 lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
101 cmpwi cr0,r11,0; /* yes -> go out of line */ \
102 beq masked_interrupt_book3e;
104 #define PROLOG_ADDITION_2REGS_GEN \
105 std r14,PACA_EXGEN+EX_R14(r13); \
106 std r15,PACA_EXGEN+EX_R15(r13)
108 #define PROLOG_ADDITION_1REG_GEN \
109 std r14,PACA_EXGEN+EX_R14(r13);
111 #define PROLOG_ADDITION_2REGS_CRIT \
112 std r14,PACA_EXCRIT+EX_R14(r13); \
113 std r15,PACA_EXCRIT+EX_R15(r13)
115 #define PROLOG_ADDITION_2REGS_DBG \
116 std r14,PACA_EXDBG+EX_R14(r13); \
117 std r15,PACA_EXDBG+EX_R15(r13)
119 #define PROLOG_ADDITION_2REGS_MC \
120 std r14,PACA_EXMC+EX_R14(r13); \
121 std r15,PACA_EXMC+EX_R15(r13)
123 #define PROLOG_ADDITION_DOORBELL_GEN \
124 lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
125 cmpwi cr0,r11,0; /* yes -> go out of line */ \
126 beq masked_doorbell_book3e
129 /* Core exception code for all exceptions except TLB misses.
130 * XXX: Needs to make SPRN_SPRG_GEN depend on exception type
132 #define EXCEPTION_COMMON(n, excf, ints) \
133 std r0,GPR0(r1); /* save r0 in stackframe */ \
134 std r2,GPR2(r1); /* save r2 in stackframe */ \
135 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
136 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
137 std r9,GPR9(r1); /* save r9 in stackframe */ \
138 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
139 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
140 ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \
141 ld r3,excf+EX_R10(r13); /* get back r10 */ \
142 ld r4,excf+EX_R11(r13); /* get back r11 */ \
143 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \
144 std r12,GPR12(r1); /* save r12 in stackframe */ \
145 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
146 mflr r6; /* save LR in stackframe */ \
147 mfctr r7; /* save CTR in stackframe */ \
148 mfspr r8,SPRN_XER; /* save XER in stackframe */ \
149 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
150 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
151 lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \
152 ld r12,exception_marker@toc(r2); \
154 std r3,GPR10(r1); /* save r10 to stackframe */ \
155 std r4,GPR11(r1); /* save r11 to stackframe */ \
156 std r5,GPR13(r1); /* save it to stackframe */ \
160 li r3,(n)+1; /* indicate partial regs in trap */ \
161 std r9,0(r1); /* store stack frame back link */ \
162 std r10,_CCR(r1); /* store orig CR in stackframe */ \
163 std r9,GPR1(r1); /* store stack frame back link */ \
164 std r11,SOFTE(r1); /* and save it to stackframe */ \
165 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
166 std r3,_TRAP(r1); /* set trap number */ \
167 std r0,RESULT(r1); /* clear regs->result */ \
170 /* Variants for the "ints" argument */
172 #define INTS_DISABLE_SOFT \
173 stb r0,PACASOFTIRQEN(r13); /* mark interrupts soft-disabled */ \
175 #define INTS_DISABLE_HARD \
176 stb r0,PACAHARDIRQEN(r13); /* and hard disabled */
177 #define INTS_DISABLE_ALL \
181 /* This is called by exceptions that used INTS_KEEP (that is did not clear
182 * neither soft nor hard IRQ indicators in the PACA. This will restore MSR:EE
183 * to it's previous value
185 * XXX In the long run, we may want to open-code it in order to separate the
186 * load from the wrtee, thus limiting the latency caused by the dependency
187 * but at this point, I'll favor code clarity until we have a near to final
190 #define INTS_RESTORE_HARD \
194 /* XXX FIXME: Restore r14/r15 when necessary */
195 #define BAD_STACK_TRAMPOLINE(n) \
196 exc_##n##_bad_stack: \
197 li r1,(n); /* get exception number */ \
198 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
199 b bad_stack_book3e; /* bad stack error */
201 /* WARNING: If you change the layout of this stub, make sure you chcek
202 * the debug exception handler which handles single stepping
203 * into exceptions from userspace, and the MM code in
204 * arch/powerpc/mm/tlb_nohash.c which patches the branch here
205 * and would need to be updated if that branch is moved
207 #define EXCEPTION_STUB(loc, label) \
208 . = interrupt_base_book3e + loc; \
209 nop; /* To make debug interrupts happy */ \
210 b exc_##label##_book3e;
220 /* Used by asynchronous interrupt that may happen in the idle loop.
222 * This check if the thread was in the idle loop, and if yes, returns
223 * to the caller rather than the PC. This is to avoid a race if
224 * interrupts happen before the wait instruction.
226 #define CHECK_NAPPING() \
227 clrrdi r11,r1,THREAD_SHIFT; \
228 ld r10,TI_LOCAL_FLAGS(r11); \
229 andi. r9,r10,_TLF_NAPPING; \
232 rlwinm r7,r10,0,~_TLF_NAPPING; \
234 std r7,TI_LOCAL_FLAGS(r11); \
238 #define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack) \
239 START_EXCEPTION(label); \
240 NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE) \
241 EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE_ALL) \
244 addi r3,r1,STACK_FRAME_OVERHEAD; \
246 b .ret_from_except_lite;
248 /* This value is used to mark exception frames on the stack. */
251 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
255 * And here we have the exception vectors !
260 .globl interrupt_base_book3e
261 interrupt_base_book3e: /* fake trap */
262 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */
263 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */
264 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
265 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
266 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
267 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
268 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
269 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
270 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
271 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
272 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
273 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
274 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
275 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
276 EXCEPTION_STUB(0x1c0, data_tlb_miss)
277 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
278 EXCEPTION_STUB(0x260, perfmon)
279 EXCEPTION_STUB(0x280, doorbell)
280 EXCEPTION_STUB(0x2a0, doorbell_crit)
281 EXCEPTION_STUB(0x2c0, guest_doorbell)
282 EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
283 EXCEPTION_STUB(0x300, hypercall)
284 EXCEPTION_STUB(0x320, ehpriv)
286 .globl interrupt_end_book3e
287 interrupt_end_book3e:
289 /* Critical Input Interrupt */
290 START_EXCEPTION(critical_input);
291 CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
292 // EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE_ALL)
293 // bl special_reg_save_crit
295 // addi r3,r1,STACK_FRAME_OVERHEAD
296 // bl .critical_exception
297 // b ret_from_crit_except
300 /* Machine Check Interrupt */
301 START_EXCEPTION(machine_check);
302 CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
303 // EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE_ALL)
304 // bl special_reg_save_mc
305 // addi r3,r1,STACK_FRAME_OVERHEAD
307 // bl .machine_check_exception
308 // b ret_from_mc_except
311 /* Data Storage Interrupt */
312 START_EXCEPTION(data_storage)
313 NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
316 EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE_ALL)
317 b storage_fault_common
319 /* Instruction Storage Interrupt */
320 START_EXCEPTION(instruction_storage);
321 NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
324 EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE_ALL)
325 b storage_fault_common
327 /* External Input Interrupt */
328 MASKABLE_EXCEPTION(0x500, external_input, .do_IRQ, ACK_NONE)
331 START_EXCEPTION(alignment);
332 NORMAL_EXCEPTION_PROLOG(0x600, PROLOG_ADDITION_2REGS)
335 EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
336 b alignment_more /* no room, go out of line */
338 /* Program Interrupt */
339 START_EXCEPTION(program);
340 NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG)
342 EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE_SOFT)
344 addi r3,r1,STACK_FRAME_OVERHEAD
345 ld r14,PACA_EXGEN+EX_R14(r13)
348 bl .program_check_exception
351 /* Floating Point Unavailable Interrupt */
352 START_EXCEPTION(fp_unavailable);
353 NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
354 /* we can probably do a shorter exception entry for that one... */
355 EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
356 bne 1f /* if from user, just load it up */
359 addi r3,r1,STACK_FRAME_OVERHEAD
360 bl .kernel_fp_unavailable_exception
364 b fast_exception_return
366 /* Decrementer Interrupt */
367 MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC)
369 /* Fixed Interval Timer Interrupt */
370 MASKABLE_EXCEPTION(0x980, fixed_interval, .unknown_exception, ACK_FIT)
372 /* Watchdog Timer Interrupt */
373 START_EXCEPTION(watchdog);
374 CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
375 // EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE_ALL)
376 // bl special_reg_save_crit
378 // addi r3,r1,STACK_FRAME_OVERHEAD
379 // bl .unknown_exception
380 // b ret_from_crit_except
383 /* System Call Interrupt */
384 START_EXCEPTION(system_call)
385 mr r9,r13 /* keep a copy of userland r13 */
386 mfspr r11,SPRN_SRR0 /* get return address */
387 mfspr r12,SPRN_SRR1 /* get previous MSR */
388 mfspr r13,SPRN_SPRG_PACA /* get our PACA */
391 /* Auxiliary Processor Unavailable Interrupt */
392 START_EXCEPTION(ap_unavailable);
393 NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE)
394 EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE_ALL)
396 addi r3,r1,STACK_FRAME_OVERHEAD
397 bl .unknown_exception
400 /* Debug exception as a critical interrupt*/
401 START_EXCEPTION(debug_crit);
402 CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
405 * If there is a single step or branch-taken exception in an
406 * exception entry sequence, it was probably meant to apply to
407 * the code where the exception occurred (since exception entry
408 * doesn't turn off DE automatically). We simulate the effect
409 * of turning off DE on entry to an exception handler by turning
410 * off DE in the CSRR1 value and clearing the debug status.
413 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
414 andis. r15,r14,DBSR_IC@h
417 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
418 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
424 /* here it looks like we got an inappropriate debug exception. */
425 lis r14,DBSR_IC@h /* clear the IC event */
426 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
429 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
430 ld r1,PACA_EXCRIT+EX_R1(r13)
431 ld r14,PACA_EXCRIT+EX_R14(r13)
432 ld r15,PACA_EXCRIT+EX_R15(r13)
434 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
435 ld r11,PACA_EXCRIT+EX_R11(r13)
436 mfspr r13,SPRN_SPRG_CRIT_SCRATCH
439 /* Normal debug exception */
440 /* XXX We only handle coming from userspace for now since we can't
441 * quite save properly an interrupted kernel state yet
443 1: andi. r14,r11,MSR_PR; /* check for userspace again */
444 beq kernel_dbg_exc; /* if from kernel mode */
446 /* Now we mash up things to make it look like we are coming on a
449 mfspr r15,SPRN_SPRG_CRIT_SCRATCH
450 mtspr SPRN_SPRG_GEN_SCRATCH,r15
452 EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE_ALL)
454 addi r3,r1,STACK_FRAME_OVERHEAD
456 ld r14,PACA_EXCRIT+EX_R14(r13)
457 ld r15,PACA_EXCRIT+EX_R15(r13)
465 /* Debug exception as a debug interrupt*/
466 START_EXCEPTION(debug_debug);
467 DBG_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
470 * If there is a single step or branch-taken exception in an
471 * exception entry sequence, it was probably meant to apply to
472 * the code where the exception occurred (since exception entry
473 * doesn't turn off DE automatically). We simulate the effect
474 * of turning off DE on entry to an exception handler by turning
475 * off DE in the DSRR1 value and clearing the debug status.
478 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
479 andis. r15,r14,DBSR_IC@h
482 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
483 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
489 /* here it looks like we got an inappropriate debug exception. */
490 lis r14,DBSR_IC@h /* clear the IC event */
491 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
494 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
495 ld r1,PACA_EXDBG+EX_R1(r13)
496 ld r14,PACA_EXDBG+EX_R14(r13)
497 ld r15,PACA_EXDBG+EX_R15(r13)
499 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
500 ld r11,PACA_EXDBG+EX_R11(r13)
501 mfspr r13,SPRN_SPRG_DBG_SCRATCH
504 /* Normal debug exception */
505 /* XXX We only handle coming from userspace for now since we can't
506 * quite save properly an interrupted kernel state yet
508 1: andi. r14,r11,MSR_PR; /* check for userspace again */
509 beq kernel_dbg_exc; /* if from kernel mode */
511 /* Now we mash up things to make it look like we are coming on a
514 mfspr r15,SPRN_SPRG_DBG_SCRATCH
515 mtspr SPRN_SPRG_GEN_SCRATCH,r15
517 EXCEPTION_COMMON(0xd00, PACA_EXDBG, INTS_DISABLE_ALL)
519 addi r3,r1,STACK_FRAME_OVERHEAD
521 ld r14,PACA_EXDBG+EX_R14(r13)
522 ld r15,PACA_EXDBG+EX_R15(r13)
527 MASKABLE_EXCEPTION(0x260, perfmon, .performance_monitor_exception, ACK_NONE)
529 /* Doorbell interrupt */
530 START_EXCEPTION(doorbell)
531 NORMAL_EXCEPTION_PROLOG(0x2070, PROLOG_ADDITION_DOORBELL)
532 EXCEPTION_COMMON(0x2070, PACA_EXGEN, INTS_DISABLE_ALL)
534 addi r3,r1,STACK_FRAME_OVERHEAD
535 bl .doorbell_exception
536 b .ret_from_except_lite
538 /* Doorbell critical Interrupt */
539 START_EXCEPTION(doorbell_crit);
540 CRIT_EXCEPTION_PROLOG(0x2080, PROLOG_ADDITION_NONE)
541 // EXCEPTION_COMMON(0x2080, PACA_EXCRIT, INTS_DISABLE_ALL)
542 // bl special_reg_save_crit
544 // addi r3,r1,STACK_FRAME_OVERHEAD
545 // bl .doorbell_critical_exception
546 // b ret_from_crit_except
549 MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception, ACK_NONE)
550 MASKABLE_EXCEPTION(0x2e0, guest_doorbell_crit, .unknown_exception, ACK_NONE)
551 MASKABLE_EXCEPTION(0x310, hypercall, .unknown_exception, ACK_NONE)
552 MASKABLE_EXCEPTION(0x320, ehpriv, .unknown_exception, ACK_NONE)
556 * An interrupt came in while soft-disabled; clear EE in SRR1,
557 * clear paca->hard_enabled and return.
559 masked_doorbell_book3e:
561 /* Resend the doorbell to fire again when ints enabled */
564 b masked_interrupt_book3e_common
566 masked_interrupt_book3e:
568 masked_interrupt_book3e_common:
569 stb r11,PACAHARDIRQEN(r13)
571 rldicl r11,r10,48,1 /* clear MSR_EE */
574 ld r10,PACA_EXGEN+EX_R10(r13); /* restore registers */
575 ld r11,PACA_EXGEN+EX_R11(r13);
576 mfspr r13,SPRN_SPRG_GEN_SCRATCH;
581 * This is called from 0x300 and 0x400 handlers after the prologs with
582 * r14 and r15 containing the fault address and error code, with the
583 * original values stashed away in the PACA
585 storage_fault_common:
588 addi r3,r1,STACK_FRAME_OVERHEAD
591 ld r14,PACA_EXGEN+EX_R14(r13)
592 ld r15,PACA_EXGEN+EX_R15(r13)
596 b .ret_from_except_lite
599 addi r3,r1,STACK_FRAME_OVERHEAD
605 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
611 addi r3,r1,STACK_FRAME_OVERHEAD
612 ld r14,PACA_EXGEN+EX_R14(r13)
613 ld r15,PACA_EXGEN+EX_R15(r13)
616 bl .alignment_exception
620 * We branch here from entry_64.S for the last stage of the exception
621 * return code path. MSR:EE is expected to be off at that point
623 _GLOBAL(exception_return_book3e)
626 /* This is the return from load_up_fpu fast path which could do with
627 * less GPR restores in fact, but for now we have a single return path
629 .globl fast_exception_return
630 fast_exception_return:
638 ACCOUNT_CPU_USER_EXIT(r10, r11)
641 1: stdcx. r0,0,r1 /* to clear the reservation */
655 mtspr SPRN_SPRG_GEN_SCRATCH,r0
657 std r10,PACA_EXGEN+EX_R10(r13);
658 std r11,PACA_EXGEN+EX_R11(r13);
665 ld r10,PACA_EXGEN+EX_R10(r13)
666 ld r11,PACA_EXGEN+EX_R11(r13)
667 mfspr r13,SPRN_SPRG_GEN_SCRATCH
671 * Trampolines used when spotting a bad kernel stack pointer in
672 * the exception entry code.
674 * TODO: move some bits like SRR0 read to trampoline, pass PACA
675 * index around, etc... to handle crit & mcheck
677 BAD_STACK_TRAMPOLINE(0x000)
678 BAD_STACK_TRAMPOLINE(0x100)
679 BAD_STACK_TRAMPOLINE(0x200)
680 BAD_STACK_TRAMPOLINE(0x260)
681 BAD_STACK_TRAMPOLINE(0x2c0)
682 BAD_STACK_TRAMPOLINE(0x2e0)
683 BAD_STACK_TRAMPOLINE(0x300)
684 BAD_STACK_TRAMPOLINE(0x310)
685 BAD_STACK_TRAMPOLINE(0x320)
686 BAD_STACK_TRAMPOLINE(0x400)
687 BAD_STACK_TRAMPOLINE(0x500)
688 BAD_STACK_TRAMPOLINE(0x600)
689 BAD_STACK_TRAMPOLINE(0x700)
690 BAD_STACK_TRAMPOLINE(0x800)
691 BAD_STACK_TRAMPOLINE(0x900)
692 BAD_STACK_TRAMPOLINE(0x980)
693 BAD_STACK_TRAMPOLINE(0x9f0)
694 BAD_STACK_TRAMPOLINE(0xa00)
695 BAD_STACK_TRAMPOLINE(0xb00)
696 BAD_STACK_TRAMPOLINE(0xc00)
697 BAD_STACK_TRAMPOLINE(0xd00)
698 BAD_STACK_TRAMPOLINE(0xe00)
699 BAD_STACK_TRAMPOLINE(0xf00)
700 BAD_STACK_TRAMPOLINE(0xf20)
701 BAD_STACK_TRAMPOLINE(0x2070)
702 BAD_STACK_TRAMPOLINE(0x2080)
704 .globl bad_stack_book3e
706 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
707 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
708 ld r1,PACAEMERGSP(r13)
709 subi r1,r1,64+INT_FRAME_SIZE
712 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
713 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
720 std r0,GPR0(r1); /* save r0 in stackframe */ \
721 std r2,GPR2(r1); /* save r2 in stackframe */ \
722 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
723 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
724 std r9,GPR9(r1); /* save r9 in stackframe */ \
725 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
726 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
727 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
728 std r3,GPR10(r1); /* save r10 to stackframe */ \
729 std r4,GPR11(r1); /* save r11 to stackframe */ \
730 std r12,GPR12(r1); /* save r12 in stackframe */ \
731 std r5,GPR13(r1); /* save it to stackframe */ \
740 lhz r12,PACA_TRAP_SAVE(r13)
742 addi r11,r1,INT_FRAME_SIZE
747 1: addi r3,r1,STACK_FRAME_OVERHEAD
752 * Setup the initial TLB for a core. This current implementation
753 * assume that whatever we are running off will not conflict with
754 * the new mapping at PAGE_OFFSET.
756 _GLOBAL(initial_tlb_book3e)
758 /* Look for the first TLB with IPROT set */
759 mfspr r4,SPRN_TLB0CFG
760 andi. r3,r4,TLBnCFG_IPROT
761 lis r3,MAS0_TLBSEL(0)@h
764 mfspr r4,SPRN_TLB1CFG
765 andi. r3,r4,TLBnCFG_IPROT
766 lis r3,MAS0_TLBSEL(1)@h
769 mfspr r4,SPRN_TLB2CFG
770 andi. r3,r4,TLBnCFG_IPROT
771 lis r3,MAS0_TLBSEL(2)@h
774 lis r3,MAS0_TLBSEL(3)@h
775 mfspr r4,SPRN_TLB3CFG
779 andi. r5,r4,TLBnCFG_HES
782 mflr r8 /* save LR */
783 /* 1. Find the index of the entry we're executing in
785 * r3 = MAS0_TLBSEL (for the iprot array)
788 bl invstr /* Find our address */
789 invstr: mflr r6 /* Make it accessible */
791 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
796 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
799 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
801 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
802 oris r7,r7,MAS1_IPROT@h
806 /* 2. Invalidate all entries except the entry we're executing in
808 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
810 * r5 = ESEL of entry we are running in
812 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
813 li r6,0 /* Set Entry counter to 0 */
814 1: mr r7,r3 /* Set MAS0(TLBSEL) */
815 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
819 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
821 beq skpinv /* Dont update the current execution TLB */
825 skpinv: addi r6,r6,1 /* Increment */
826 cmpw r6,r4 /* Are we done? */
827 bne 1b /* If not, repeat */
829 /* Invalidate all TLBs */
834 /* 3. Setup a temp mapping and jump to it
836 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
837 * r5 = ESEL of entry we are running in
839 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
841 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
845 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
849 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
857 bl 1f /* Find our address */
864 /* 4. Clear out PIDs & Search info
866 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
867 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
874 /* 5. Invalidate mapping we started in
876 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
877 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
883 rlwinm r6,r6,0,2,0 /* clear IPROT */
887 /* Invalidate TLB1 */
892 /* The mapping only needs to be cache-coherent on SMP */
894 #define M_IF_SMP MAS2_M
899 /* 6. Setup KERNELBASE mapping in TLB[0]
901 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
902 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
905 rlwinm r3,r3,0,16,3 /* clear ESEL */
907 lis r6,(MAS1_VALID|MAS1_IPROT)@h
908 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
911 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
915 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
922 /* 7. Jump to KERNELBASE mapping
924 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
926 /* Now we branch the new virtual address mapped by this entry */
927 LOAD_REG_IMMEDIATE(r6,2f)
929 ori r7,r7,MSR_KERNEL@l
932 rfi /* start execution out of TLB1[0] entry */
935 /* 8. Clear out the temp mapping
937 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
942 rlwinm r5,r5,0,2,0 /* clear IPROT */
946 /* Invalidate TLB1 */
951 /* We translate LR and return */
957 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
958 * kernel linear mapping. We also set MAS8 once for all here though
959 * that will have to be made dependent on whether we are running under
960 * a hypervisor I suppose.
964 * This code is called as an ordinary function on the boot CPU. But to
965 * avoid duplication, this code is also used in SCOM bringup of
966 * secondary CPUs. We read the code between the initial_tlb_code_start
967 * and initial_tlb_code_end labels one instruction at a time and RAM it
968 * into the new core via SCOM. That doesn't process branches, so there
969 * must be none between those two labels. It also means if this code
970 * ever takes any parameters, the SCOM code must also be updated to
973 .globl a2_tlbinit_code_start
974 a2_tlbinit_code_start:
976 ori r11,r3,MAS0_WQ_ALLWAYS
977 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
979 lis r3,(MAS1_VALID | MAS1_IPROT)@h
980 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
982 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
984 li r3,MAS3_SR | MAS3_SW | MAS3_SX
985 mtspr SPRN_MAS7_MAS3,r3
989 /* Write the TLB entry */
992 .globl a2_tlbinit_after_linear_map
993 a2_tlbinit_after_linear_map:
995 /* Now we branch the new virtual address mapped by this entry */
996 LOAD_REG_IMMEDIATE(r3,1f)
1000 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
1001 * else (including IPROTed things left by firmware)
1003 * r3 = current address (more or less)
1010 rlwinm r9,r4,0,TLBnCFG_N_ENTRY
1011 rlwinm r10,r4,8,0xff
1012 addi r10,r10,-1 /* Get inner loop mask */
1017 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1020 rldicr r6,r6,0,51 /* Extract EPN */
1023 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
1025 rlwinm r8,r7,16,0xfff /* Extract ESEL */
1030 rlwimi r7,r4,16,MAS0_ESEL_MASK
1041 addis r6,r6,(1<<30)@h
1046 .globl a2_tlbinit_after_iprot_flush
1047 a2_tlbinit_after_iprot_flush:
1049 #ifdef CONFIG_PPC_EARLY_DEBUG_WSP
1050 /* Now establish early debug mappings if applicable */
1051 /* Restore the MAS0 we used for linear mapping load */
1054 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1055 ori r3,r3,(BOOK3E_PAGESZ_4K << MAS1_TSIZE_SHIFT)
1057 LOAD_REG_IMMEDIATE(r3, WSP_UART_VIRT | MAS2_I | MAS2_G)
1059 LOAD_REG_IMMEDIATE(r3, WSP_UART_PHYS | MAS3_SR | MAS3_SW)
1060 mtspr SPRN_MAS7_MAS3,r3
1061 /* re-use the MAS8 value from the linear mapping */
1063 #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
1069 .globl a2_tlbinit_code_end
1070 a2_tlbinit_code_end:
1072 /* We translate LR and return */
1079 * Main entry (boot CPU, thread 0)
1081 * We enter here from head_64.S, possibly after the prom_init trampoline
1082 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1083 * mode. Anything else is as it was left by the bootloader
1085 * Initial requirements of this port:
1087 * - Kernel loaded at 0 physical
1088 * - A good lump of memory mapped 0:0 by UTLB entry 0
1089 * - MSR:IS & MSR:DS set to 0
1091 * Note that some of the above requirements will be relaxed in the future
1092 * as the kernel becomes smarter at dealing with different initial conditions
1093 * but for now you have to be careful
1095 _GLOBAL(start_initialization_book3e)
1098 /* First, we need to setup some initial TLBs to map the kernel
1099 * text, data and bss at PAGE_OFFSET. We don't have a real mode
1100 * and always use AS 0, so we just set it up to match our link
1101 * address and never use 0 based addresses.
1103 bl .initial_tlb_book3e
1105 /* Init global core bits */
1106 bl .init_core_book3e
1108 /* Init per-thread bits */
1109 bl .init_thread_book3e
1111 /* Return to common init code */
1118 * Secondary core/processor entry
1120 * This is entered for thread 0 of a secondary core, all other threads
1121 * are expected to be stopped. It's similar to start_initialization_book3e
1122 * except that it's generally entered from the holding loop in head_64.S
1123 * after CPUs have been gathered by Open Firmware.
1125 * We assume we are in 32 bits mode running with whatever TLB entry was
1126 * set for us by the firmware or POR engine.
1128 _GLOBAL(book3e_secondary_core_init_tlb_set)
1130 b .generic_secondary_smp_init
1132 _GLOBAL(book3e_secondary_core_init)
1135 /* Do we need to setup initial TLB entry ? */
1139 /* Setup TLB for this core */
1140 bl .initial_tlb_book3e
1142 /* We can return from the above running at a different
1143 * address, so recalculate r2 (TOC)
1147 /* Init global core bits */
1148 2: bl .init_core_book3e
1150 /* Init per-thread bits */
1151 3: bl .init_thread_book3e
1153 /* Return to common init code at proper virtual address.
1155 * Due to various previous assumptions, we know we entered this
1156 * function at either the final PAGE_OFFSET mapping or using a
1157 * 1:1 mapping at 0, so we don't bother doing a complicated check
1158 * here, we just ensure the return address has the right top bits.
1160 * Note that if we ever want to be smarter about where we can be
1161 * started from, we have to be careful that by the time we reach
1162 * the code below we may already be running at a different location
1163 * than the one we were called from since initial_tlb_book3e can
1164 * have moved us already.
1168 lis r3,PAGE_OFFSET@highest
1174 _GLOBAL(book3e_secondary_thread_init)
1178 _STATIC(init_core_book3e)
1179 /* Establish the interrupt vector base */
1180 LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e)
1185 _STATIC(init_thread_book3e)
1186 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1189 /* Make sure interrupts are off */
1192 /* disable all timers and clear out status */
1200 _GLOBAL(__setup_base_ivors)
1201 SET_IVOR(0, 0x020) /* Critical Input */
1202 SET_IVOR(1, 0x000) /* Machine Check */
1203 SET_IVOR(2, 0x060) /* Data Storage */
1204 SET_IVOR(3, 0x080) /* Instruction Storage */
1205 SET_IVOR(4, 0x0a0) /* External Input */
1206 SET_IVOR(5, 0x0c0) /* Alignment */
1207 SET_IVOR(6, 0x0e0) /* Program */
1208 SET_IVOR(7, 0x100) /* FP Unavailable */
1209 SET_IVOR(8, 0x120) /* System Call */
1210 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1211 SET_IVOR(10, 0x160) /* Decrementer */
1212 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1213 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1214 SET_IVOR(13, 0x1c0) /* Data TLB Error */
1215 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1216 SET_IVOR(15, 0x040) /* Debug */
1222 _GLOBAL(setup_perfmon_ivor)
1223 SET_IVOR(35, 0x260) /* Performance Monitor */
1226 _GLOBAL(setup_doorbell_ivors)
1227 SET_IVOR(36, 0x280) /* Processor Doorbell */
1228 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1230 /* Check MMUCFG[LPIDSIZE] to determine if we have category E.HV */
1231 mfspr r10,SPRN_MMUCFG
1232 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1235 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1236 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1239 _GLOBAL(setup_ehv_ivors)
1241 * We may be running as a guest and lack E.HV even on a chip
1242 * that normally has it.
1244 mfspr r10,SPRN_MMUCFG
1245 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1248 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1249 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */