1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
5 #include <asm/asm-compat.h>
6 #include <asm/feature-fixups.h>
7 #include <uapi/asm/cputable.h>
11 /* This structure can grow, it's real size is used by head.S code
12 * via the mkdefs mechanism.
16 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
17 typedef void (*cpu_restore_t)(void);
19 enum powerpc_oprofile_type {
20 PPC_OPROFILE_INVALID = 0,
21 PPC_OPROFILE_RS64 = 1,
22 PPC_OPROFILE_POWER4 = 2,
24 PPC_OPROFILE_FSL_EMB = 4,
25 PPC_OPROFILE_CELL = 5,
26 PPC_OPROFILE_PA6T = 6,
29 enum powerpc_pmc_type {
38 extern int machine_check_generic(struct pt_regs *regs);
39 extern int machine_check_4xx(struct pt_regs *regs);
40 extern int machine_check_440A(struct pt_regs *regs);
41 extern int machine_check_e500mc(struct pt_regs *regs);
42 extern int machine_check_e500(struct pt_regs *regs);
43 extern int machine_check_e200(struct pt_regs *regs);
44 extern int machine_check_47x(struct pt_regs *regs);
46 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
48 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
49 unsigned int pvr_mask;
50 unsigned int pvr_value;
53 unsigned long cpu_features; /* Kernel features */
54 unsigned int cpu_user_features; /* Userland features */
55 unsigned int cpu_user_features2; /* Userland features v2 */
56 unsigned int mmu_features; /* MMU features */
58 /* cache line sizes */
59 unsigned int icache_bsize;
60 unsigned int dcache_bsize;
62 /* number of performance monitor counters */
63 unsigned int num_pmcs;
64 enum powerpc_pmc_type pmc_type;
66 /* this is called to initialize various CPU bits like L1 cache,
67 * BHT, SPD, etc... from head.S before branching to identify_machine
69 cpu_setup_t cpu_setup;
70 /* Used to restore cpu setup on secondary processors and at resume */
71 cpu_restore_t cpu_restore;
73 /* Used by oprofile userspace to select the right counters */
74 char *oprofile_cpu_type;
76 /* Processor specific oprofile operations */
77 enum powerpc_oprofile_type oprofile_type;
79 /* Bit locations inside the mmcra change */
80 unsigned long oprofile_mmcra_sihv;
81 unsigned long oprofile_mmcra_sipr;
83 /* Bits to clear during an oprofile exception */
84 unsigned long oprofile_mmcra_clear;
86 /* Name of processor class, for the ELF AT_PLATFORM entry */
89 /* Processor specific machine check handling. Return negative
90 * if the error is fatal, 1 if it was fully recovered and 0 to
91 * pass up (not CPU originated) */
92 int (*machine_check)(struct pt_regs *regs);
95 extern struct cpu_spec *cur_cpu_spec;
97 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
99 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
100 extern void do_feature_fixups(unsigned long value, void *fixup_start,
103 extern const char *powerpc_base_platform;
105 #endif /* __ASSEMBLY__ */
107 /* CPU kernel features */
109 /* Retain the 32b definitions all use bottom half of word */
110 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
111 #define CPU_FTR_L2CR ASM_CONST(0x00000002)
112 #define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
113 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
114 #define CPU_FTR_TAU ASM_CONST(0x00000010)
115 #define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
116 #define CPU_FTR_USE_TB ASM_CONST(0x00000040)
117 #define CPU_FTR_L2CSR ASM_CONST(0x00000080)
118 #define CPU_FTR_601 ASM_CONST(0x00000100)
119 #define CPU_FTR_DBELL ASM_CONST(0x00000200)
120 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
121 #define CPU_FTR_L3CR ASM_CONST(0x00000800)
122 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
123 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
124 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
125 #define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
126 #define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
127 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
128 #define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
129 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
130 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
131 #define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
132 #define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
133 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
134 #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
135 #define CPU_FTR_SPE ASM_CONST(0x02000000)
136 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
137 #define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
138 #define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
139 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
140 #define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
143 * Add the 64-bit processor unique features in the top half of the word;
144 * on 32-bit, make the names available but defined to be 0.
147 #define LONG_ASM_CONST(x) ASM_CONST(x)
149 #define LONG_ASM_CONST(x) 0
152 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
153 #define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
154 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
155 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0000000800000000)
156 #define CPU_FTR_IABR LONG_ASM_CONST(0x0000001000000000)
157 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
158 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
159 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
160 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
161 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
162 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
163 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
164 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
165 #define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
166 #define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
167 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
168 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
169 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
170 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
171 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
172 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
173 #define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
174 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
175 #define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
176 #define CPU_FTR_BCTAR LONG_ASM_CONST(0x0100000000000000)
177 #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
178 #define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
182 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
184 #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
187 /* We only set the altivec features if the kernel was compiled with altivec
190 #ifdef CONFIG_ALTIVEC
191 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
192 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
194 #define CPU_FTR_ALTIVEC_COMP 0
195 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
198 /* We only set the VSX features if the kernel was compiled with VSX
202 #define CPU_FTR_VSX_COMP CPU_FTR_VSX
203 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
205 #define CPU_FTR_VSX_COMP 0
206 #define PPC_FEATURE_HAS_VSX_COMP 0
209 /* We only set the spe features if the kernel was compiled with spe
213 #define CPU_FTR_SPE_COMP CPU_FTR_SPE
214 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
215 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
216 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
218 #define CPU_FTR_SPE_COMP 0
219 #define PPC_FEATURE_HAS_SPE_COMP 0
220 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
221 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
224 /* We only set the TM feature if the kernel was compiled with TM supprt */
225 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
226 #define CPU_FTR_TM_COMP CPU_FTR_TM
228 #define CPU_FTR_TM_COMP 0
231 /* We need to mark all pages as being coherent if we're SMP or we have a
232 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
233 * require it for PCI "streaming/prefetch" to work properly.
234 * This is also required by 52xx family.
236 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
237 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
238 || defined(CONFIG_PPC_MPC52xx)
239 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
241 #define CPU_FTR_COMMON 0
244 /* The powersave features NAP & DOZE seems to confuse BDI when
245 debugging. So if a BDI is used, disable theses
247 #ifndef CONFIG_BDI_SWITCH
248 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
249 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
251 #define CPU_FTR_MAYBE_CAN_DOZE 0
252 #define CPU_FTR_MAYBE_CAN_NAP 0
255 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
256 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
257 !defined(CONFIG_BOOKE))
259 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
260 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
261 #define CPU_FTRS_603 (CPU_FTR_COMMON | \
262 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
263 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
264 #define CPU_FTRS_604 (CPU_FTR_COMMON | \
265 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
266 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
267 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
268 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
269 #define CPU_FTRS_740 (CPU_FTR_COMMON | \
270 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
271 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
273 #define CPU_FTRS_750 (CPU_FTR_COMMON | \
274 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
275 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
277 #define CPU_FTRS_750CL (CPU_FTRS_750)
278 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
279 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
280 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
281 #define CPU_FTRS_750GX (CPU_FTRS_750FX)
282 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
283 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
284 CPU_FTR_ALTIVEC_COMP | \
285 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
286 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \
287 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
288 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
289 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
290 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
291 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
292 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
293 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
294 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
297 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
298 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
299 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
300 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
301 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
302 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
303 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
304 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
305 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
306 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
307 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
308 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
309 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
310 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
311 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
312 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
313 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
314 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
315 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \
317 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
318 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
319 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
320 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
322 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
323 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
324 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
325 CPU_FTR_NEED_PAIRED_STWCX)
326 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \
328 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
329 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
330 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
331 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \
333 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
334 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
335 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
336 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \
338 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
339 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
340 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
341 #define CPU_FTRS_82XX (CPU_FTR_COMMON | \
342 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
343 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
344 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
345 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
346 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
348 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
349 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
350 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
351 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
352 #define CPU_FTRS_8XX (CPU_FTR_USE_TB)
353 #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
354 #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
355 #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
357 #define CPU_FTRS_47X (CPU_FTRS_440x6)
358 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
359 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
360 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
361 CPU_FTR_DEBUG_LVL_EXC)
362 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
363 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
365 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
366 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
367 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
368 #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
369 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
370 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
371 #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
372 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
373 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
374 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
375 #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
376 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
377 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
378 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP)
379 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
382 #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
383 CPU_FTR_IABR | CPU_FTR_PPC_LE)
384 #define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
386 CPU_FTR_MMCRA | CPU_FTR_CTRL)
387 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
388 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
389 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
390 CPU_FTR_STCX_CHECKS_ADDRESS)
391 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
392 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
393 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
394 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
396 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
397 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
398 CPU_FTR_MMCRA | CPU_FTR_SMT | \
399 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
400 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
401 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
402 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
403 CPU_FTR_MMCRA | CPU_FTR_SMT | \
404 CPU_FTR_COHERENT_ICACHE | \
405 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
406 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
407 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
408 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
409 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
410 CPU_FTR_MMCRA | CPU_FTR_SMT | \
411 CPU_FTR_COHERENT_ICACHE | \
412 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
413 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
414 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
415 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
416 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)
417 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
418 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
419 CPU_FTR_MMCRA | CPU_FTR_SMT | \
420 CPU_FTR_COHERENT_ICACHE | \
421 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
422 CPU_FTR_DSCR | CPU_FTR_SAO | \
423 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
424 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
425 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | CPU_FTR_BCTAR | \
427 #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
428 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
429 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
430 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
431 CPU_FTR_UNALIGNED_LD_STD)
432 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
433 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
434 CPU_FTR_PURR | CPU_FTR_REAL_LE)
435 #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
437 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
438 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
441 #ifdef CONFIG_PPC_BOOK3E
442 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
444 #define CPU_FTRS_POSSIBLE \
445 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
446 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
447 CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL | \
448 CPU_FTRS_PA6T | CPU_FTR_VSX)
454 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
455 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
456 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
457 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
458 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
459 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
460 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
461 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
464 CPU_FTRS_GENERIC_32 |
473 CPU_FTRS_44X | CPU_FTRS_440x6 |
475 #ifdef CONFIG_PPC_47x
476 CPU_FTRS_47X | CPU_FTR_476_DD2 |
482 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
484 #ifdef CONFIG_PPC_E500MC
485 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
489 #endif /* __powerpc64__ */
492 #ifdef CONFIG_PPC_BOOK3E
493 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
495 #define CPU_FTRS_ALWAYS \
496 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
497 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
498 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
504 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
505 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
506 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
507 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
508 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
509 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
510 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
511 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
514 CPU_FTRS_GENERIC_32 &
523 CPU_FTRS_44X & CPU_FTRS_440x6 &
529 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
531 #ifdef CONFIG_PPC_E500MC
532 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
534 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
537 #endif /* __powerpc64__ */
539 static inline int cpu_has_feature(unsigned long feature)
541 return (CPU_FTRS_ALWAYS & feature) ||
543 & cur_cpu_spec->cpu_features
549 #endif /* !__ASSEMBLY__ */
551 #endif /* __ASM_POWERPC_CPUTABLE_H */