2 * base MPC5121 Device Tree Source
4 * Copyright 2007-2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
16 compatible = "fsl,mpc5121";
19 interrupt-parent = <&ipic>;
33 d-cache-line-size = <0x20>; /* 32 bytes */
34 i-cache-line-size = <0x20>; /* 32 bytes */
35 d-cache-size = <0x8000>; /* L1, 32K */
36 i-cache-size = <0x8000>; /* L1, 32K */
37 timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
38 bus-frequency = <198000000>; /* 198 MHz csb bus */
39 clock-frequency = <396000000>; /* 396 MHz ppc core */
44 device_type = "memory";
45 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
49 compatible = "fsl,mpc5121-mbx";
50 reg = <0x20000000 0x4000>;
51 interrupts = <66 0x8>;
55 compatible = "fsl,mpc5121-sram";
56 reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */
60 compatible = "fsl,mpc5121-nfc";
61 reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */
68 compatible = "fsl,mpc5121-localbus";
71 reg = <0x80000020 0x40>;
73 ranges = <0x0 0x0 0xfc000000 0x04000000>;
77 compatible = "fsl,mpc5121-immr";
80 ranges = <0x0 0x80000000 0x400000>;
81 reg = <0x80000000 0x400000>;
82 bus-frequency = <66000000>; /* 66 MHz ips bus */
87 * interrupts cell = <intr #, sense>
88 * sense values match linux IORESOURCE_IRQ_* defines:
89 * sense == 8: Level, low assertion
90 * sense == 2: Edge, high-to-low change
92 ipic: interrupt-controller@c00 {
93 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
96 #interrupt-cells = <2>;
102 compatible = "fsl,mpc5121-wdt";
106 /* Real time clock */
108 compatible = "fsl,mpc5121-rtc";
110 interrupts = <79 0x8 80 0x8>;
115 compatible = "fsl,mpc5121-reset";
121 compatible = "fsl,mpc5121-clock";
125 /* Power Management Controller */
127 compatible = "fsl,mpc5121-pmc";
128 reg = <0x1000 0x100>;
129 interrupts = <83 0x8>;
133 compatible = "fsl,mpc5121-gpio";
134 reg = <0x1100 0x100>;
135 interrupts = <78 0x8>;
139 compatible = "fsl,mpc5121-mscan";
141 interrupts = <12 0x8>;
145 compatible = "fsl,mpc5121-mscan";
147 interrupts = <13 0x8>;
151 compatible = "fsl,mpc5121-sdhc";
152 reg = <0x1500 0x100>;
153 interrupts = <8 0x8>;
159 #address-cells = <1>;
161 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
163 interrupts = <9 0x8>;
167 #address-cells = <1>;
169 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
171 interrupts = <10 0x8>;
175 #address-cells = <1>;
177 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
179 interrupts = <11 0x8>;
183 compatible = "fsl,mpc5121-i2c-ctrl";
188 compatible = "fsl,mpc5121-axe";
189 reg = <0x2000 0x100>;
190 interrupts = <42 0x8>;
194 compatible = "fsl,mpc5121-diu";
195 reg = <0x2100 0x100>;
196 interrupts = <64 0x8>;
200 compatible = "fsl,mpc5121-mscan";
202 interrupts = <90 0x8>;
206 compatible = "fsl,mpc5121-mscan";
208 interrupts = <91 0x8>;
212 compatible = "fsl,mpc5121-viu";
213 reg = <0x2400 0x400>;
214 interrupts = <67 0x8>;
218 compatible = "fsl,mpc5121-fec-mdio";
219 reg = <0x2800 0x800>;
220 #address-cells = <1>;
224 eth0: ethernet@2800 {
225 device_type = "network";
226 compatible = "fsl,mpc5121-fec";
227 reg = <0x2800 0x800>;
228 local-mac-address = [ 00 00 00 00 00 00 ];
229 interrupts = <4 0x8>;
232 /* USB1 using external ULPI PHY */
234 compatible = "fsl,mpc5121-usb2-dr";
235 reg = <0x3000 0x600>;
236 #address-cells = <1>;
238 interrupts = <43 0x8>;
243 /* USB0 using internal UTMI PHY */
245 compatible = "fsl,mpc5121-usb2-dr";
246 reg = <0x4000 0x600>;
247 #address-cells = <1>;
249 interrupts = <44 0x8>;
251 phy_type = "utmi_wide";
256 compatible = "fsl,mpc5121-ioctl";
257 reg = <0xA000 0x1000>;
260 /* LocalPlus controller */
262 compatible = "fsl,mpc5121-lpc";
263 reg = <0x10000 0x200>;
267 compatible = "fsl,mpc5121-pata";
268 reg = <0x10200 0x100>;
269 interrupts = <5 0x8>;
272 /* 512x PSCs are not 52xx PSC compatible */
276 compatible = "fsl,mpc5121-psc";
277 reg = <0x11000 0x100>;
278 interrupts = <40 0x8>;
279 fsl,rx-fifo-size = <16>;
280 fsl,tx-fifo-size = <16>;
285 compatible = "fsl,mpc5121-psc";
286 reg = <0x11100 0x100>;
287 interrupts = <40 0x8>;
288 fsl,rx-fifo-size = <16>;
289 fsl,tx-fifo-size = <16>;
294 compatible = "fsl,mpc5121-psc";
295 reg = <0x11200 0x100>;
296 interrupts = <40 0x8>;
297 fsl,rx-fifo-size = <16>;
298 fsl,tx-fifo-size = <16>;
303 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
304 reg = <0x11300 0x100>;
305 interrupts = <40 0x8>;
306 fsl,rx-fifo-size = <16>;
307 fsl,tx-fifo-size = <16>;
312 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
313 reg = <0x11400 0x100>;
314 interrupts = <40 0x8>;
315 fsl,rx-fifo-size = <16>;
316 fsl,tx-fifo-size = <16>;
321 compatible = "fsl,mpc5121-psc";
322 reg = <0x11500 0x100>;
323 interrupts = <40 0x8>;
324 fsl,rx-fifo-size = <16>;
325 fsl,tx-fifo-size = <16>;
330 compatible = "fsl,mpc5121-psc";
331 reg = <0x11600 0x100>;
332 interrupts = <40 0x8>;
333 fsl,rx-fifo-size = <16>;
334 fsl,tx-fifo-size = <16>;
339 compatible = "fsl,mpc5121-psc";
340 reg = <0x11700 0x100>;
341 interrupts = <40 0x8>;
342 fsl,rx-fifo-size = <16>;
343 fsl,tx-fifo-size = <16>;
348 compatible = "fsl,mpc5121-psc";
349 reg = <0x11800 0x100>;
350 interrupts = <40 0x8>;
351 fsl,rx-fifo-size = <16>;
352 fsl,tx-fifo-size = <16>;
357 compatible = "fsl,mpc5121-psc";
358 reg = <0x11900 0x100>;
359 interrupts = <40 0x8>;
360 fsl,rx-fifo-size = <16>;
361 fsl,tx-fifo-size = <16>;
366 compatible = "fsl,mpc5121-psc";
367 reg = <0x11a00 0x100>;
368 interrupts = <40 0x8>;
369 fsl,rx-fifo-size = <16>;
370 fsl,tx-fifo-size = <16>;
375 compatible = "fsl,mpc5121-psc";
376 reg = <0x11b00 0x100>;
377 interrupts = <40 0x8>;
378 fsl,rx-fifo-size = <16>;
379 fsl,tx-fifo-size = <16>;
383 compatible = "fsl,mpc5121-psc-fifo";
384 reg = <0x11f00 0x100>;
385 interrupts = <40 0x8>;
389 compatible = "fsl,mpc5121-dma";
390 reg = <0x14000 0x1800>;
391 interrupts = <65 0x8>;
396 compatible = "fsl,mpc5121-pci";
398 interrupts = <1 0x8>;
399 clock-frequency = <0>;
400 #address-cells = <3>;
402 #interrupt-cells = <1>;
404 reg = <0x80008500 0x100 /* internal registers */
405 0x80008300 0x8>; /* config space access registers */
406 bus-range = <0x0 0x0>;
407 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
408 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
409 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;