Pileus Git - ~andy/linux/blob - arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi

   1 /*
   2  * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
   3  *
   4  * Copyright 2011-2012 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 crypto: crypto@300000 {
  36         compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
  37         #address-cells = <1>;
  38         #size-cells = <1>;
  39         reg              = <0x300000 0x10000>;
  40         ranges           = <0 0x300000 0x10000>;
  41         interrupts       = <92 2 0 0>;
  42
  43         sec_jr0: jr@1000 {
  44                 compatible = "fsl,sec-v5.2-job-ring",
  45                              "fsl,sec-v5.0-job-ring",
  46                              "fsl,sec-v4.0-job-ring";
  47                 reg = <0x1000 0x1000>;
  48                 interrupts = <88 2 0 0>;
  49         };
  50
  51         sec_jr1: jr@2000 {
  52                 compatible = "fsl,sec-v5.2-job-ring",
  53                              "fsl,sec-v5.0-job-ring",
  54                              "fsl,sec-v4.0-job-ring";
  55                 reg = <0x2000 0x1000>;
  56                 interrupts = <89 2 0 0>;
  57         };
  58
  59         sec_jr2: jr@3000 {
  60                 compatible = "fsl,sec-v5.2-job-ring",
  61                              "fsl,sec-v5.0-job-ring",
  62                              "fsl,sec-v4.0-job-ring";
  63                 reg = <0x3000 0x1000>;
  64                 interrupts = <90 2 0 0>;
  65         };
  66
  67         sec_jr3: jr@4000 {
  68                 compatible = "fsl,sec-v5.2-job-ring",
  69                              "fsl,sec-v5.0-job-ring",
  70                              "fsl,sec-v4.0-job-ring";
  71                 reg = <0x4000 0x1000>;
  72                 interrupts = <91 2 0 0>;
  73         };
  74
  75         rtic@6000 {
  76                 compatible = "fsl,sec-v5.2-rtic",
  77                              "fsl,sec-v5.0-rtic",
  78                              "fsl,sec-v4.0-rtic";
  79                 #address-cells = <1>;
  80                 #size-cells = <1>;
  81                 reg = <0x6000 0x100>;
  82                 ranges = <0x0 0x6100 0xe00>;
  83
  84                 rtic_a: rtic-a@0 {
  85                         compatible = "fsl,sec-v5.2-rtic-memory",
  86                                      "fsl,sec-v5.0-rtic-memory",
  87                                      "fsl,sec-v4.0-rtic-memory";
  88                         reg = <0x00 0x20 0x100 0x80>;
  89                 };
  90
  91                 rtic_b: rtic-b@20 {
  92                         compatible = "fsl,sec-v5.2-rtic-memory",
  93                                      "fsl,sec-v5.0-rtic-memory",
  94                                      "fsl,sec-v4.0-rtic-memory";
  95                         reg = <0x20 0x20 0x200 0x80>;
  96                 };
  97
  98                 rtic_c: rtic-c@40 {
  99                         compatible = "fsl,sec-v5.2-rtic-memory",
 100                                      "fsl,sec-v5.0-rtic-memory",
 101                                      "fsl,sec-v4.0-rtic-memory";
 102                         reg = <0x40 0x20 0x300 0x80>;
 103                 };
 104
 105                 rtic_d: rtic-d@60 {
 106                         compatible = "fsl,sec-v5.2-rtic-memory",
 107                                      "fsl,sec-v5.0-rtic-memory",
 108                                      "fsl,sec-v4.0-rtic-memory";
 109                         reg = <0x60 0x20 0x500 0x80>;
 110                 };
 111         };
 112 };
 113
 114 sec_mon: sec_mon@314000 {
 115         compatible = "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
 116         reg = <0x314000 0x1000>;
 117         interrupts = <93 2 0 0>;
 118 };