2 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
4 * kernel entry points (interruptions, system call wrappers)
5 * Copyright (C) 1999,2000 Philipp Rumpf
6 * Copyright (C) 1999 SuSE GmbH Nuernberg
7 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
8 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <asm/asm-offsets.h>
27 /* we have the following possibilities to act on an interruption:
28 * - handle in assembly and use shadowed registers only
29 * - save registers to kernel stack and handle in assembly or C */
33 #include <asm/cache.h> /* for L1_CACHE_SHIFT */
34 #include <asm/assembly.h> /* for LDREG/STREG defines */
35 #include <asm/pgtable.h>
36 #include <asm/signal.h>
37 #include <asm/unistd.h>
38 #include <asm/thread_info.h>
40 #include <linux/linkage.h>
48 .import pa_dbit_lock,data
50 /* space_to_prot macro creates a prot id from a space id */
52 #if (SPACEID_SHIFT) == 0
53 .macro space_to_prot spc prot
54 depd,z \spc,62,31,\prot
57 .macro space_to_prot spc prot
58 extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
62 /* Switch to virtual mapping, trashing only %r1 */
65 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
69 or,= %r0,%r1,%r0 /* Only save sr7 in sr3 if sr7 != 0 */
72 load32 KERNEL_PSW, %r1
74 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
77 mtctl %r0, %cr17 /* Clear IIASQ tail */
78 mtctl %r0, %cr17 /* Clear IIASQ head */
81 mtctl %r1, %cr18 /* Set IIAOQ tail */
83 mtctl %r1, %cr18 /* Set IIAOQ head */
90 * The "get_stack" macros are responsible for determining the
94 * Already using a kernel stack, so call the
95 * get_stack_use_r30 macro to push a pt_regs structure
96 * on the stack, and store registers there.
98 * Need to set up a kernel stack, so call the
99 * get_stack_use_cr30 macro to set up a pointer
100 * to the pt_regs structure contained within the
101 * task pointer pointed to by cr30. Set the stack
102 * pointer to point to the end of the task structure.
104 * Note that we use shadowed registers for temps until
105 * we can save %r26 and %r29. %r26 is used to preserve
106 * %r8 (a shadowed register) which temporarily contained
107 * either the fault type ("code") or the eirr. We need
108 * to use a non-shadowed register to carry the value over
109 * the rfir in virt_map. We use %r26 since this value winds
110 * up being passed as the argument to either do_cpu_irq_mask
111 * or handle_interruption. %r29 is used to hold a pointer
112 * the register save area, and once again, it needs to
113 * be a non-shadowed register so that it survives the rfir.
115 * N.B. TASK_SZ_ALGN and PT_SZ_ALGN include space for a stack frame.
118 .macro get_stack_use_cr30
120 /* we save the registers in the task struct */
124 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
126 ldo TASK_REGS(%r9),%r9
127 STREG %r30, PT_GR30(%r9)
128 STREG %r29,PT_GR29(%r9)
129 STREG %r26,PT_GR26(%r9)
132 ldo THREAD_SZ_ALGN(%r1), %r30
135 .macro get_stack_use_r30
137 /* we put a struct pt_regs on the stack and save the registers there */
140 STREG %r30,PT_GR30(%r9)
141 ldo PT_SZ_ALGN(%r30),%r30
142 STREG %r29,PT_GR29(%r9)
143 STREG %r26,PT_GR26(%r9)
148 LDREG PT_GR1(%r29), %r1
149 LDREG PT_GR30(%r29),%r30
150 LDREG PT_GR29(%r29),%r29
153 /* default interruption handler
154 * (calls traps.c:handle_interruption) */
161 /* Interrupt interruption handler
162 * (calls irq.c:do_cpu_irq_mask) */
169 .import os_hpmc, code
173 nop /* must be a NOP, will be patched later */
174 load32 PA(os_hpmc), %r3
177 .word 0 /* checksum (will be patched) */
178 .word PA(os_hpmc) /* address of handler */
179 .word 0 /* length of handler */
183 * Performance Note: Instructions will be moved up into
184 * this part of the code later on, once we are sure
185 * that the tlb miss handlers are close to final form.
188 /* Register definitions for tlb miss handler macros */
190 va = r8 /* virtual address for which the trap occurred */
191 spc = r24 /* space for which the trap occurred */
196 * itlb miss interruption handler (parisc 1.1 - 32 bit)
210 * itlb miss interruption handler (parisc 2.0)
227 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
230 .macro naitlb_11 code
241 * naitlb miss interruption handler (parisc 2.0)
244 .macro naitlb_20 code
259 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
273 * dtlb miss interruption handler (parisc 2.0)
290 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
292 .macro nadtlb_11 code
302 /* nadtlb miss interruption handler (parisc 2.0) */
304 .macro nadtlb_20 code
319 * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
333 * dirty bit trap interruption handler (parisc 2.0)
349 /* In LP64, the space contains part of the upper 32 bits of the
350 * fault. We have to extract this and place it in the va,
351 * zeroing the corresponding bits in the space register */
352 .macro space_adjust spc,va,tmp
354 extrd,u \spc,63,SPACEID_SHIFT,\tmp
355 depd %r0,63,SPACEID_SHIFT,\spc
356 depd \tmp,31,SPACEID_SHIFT,\va
360 .import swapper_pg_dir,code
362 /* Get the pgd. For faults on space zero (kernel space), this
363 * is simply swapper_pg_dir. For user space faults, the
364 * pgd is stored in %cr25 */
365 .macro get_pgd spc,reg
366 ldil L%PA(swapper_pg_dir),\reg
367 ldo R%PA(swapper_pg_dir)(\reg),\reg
368 or,COND(=) %r0,\spc,%r0
373 space_check(spc,tmp,fault)
375 spc - The space we saw the fault with.
376 tmp - The place to store the current space.
377 fault - Function to call on failure.
379 Only allow faults on different spaces from the
380 currently active one if we're the kernel
383 .macro space_check spc,tmp,fault
385 or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page
386 * as kernel, so defeat the space
389 or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */
390 cmpb,COND(<>),n \tmp,\spc,\fault
393 /* Look up a PTE in a 2-Level scheme (faulting at each
394 * level if the entry isn't present
396 * NOTE: we use ldw even for LP64, since the short pointers
397 * can address up to 1TB
399 .macro L2_ptep pmd,pte,index,va,fault
401 extru \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
403 extru \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
405 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
407 ldw,s \index(\pmd),\pmd
408 bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
409 dep %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
411 SHLREG %r9,PxD_VALUE_SHIFT,\pmd
412 extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
413 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
414 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd
415 LDREG %r0(\pmd),\pte /* pmd is now pte */
416 bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
419 /* Look up PTE in a 3-Level scheme.
421 * Here we implement a Hybrid L2/L3 scheme: we allocate the
422 * first pmd adjacent to the pgd. This means that we can
423 * subtract a constant offset to get to it. The pmd and pgd
424 * sizes are arranged so that a single pmd covers 4GB (giving
425 * a full LP64 process access to 8TB) so our lookups are
426 * effectively L2 for the first 4GB of the kernel (i.e. for
427 * all ILP32 processes and all the kernel for machines with
428 * under 4GB of memory) */
429 .macro L3_ptep pgd,pte,index,va,fault
430 #if PT_NLEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
431 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
433 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
434 ldw,s \index(\pgd),\pgd
435 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
436 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
437 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
438 shld \pgd,PxD_VALUE_SHIFT,\index
439 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
441 extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
442 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
444 L2_ptep \pgd,\pte,\index,\va,\fault
447 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
448 * don't needlessly dirty the cache line if it was already set */
449 .macro update_ptep ptep,pte,tmp,tmp1
450 ldi _PAGE_ACCESSED,\tmp1
452 and,COND(<>) \tmp1,\pte,%r0
456 /* Set the dirty bit (and accessed bit). No need to be
457 * clever, this is only used from the dirty fault */
458 .macro update_dirty ptep,pte,tmp
459 ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
464 /* bitshift difference between a PFN (based on kernel's PAGE_SIZE)
465 * to a CPU TLB 4k PFN (4k => 12 bits to shift) */
466 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
468 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
469 .macro convert_for_tlb_insert20 pte
470 extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
471 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
472 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
473 (63-58)+PAGE_ADD_SHIFT,\pte
476 /* Convert the pte and prot to tlb insertion values. How
477 * this happens is quite subtle, read below */
478 .macro make_insert_tlb spc,pte,prot
479 space_to_prot \spc \prot /* create prot id from space */
480 /* The following is the real subtlety. This is depositing
481 * T <-> _PAGE_REFTRAP
483 * B <-> _PAGE_DMB (memory break)
485 * Then incredible subtlety: The access rights are
486 * _PAGE_GATEWAY _PAGE_EXEC _PAGE_READ
487 * See 3-14 of the parisc 2.0 manual
489 * Finally, _PAGE_READ goes in the top bit of PL1 (so we
490 * trigger an access rights trap in user space if the user
491 * tries to read an unreadable page */
494 /* PAGE_USER indicates the page can be read with user privileges,
495 * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
496 * contains _PAGE_READ */
497 extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
499 /* If we're a gateway page, drop PL2 back to zero for promotion
500 * to kernel privilege (so we can execute the page as kernel).
501 * Any privilege promotion page always denys read and write */
502 extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
503 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
505 /* Enforce uncacheable pages.
506 * This should ONLY be use for MMIO on PA 2.0 machines.
507 * Memory/DMA is cache coherent on all PA2.0 machines we support
508 * (that means T-class is NOT supported) and the memory controllers
509 * on most of those machines only handles cache transactions.
511 extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
514 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
515 convert_for_tlb_insert20 \pte
518 /* Identical macro to make_insert_tlb above, except it
519 * makes the tlb entry for the differently formatted pa11
520 * insertion instructions */
521 .macro make_insert_tlb_11 spc,pte,prot
522 zdep \spc,30,15,\prot
524 extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
526 extru,= \pte,_PAGE_USER_BIT,1,%r0
527 depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
528 extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
529 depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
531 /* Get rid of prot bits and convert to page addr for iitlba */
533 depi 0,31,ASM_PFN_PTE_SHIFT,\pte
534 SHRREG \pte,(ASM_PFN_PTE_SHIFT-(31-26)),\pte
537 /* This is for ILP32 PA2.0 only. The TLB insertion needs
538 * to extend into I/O space if the address is 0xfXXXXXXX
539 * so we extend the f's into the top word of the pte in
541 .macro f_extend pte,tmp
542 extrd,s \pte,42,4,\tmp
544 extrd,s \pte,63,25,\pte
547 /* The alias region is an 8MB aligned 16MB to do clear and
548 * copy user pages at addresses congruent with the user
551 * To use the alias page, you set %r26 up with the to TLB
552 * entry (identifying the physical page) and %r23 up with
553 * the from tlb entry (or nothing if only a to entry---for
554 * clear_user_page_asm) */
555 .macro do_alias spc,tmp,tmp1,va,pte,prot,fault,patype
556 cmpib,COND(<>),n 0,\spc,\fault
557 ldil L%(TMPALIAS_MAP_START),\tmp
558 #if defined(CONFIG_64BIT) && (TMPALIAS_MAP_START >= 0x80000000)
559 /* on LP64, ldi will sign extend into the upper 32 bits,
560 * which is behaviour we don't want */
565 cmpb,COND(<>),n \tmp,\tmp1,\fault
566 mfctl %cr19,\tmp /* iir */
567 /* get the opcode (first six bits) into \tmp */
568 extrw,u \tmp,5,6,\tmp
570 * Only setting the T bit prevents data cache movein
571 * Setting access rights to zero prevents instruction cache movein
573 * Note subtlety here: _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE go
574 * to type field and _PAGE_READ goes to top bit of PL1
576 ldi (_PAGE_REFTRAP|_PAGE_READ|_PAGE_WRITE),\prot
578 * so if the opcode is one (i.e. this is a memory management
579 * instruction) nullify the next load so \prot is only T.
580 * Otherwise this is a normal data operation
582 cmpiclr,= 0x01,\tmp,%r0
583 ldi (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot
585 depd,z \prot,8,7,\prot
588 depw,z \prot,8,7,\prot
590 .error "undefined PA type to do_alias"
594 * OK, it is in the temp alias region, check whether "from" or "to".
595 * Check "subtle" note in pacache.S re: r23/r26.
598 extrd,u,*= \va,41,1,%r0
600 extrw,u,= \va,9,1,%r0
602 or,COND(tr) %r23,%r0,\pte
608 * Align fault_vector_20 on 4K boundary so that both
609 * fault_vector_11 and fault_vector_20 are on the
610 * same page. This is only necessary as long as we
611 * write protect the kernel text, which we may stop
612 * doing once we use large page translations to cover
613 * the static part of the kernel address space.
620 ENTRY(fault_vector_20)
621 /* First vector is invalid (0) */
622 .ascii "cows can fly"
663 ENTRY(fault_vector_11)
664 /* First vector is invalid (0) */
665 .ascii "cows can fly"
703 /* Fault vector is separately protected and *must* be on its own page */
705 ENTRY(end_fault_vector)
707 .import handle_interruption,code
708 .import do_cpu_irq_mask,code
713 * copy_thread moved args into task save area.
716 ENTRY(ret_from_kernel_thread)
718 /* Call schedule_tail first though */
719 BL schedule_tail, %r2
722 LDREG TI_TASK-THREAD_SZ_ALGN(%r30), %r1
723 LDREG TASK_PT_GR25(%r1), %r26
725 LDREG TASK_PT_GR27(%r1), %r27
727 LDREG TASK_PT_GR26(%r1), %r1
732 ldo -16(%r30),%r29 /* Reference param save area */
733 loadgp /* Thread could have been in a module */
742 ENDPROC(ret_from_kernel_thread)
744 ENTRY(ret_from_kernel_execve)
746 ldo THREAD_SZ_ALGN(%r1), %r30
747 b intr_return /* forward */
748 copy %r26,%r16 /* pt_regs into r16 */
749 ENDPROC(ret_from_kernel_execve)
753 * struct task_struct *_switch_to(struct task_struct *prev,
754 * struct task_struct *next)
756 * switch kernel stacks and return prev */
758 STREG %r2, -RP_OFFSET(%r30)
763 load32 _switch_to_ret, %r2
765 STREG %r2, TASK_PT_KPC(%r26)
766 LDREG TASK_PT_KPC(%r25), %r2
768 STREG %r30, TASK_PT_KSP(%r26)
769 LDREG TASK_PT_KSP(%r25), %r30
770 LDREG TASK_THREAD_INFO(%r25), %r25
775 mtctl %r0, %cr0 /* Needed for single stepping */
779 LDREG -RP_OFFSET(%r30), %r2
785 * Common rfi return path for interruptions, kernel execve, and
786 * sys_rt_sigreturn (sometimes). The sys_rt_sigreturn syscall will
787 * return via this path if the signal was received when the process
788 * was running; if the process was blocked on a syscall then the
789 * normal syscall_exit path is used. All syscalls for traced
790 * proceses exit via intr_restore.
792 * XXX If any syscalls that change a processes space id ever exit
793 * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
800 ENTRY(syscall_exit_rfi)
802 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
803 ldo TASK_REGS(%r16),%r16
804 /* Force iaoq to userspace, as the user has had access to our current
805 * context via sigcontext. Also Filter the PSW for the same reason.
807 LDREG PT_IAOQ0(%r16),%r19
809 STREG %r19,PT_IAOQ0(%r16)
810 LDREG PT_IAOQ1(%r16),%r19
812 STREG %r19,PT_IAOQ1(%r16)
813 LDREG PT_PSW(%r16),%r19
814 load32 USER_PSW_MASK,%r1
816 load32 USER_PSW_HI_MASK,%r20
819 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
821 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
822 STREG %r19,PT_PSW(%r16)
825 * If we aren't being traced, we never saved space registers
826 * (we don't store them in the sigcontext), so set them
827 * to "proper" values now (otherwise we'll wind up restoring
828 * whatever was last stored in the task structure, which might
829 * be inconsistent if an interrupt occurred while on the gateway
830 * page). Note that we may be "trashing" values the user put in
831 * them, but we don't support the user changing them.
834 STREG %r0,PT_SR2(%r16)
836 STREG %r19,PT_SR0(%r16)
837 STREG %r19,PT_SR1(%r16)
838 STREG %r19,PT_SR3(%r16)
839 STREG %r19,PT_SR4(%r16)
840 STREG %r19,PT_SR5(%r16)
841 STREG %r19,PT_SR6(%r16)
842 STREG %r19,PT_SR7(%r16)
845 /* NOTE: Need to enable interrupts incase we schedule. */
850 /* check for reschedule */
852 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
853 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
855 .import do_notify_resume,code
859 LDREG TI_FLAGS(%r1),%r19
860 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r20
861 and,COND(<>) %r19, %r20, %r0
862 b,n intr_restore /* skip past if we've nothing to do */
864 /* This check is critical to having LWS
865 * working. The IASQ is zero on the gateway
866 * page and we cannot deliver any signals until
867 * we get off the gateway page.
869 * Only do signals if we are returning to user space
871 LDREG PT_IASQ0(%r16), %r20
872 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
873 LDREG PT_IASQ1(%r16), %r20
874 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
876 copy %r0, %r25 /* long in_syscall = 0 */
878 ldo -16(%r30),%r29 /* Reference param save area */
881 BL do_notify_resume,%r2
882 copy %r16, %r26 /* struct pt_regs *regs */
888 ldo PT_FR31(%r29),%r1
892 /* inverse of virt_map */
894 rsm PSW_SM_QUIET,%r0 /* prepare for rfi */
897 /* Restore space id's and special cr's from PT_REGS
898 * structure pointed to by r29
902 /* IMPORTANT: rest_stack restores r29 last (we are using it)!
903 * It also restores r1 and r30.
910 #ifndef CONFIG_PREEMPT
911 # define intr_do_preempt intr_restore
912 #endif /* !CONFIG_PREEMPT */
914 .import schedule,code
916 /* Only call schedule on return to userspace. If we're returning
917 * to kernel space, we may schedule if CONFIG_PREEMPT, otherwise
918 * we jump back to intr_restore.
920 LDREG PT_IASQ0(%r16), %r20
921 cmpib,COND(=) 0, %r20, intr_do_preempt
923 LDREG PT_IASQ1(%r16), %r20
924 cmpib,COND(=) 0, %r20, intr_do_preempt
928 ldo -16(%r30),%r29 /* Reference param save area */
931 ldil L%intr_check_sig, %r2
935 load32 schedule, %r20
938 ldo R%intr_check_sig(%r2), %r2
940 /* preempt the current task on returning to kernel
941 * mode from an interrupt, iff need_resched is set,
942 * and preempt_count is 0. otherwise, we continue on
943 * our merry way back to the current running task.
945 #ifdef CONFIG_PREEMPT
946 .import preempt_schedule_irq,code
948 rsm PSW_SM_I, %r0 /* disable interrupts */
950 /* current_thread_info()->preempt_count */
952 LDREG TI_PRE_COUNT(%r1), %r19
953 cmpib,COND(<>) 0, %r19, intr_restore /* if preempt_count > 0 */
954 nop /* prev insn branched backwards */
956 /* check if we interrupted a critical path */
957 LDREG PT_PSW(%r16), %r20
958 bb,<,n %r20, 31 - PSW_SM_I, intr_restore
961 BL preempt_schedule_irq, %r2
964 b,n intr_restore /* ssm PSW_SM_I done by intr_restore */
965 #endif /* CONFIG_PREEMPT */
968 * External interrupts.
972 cmpib,COND(=),n 0,%r16,1f
984 ldo PT_FR0(%r29), %r24
989 copy %r29, %r26 /* arg0 is pt_regs */
990 copy %r29, %r16 /* save pt_regs */
992 ldil L%intr_return, %r2
995 ldo -16(%r30),%r29 /* Reference param save area */
999 ldo R%intr_return(%r2), %r2 /* return to intr_return, not here */
1000 ENDPROC(syscall_exit_rfi)
1003 /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
1005 ENTRY(intr_save) /* for os_hpmc */
1007 cmpib,COND(=),n 0,%r16,1f
1019 /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
1022 * FIXME: 1) Use a #define for the hardwired "6" below (and in
1024 * 2) Once we start executing code above 4 Gb, we need
1025 * to adjust iasq/iaoq here in the same way we
1026 * adjust isr/ior below.
1029 cmpib,COND(=),n 6,%r26,skip_save_ior
1032 mfctl %cr20, %r16 /* isr */
1033 nop /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
1034 mfctl %cr21, %r17 /* ior */
1039 * If the interrupted code was running with W bit off (32 bit),
1040 * clear the b bits (bits 0 & 1) in the ior.
1041 * save_specials left ipsw value in r8 for us to test.
1043 extrd,u,*<> %r8,PSW_W_BIT,1,%r0
1047 * FIXME: This code has hardwired assumptions about the split
1048 * between space bits and offset bits. This will change
1049 * when we allow alternate page sizes.
1052 /* adjust isr/ior. */
1053 extrd,u %r16,63,SPACEID_SHIFT,%r1 /* get high bits from isr for ior */
1054 depd %r1,31,SPACEID_SHIFT,%r17 /* deposit them into ior */
1055 depdi 0,63,SPACEID_SHIFT,%r16 /* clear them from isr */
1057 STREG %r16, PT_ISR(%r29)
1058 STREG %r17, PT_IOR(%r29)
1065 ldo PT_FR0(%r29), %r25
1070 copy %r29, %r25 /* arg1 is pt_regs */
1072 ldo -16(%r30),%r29 /* Reference param save area */
1075 ldil L%intr_check_sig, %r2
1076 copy %r25, %r16 /* save pt_regs */
1078 b handle_interruption
1079 ldo R%intr_check_sig(%r2), %r2
1084 * Note for all tlb miss handlers:
1086 * cr24 contains a pointer to the kernel address space
1089 * cr25 contains a pointer to the current user address
1090 * space page directory.
1092 * sr3 will contain the space id of the user address space
1093 * of the current running thread while that thread is
1094 * running in the kernel.
1098 * register number allocations. Note that these are all
1099 * in the shadowed registers
1102 t0 = r1 /* temporary register 0 */
1103 va = r8 /* virtual address for which the trap occurred */
1104 t1 = r9 /* temporary register 1 */
1105 pte = r16 /* pte/phys page # */
1106 prot = r17 /* prot bits */
1107 spc = r24 /* space for which the trap occurred */
1108 ptp = r25 /* page directory/page table pointer */
1113 space_adjust spc,va,t0
1115 space_check spc,t0,dtlb_fault
1117 L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
1119 update_ptep ptp,pte,t0,t1
1121 make_insert_tlb spc,pte,prot
1128 dtlb_check_alias_20w:
1129 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1137 space_adjust spc,va,t0
1139 space_check spc,t0,nadtlb_fault
1141 L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w
1143 update_ptep ptp,pte,t0,t1
1145 make_insert_tlb spc,pte,prot
1152 nadtlb_check_alias_20w:
1153 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1165 space_check spc,t0,dtlb_fault
1167 L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
1169 update_ptep ptp,pte,t0,t1
1171 make_insert_tlb_11 spc,pte,prot
1173 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1176 idtlba pte,(%sr1,va)
1177 idtlbp prot,(%sr1,va)
1179 mtsp t0, %sr1 /* Restore sr1 */
1184 dtlb_check_alias_11:
1185 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,11
1196 space_check spc,t0,nadtlb_fault
1198 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11
1200 update_ptep ptp,pte,t0,t1
1202 make_insert_tlb_11 spc,pte,prot
1205 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1208 idtlba pte,(%sr1,va)
1209 idtlbp prot,(%sr1,va)
1211 mtsp t0, %sr1 /* Restore sr1 */
1216 nadtlb_check_alias_11:
1217 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,11
1226 space_adjust spc,va,t0
1228 space_check spc,t0,dtlb_fault
1230 L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
1232 update_ptep ptp,pte,t0,t1
1234 make_insert_tlb spc,pte,prot
1243 dtlb_check_alias_20:
1244 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1254 space_check spc,t0,nadtlb_fault
1256 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20
1258 update_ptep ptp,pte,t0,t1
1260 make_insert_tlb spc,pte,prot
1269 nadtlb_check_alias_20:
1270 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1282 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1283 * probei instructions. We don't want to fault for these
1284 * instructions (not only does it not make sense, it can cause
1285 * deadlocks, since some flushes are done with the mmap
1286 * semaphore held). If the translation doesn't exist, we can't
1287 * insert a translation, so have to emulate the side effects
1288 * of the instruction. Since we don't insert a translation
1289 * we can get a lot of faults during a flush loop, so it makes
1290 * sense to try to do it here with minimum overhead. We only
1291 * emulate fdc,fic,pdc,probew,prober instructions whose base
1292 * and index registers are not shadowed. We defer everything
1293 * else to the "slow" path.
1296 mfctl %cr19,%r9 /* Get iir */
1298 /* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.
1299 Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1301 /* Checks for fdc,fdce,pdc,"fic,4f" only */
1304 cmpb,<>,n %r16,%r17,nadtlb_probe_check
1305 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
1306 BL get_register,%r25
1307 extrw,u %r9,15,5,%r8 /* Get index register # */
1308 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1310 BL get_register,%r25
1311 extrw,u %r9,10,5,%r8 /* Get base register # */
1312 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1313 BL set_register,%r25
1314 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1319 or %r8,%r9,%r8 /* Set PSW_N */
1326 When there is no translation for the probe address then we
1327 must nullify the insn and return zero in the target regsiter.
1328 This will indicate to the calling code that it does not have
1329 write/read privileges to this address.
1331 This should technically work for prober and probew in PA 1.1,
1332 and also probe,r and probe,w in PA 2.0
1334 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1335 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1341 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1342 BL get_register,%r25 /* Find the target register */
1343 extrw,u %r9,31,5,%r8 /* Get target register */
1344 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1345 BL set_register,%r25
1346 copy %r0,%r1 /* Write zero to target register */
1347 b nadtlb_nullify /* Nullify return insn */
1355 * I miss is a little different, since we allow users to fault
1356 * on the gateway page which is in the kernel address space.
1359 space_adjust spc,va,t0
1361 space_check spc,t0,itlb_fault
1363 L3_ptep ptp,pte,t0,va,itlb_fault
1365 update_ptep ptp,pte,t0,t1
1367 make_insert_tlb spc,pte,prot
1377 * I miss is a little different, since we allow users to fault
1378 * on the gateway page which is in the kernel address space.
1381 space_adjust spc,va,t0
1383 space_check spc,t0,naitlb_fault
1385 L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w
1387 update_ptep ptp,pte,t0,t1
1389 make_insert_tlb spc,pte,prot
1396 naitlb_check_alias_20w:
1397 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1409 space_check spc,t0,itlb_fault
1411 L2_ptep ptp,pte,t0,va,itlb_fault
1413 update_ptep ptp,pte,t0,t1
1415 make_insert_tlb_11 spc,pte,prot
1417 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1420 iitlba pte,(%sr1,va)
1421 iitlbp prot,(%sr1,va)
1423 mtsp t0, %sr1 /* Restore sr1 */
1431 space_check spc,t0,naitlb_fault
1433 L2_ptep ptp,pte,t0,va,naitlb_check_alias_11
1435 update_ptep ptp,pte,t0,t1
1437 make_insert_tlb_11 spc,pte,prot
1439 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1442 iitlba pte,(%sr1,va)
1443 iitlbp prot,(%sr1,va)
1445 mtsp t0, %sr1 /* Restore sr1 */
1450 naitlb_check_alias_11:
1451 do_alias spc,t0,t1,va,pte,prot,itlb_fault,11
1453 iitlba pte,(%sr0, va)
1454 iitlbp prot,(%sr0, va)
1463 space_check spc,t0,itlb_fault
1465 L2_ptep ptp,pte,t0,va,itlb_fault
1467 update_ptep ptp,pte,t0,t1
1469 make_insert_tlb spc,pte,prot
1481 space_check spc,t0,naitlb_fault
1483 L2_ptep ptp,pte,t0,va,naitlb_check_alias_20
1485 update_ptep ptp,pte,t0,t1
1487 make_insert_tlb spc,pte,prot
1496 naitlb_check_alias_20:
1497 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1509 space_adjust spc,va,t0
1511 space_check spc,t0,dbit_fault
1513 L3_ptep ptp,pte,t0,va,dbit_fault
1516 cmpib,COND(=),n 0,spc,dbit_nolock_20w
1517 load32 PA(pa_dbit_lock),t0
1521 cmpib,COND(=) 0,t1,dbit_spin_20w
1526 update_dirty ptp,pte,t1
1528 make_insert_tlb spc,pte,prot
1532 cmpib,COND(=),n 0,spc,dbit_nounlock_20w
1547 space_check spc,t0,dbit_fault
1549 L2_ptep ptp,pte,t0,va,dbit_fault
1552 cmpib,COND(=),n 0,spc,dbit_nolock_11
1553 load32 PA(pa_dbit_lock),t0
1557 cmpib,= 0,t1,dbit_spin_11
1562 update_dirty ptp,pte,t1
1564 make_insert_tlb_11 spc,pte,prot
1566 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1569 idtlba pte,(%sr1,va)
1570 idtlbp prot,(%sr1,va)
1572 mtsp t1, %sr1 /* Restore sr1 */
1574 cmpib,COND(=),n 0,spc,dbit_nounlock_11
1587 space_check spc,t0,dbit_fault
1589 L2_ptep ptp,pte,t0,va,dbit_fault
1592 cmpib,COND(=),n 0,spc,dbit_nolock_20
1593 load32 PA(pa_dbit_lock),t0
1597 cmpib,= 0,t1,dbit_spin_20
1602 update_dirty ptp,pte,t1
1604 make_insert_tlb spc,pte,prot
1611 cmpib,COND(=),n 0,spc,dbit_nounlock_20
1622 .import handle_interruption,code
1626 ldi 31,%r8 /* Use an unused code */
1648 /* Register saving semantics for system calls:
1650 %r1 clobbered by system call macro in userspace
1651 %r2 saved in PT_REGS by gateway page
1652 %r3 - %r18 preserved by C code (saved by signal code)
1653 %r19 - %r20 saved in PT_REGS by gateway page
1654 %r21 - %r22 non-standard syscall args
1655 stored in kernel stack by gateway page
1656 %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
1657 %r27 - %r30 saved in PT_REGS by gateway page
1658 %r31 syscall return pointer
1661 /* Floating point registers (FIXME: what do we do with these?)
1663 %fr0 - %fr3 status/exception, not preserved
1664 %fr4 - %fr7 arguments
1665 %fr8 - %fr11 not preserved by C code
1666 %fr12 - %fr21 preserved by C code
1667 %fr22 - %fr31 not preserved by C code
1670 .macro reg_save regs
1671 STREG %r3, PT_GR3(\regs)
1672 STREG %r4, PT_GR4(\regs)
1673 STREG %r5, PT_GR5(\regs)
1674 STREG %r6, PT_GR6(\regs)
1675 STREG %r7, PT_GR7(\regs)
1676 STREG %r8, PT_GR8(\regs)
1677 STREG %r9, PT_GR9(\regs)
1678 STREG %r10,PT_GR10(\regs)
1679 STREG %r11,PT_GR11(\regs)
1680 STREG %r12,PT_GR12(\regs)
1681 STREG %r13,PT_GR13(\regs)
1682 STREG %r14,PT_GR14(\regs)
1683 STREG %r15,PT_GR15(\regs)
1684 STREG %r16,PT_GR16(\regs)
1685 STREG %r17,PT_GR17(\regs)
1686 STREG %r18,PT_GR18(\regs)
1689 .macro reg_restore regs
1690 LDREG PT_GR3(\regs), %r3
1691 LDREG PT_GR4(\regs), %r4
1692 LDREG PT_GR5(\regs), %r5
1693 LDREG PT_GR6(\regs), %r6
1694 LDREG PT_GR7(\regs), %r7
1695 LDREG PT_GR8(\regs), %r8
1696 LDREG PT_GR9(\regs), %r9
1697 LDREG PT_GR10(\regs),%r10
1698 LDREG PT_GR11(\regs),%r11
1699 LDREG PT_GR12(\regs),%r12
1700 LDREG PT_GR13(\regs),%r13
1701 LDREG PT_GR14(\regs),%r14
1702 LDREG PT_GR15(\regs),%r15
1703 LDREG PT_GR16(\regs),%r16
1704 LDREG PT_GR17(\regs),%r17
1705 LDREG PT_GR18(\regs),%r18
1708 ENTRY(sys_fork_wrapper)
1709 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1710 ldo TASK_REGS(%r1),%r1
1713 STREG %r3, PT_CR27(%r1)
1715 STREG %r2,-RP_OFFSET(%r30)
1716 ldo FRAME_SIZE(%r30),%r30
1718 ldo -16(%r30),%r29 /* Reference param save area */
1721 /* These are call-clobbered registers and therefore
1722 also syscall-clobbered (we hope). */
1723 STREG %r2,PT_GR19(%r1) /* save for child */
1724 STREG %r30,PT_GR21(%r1)
1726 LDREG PT_GR30(%r1),%r25
1731 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1733 ldo -FRAME_SIZE(%r30),%r30 /* get the stackframe */
1734 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1735 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1737 LDREG PT_CR27(%r1), %r3
1741 /* strace expects syscall # to be preserved in r20 */
1744 STREG %r20,PT_GR20(%r1)
1745 ENDPROC(sys_fork_wrapper)
1747 /* Set the return value for the child */
1749 BL schedule_tail, %r2
1752 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE-FRAME_SIZE(%r30), %r1
1753 LDREG TASK_PT_GR19(%r1),%r2
1756 ENDPROC(child_return)
1759 ENTRY(sys_clone_wrapper)
1760 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1761 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1764 STREG %r3, PT_CR27(%r1)
1766 STREG %r2,-RP_OFFSET(%r30)
1767 ldo FRAME_SIZE(%r30),%r30
1769 ldo -16(%r30),%r29 /* Reference param save area */
1772 /* WARNING - Clobbers r19 and r21, userspace must save these! */
1773 STREG %r2,PT_GR19(%r1) /* save for child */
1774 STREG %r30,PT_GR21(%r1)
1779 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1780 ENDPROC(sys_clone_wrapper)
1783 ENTRY(sys_vfork_wrapper)
1784 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1785 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1788 STREG %r3, PT_CR27(%r1)
1790 STREG %r2,-RP_OFFSET(%r30)
1791 ldo FRAME_SIZE(%r30),%r30
1793 ldo -16(%r30),%r29 /* Reference param save area */
1796 STREG %r2,PT_GR19(%r1) /* save for child */
1797 STREG %r30,PT_GR21(%r1)
1803 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1804 ENDPROC(sys_vfork_wrapper)
1807 ENTRY(sys_rt_sigreturn_wrapper)
1808 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1809 ldo TASK_REGS(%r26),%r26 /* get pt regs */
1810 /* Don't save regs, we are going to restore them from sigcontext. */
1811 STREG %r2, -RP_OFFSET(%r30)
1813 ldo FRAME_SIZE(%r30), %r30
1814 BL sys_rt_sigreturn,%r2
1815 ldo -16(%r30),%r29 /* Reference param save area */
1817 BL sys_rt_sigreturn,%r2
1818 ldo FRAME_SIZE(%r30), %r30
1821 ldo -FRAME_SIZE(%r30), %r30
1822 LDREG -RP_OFFSET(%r30), %r2
1824 /* FIXME: I think we need to restore a few more things here. */
1825 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1826 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1829 /* If the signal was received while the process was blocked on a
1830 * syscall, then r2 will take us to syscall_exit; otherwise r2 will
1831 * take us to syscall_exit_rfi and on to intr_return.
1834 LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
1835 ENDPROC(sys_rt_sigreturn_wrapper)
1837 ENTRY(sys_sigaltstack_wrapper)
1838 /* Get the user stack pointer */
1839 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1840 ldo TASK_REGS(%r1),%r24 /* get pt regs */
1841 LDREG TASK_PT_GR30(%r24),%r24
1842 STREG %r2, -RP_OFFSET(%r30)
1844 ldo FRAME_SIZE(%r30), %r30
1845 BL do_sigaltstack,%r2
1846 ldo -16(%r30),%r29 /* Reference param save area */
1848 BL do_sigaltstack,%r2
1849 ldo FRAME_SIZE(%r30), %r30
1852 ldo -FRAME_SIZE(%r30), %r30
1853 LDREG -RP_OFFSET(%r30), %r2
1856 ENDPROC(sys_sigaltstack_wrapper)
1859 ENTRY(sys32_sigaltstack_wrapper)
1860 /* Get the user stack pointer */
1861 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r24
1862 LDREG TASK_PT_GR30(%r24),%r24
1863 STREG %r2, -RP_OFFSET(%r30)
1864 ldo FRAME_SIZE(%r30), %r30
1865 BL do_sigaltstack32,%r2
1866 ldo -16(%r30),%r29 /* Reference param save area */
1868 ldo -FRAME_SIZE(%r30), %r30
1869 LDREG -RP_OFFSET(%r30), %r2
1872 ENDPROC(sys32_sigaltstack_wrapper)
1876 /* NOTE: HP-UX syscalls also come through here
1877 * after hpux_syscall_exit fixes up return
1880 /* NOTE: Not all syscalls exit this way. rt_sigreturn will exit
1881 * via syscall_exit_rfi if the signal was received while the process
1885 /* save return value now */
1888 LDREG TI_TASK(%r1),%r1
1889 STREG %r28,TASK_PT_GR28(%r1)
1892 /* <linux/personality.h> cannot be easily included */
1893 #define PER_HPUX 0x10
1894 ldw TASK_PERSONALITY(%r1),%r19
1896 /* We can't use "CMPIB<> PER_HPUX" since "im5" field is sign extended */
1897 ldo -PER_HPUX(%r19), %r19
1898 cmpib,COND(<>),n 0,%r19,1f
1900 /* Save other hpux returns if personality is PER_HPUX */
1901 STREG %r22,TASK_PT_GR22(%r1)
1902 STREG %r29,TASK_PT_GR29(%r1)
1905 #endif /* CONFIG_HPUX */
1907 /* Seems to me that dp could be wrong here, if the syscall involved
1908 * calling a module, and nothing got round to restoring dp on return.
1912 syscall_check_resched:
1914 /* check for reschedule */
1916 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
1917 bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
1919 .import do_signal,code
1921 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
1922 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r26
1923 and,COND(<>) %r19, %r26, %r0
1924 b,n syscall_restore /* skip past if we've nothing to do */
1927 /* Save callee-save registers (for sigcontext).
1928 * FIXME: After this point the process structure should be
1929 * consistent with all the relevant state of the process
1930 * before the syscall. We need to verify this.
1932 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1933 ldo TASK_REGS(%r1), %r26 /* struct pt_regs *regs */
1937 ldo -16(%r30),%r29 /* Reference param save area */
1940 BL do_notify_resume,%r2
1941 ldi 1, %r25 /* long in_syscall = 1 */
1943 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1944 ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
1947 b,n syscall_check_sig
1950 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1952 /* Are we being ptraced? */
1953 ldw TASK_FLAGS(%r1),%r19
1954 ldi (_TIF_SINGLESTEP|_TIF_BLOCKSTEP),%r2
1955 and,COND(=) %r19,%r2,%r0
1956 b,n syscall_restore_rfi
1958 ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
1961 LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
1964 LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
1965 LDREG TASK_PT_GR19(%r1),%r19
1966 LDREG TASK_PT_GR20(%r1),%r20
1967 LDREG TASK_PT_GR21(%r1),%r21
1968 LDREG TASK_PT_GR22(%r1),%r22
1969 LDREG TASK_PT_GR23(%r1),%r23
1970 LDREG TASK_PT_GR24(%r1),%r24
1971 LDREG TASK_PT_GR25(%r1),%r25
1972 LDREG TASK_PT_GR26(%r1),%r26
1973 LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
1974 LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
1975 LDREG TASK_PT_GR29(%r1),%r29
1976 LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
1978 /* NOTE: We use rsm/ssm pair to make this operation atomic */
1979 LDREG TASK_PT_GR30(%r1),%r1 /* Get user sp */
1981 copy %r1,%r30 /* Restore user sp */
1982 mfsp %sr3,%r1 /* Get user space id */
1983 mtsp %r1,%sr7 /* Restore sr7 */
1986 /* Set sr2 to zero for userspace syscalls to work. */
1988 mtsp %r1,%sr4 /* Restore sr4 */
1989 mtsp %r1,%sr5 /* Restore sr5 */
1990 mtsp %r1,%sr6 /* Restore sr6 */
1992 depi 3,31,2,%r31 /* ensure return to user mode. */
1995 /* decide whether to reset the wide mode bit
1997 * For a syscall, the W bit is stored in the lowest bit
1998 * of sp. Extract it and reset W if it is zero */
1999 extrd,u,*<> %r30,63,1,%r1
2001 /* now reset the lowest bit of sp if it was set */
2004 be,n 0(%sr3,%r31) /* return to user space */
2006 /* We have to return via an RFI, so that PSW T and R bits can be set
2008 * This sets up pt_regs so we can return via intr_restore, which is not
2009 * the most efficient way of doing things, but it works.
2011 syscall_restore_rfi:
2012 ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
2013 mtctl %r2,%cr0 /* for immediate trap */
2014 LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
2015 ldi 0x0b,%r20 /* Create new PSW */
2016 depi -1,13,1,%r20 /* C, Q, D, and I bits */
2018 /* The values of SINGLESTEP_BIT and BLOCKSTEP_BIT are
2019 * set in thread_info.h and converted to PA bitmap
2020 * numbers in asm-offsets.c */
2022 /* if ((%r19.SINGLESTEP_BIT)) { %r20.27=1} */
2023 extru,= %r19,TIF_SINGLESTEP_PA_BIT,1,%r0
2024 depi -1,27,1,%r20 /* R bit */
2026 /* if ((%r19.BLOCKSTEP_BIT)) { %r20.7=1} */
2027 extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,%r0
2028 depi -1,7,1,%r20 /* T bit */
2030 STREG %r20,TASK_PT_PSW(%r1)
2032 /* Always store space registers, since sr3 can be changed (e.g. fork) */
2035 STREG %r25,TASK_PT_SR3(%r1)
2036 STREG %r25,TASK_PT_SR4(%r1)
2037 STREG %r25,TASK_PT_SR5(%r1)
2038 STREG %r25,TASK_PT_SR6(%r1)
2039 STREG %r25,TASK_PT_SR7(%r1)
2040 STREG %r25,TASK_PT_IASQ0(%r1)
2041 STREG %r25,TASK_PT_IASQ1(%r1)
2044 /* Now if old D bit is clear, it means we didn't save all registers
2045 * on syscall entry, so do that now. This only happens on TRACEME
2046 * calls, or if someone attached to us while we were on a syscall.
2047 * We could make this more efficient by not saving r3-r18, but
2048 * then we wouldn't be able to use the common intr_restore path.
2049 * It is only for traced processes anyway, so performance is not
2052 bb,< %r2,30,pt_regs_ok /* Branch if D set */
2053 ldo TASK_REGS(%r1),%r25
2054 reg_save %r25 /* Save r3 to r18 */
2056 /* Save the current sr */
2058 STREG %r2,TASK_PT_SR0(%r1)
2060 /* Save the scratch sr */
2062 STREG %r2,TASK_PT_SR1(%r1)
2064 /* sr2 should be set to zero for userspace syscalls */
2065 STREG %r0,TASK_PT_SR2(%r1)
2068 LDREG TASK_PT_GR31(%r1),%r2
2069 depi 3,31,2,%r2 /* ensure return to user mode. */
2070 STREG %r2,TASK_PT_IAOQ0(%r1)
2072 STREG %r2,TASK_PT_IAOQ1(%r1)
2077 .import schedule,code
2081 ldo -16(%r30),%r29 /* Reference param save area */
2085 b syscall_check_resched /* if resched, we start over again */
2087 ENDPROC(syscall_exit)
2090 #ifdef CONFIG_FUNCTION_TRACER
2091 .import ftrace_function_trampoline,code
2094 b ftrace_function_trampoline
2098 ENTRY(return_to_handler)
2099 load32 return_trampoline, %rp
2102 b ftrace_return_to_handler
2113 ENDPROC(return_to_handler)
2114 #endif /* CONFIG_FUNCTION_TRACER */
2119 * get_register is used by the non access tlb miss handlers to
2120 * copy the value of the general register specified in r8 into
2121 * r1. This routine can't be used for shadowed registers, since
2122 * the rfir will restore the original value. So, for the shadowed
2123 * registers we put a -1 into r1 to indicate that the register
2124 * should not be used (the register being copied could also have
2125 * a -1 in it, but that is OK, it just means that we will have
2126 * to use the slow path instead).
2130 bv %r0(%r25) /* r0 */
2132 bv %r0(%r25) /* r1 - shadowed */
2134 bv %r0(%r25) /* r2 */
2136 bv %r0(%r25) /* r3 */
2138 bv %r0(%r25) /* r4 */
2140 bv %r0(%r25) /* r5 */
2142 bv %r0(%r25) /* r6 */
2144 bv %r0(%r25) /* r7 */
2146 bv %r0(%r25) /* r8 - shadowed */
2148 bv %r0(%r25) /* r9 - shadowed */
2150 bv %r0(%r25) /* r10 */
2152 bv %r0(%r25) /* r11 */
2154 bv %r0(%r25) /* r12 */
2156 bv %r0(%r25) /* r13 */
2158 bv %r0(%r25) /* r14 */
2160 bv %r0(%r25) /* r15 */
2162 bv %r0(%r25) /* r16 - shadowed */
2164 bv %r0(%r25) /* r17 - shadowed */
2166 bv %r0(%r25) /* r18 */
2168 bv %r0(%r25) /* r19 */
2170 bv %r0(%r25) /* r20 */
2172 bv %r0(%r25) /* r21 */
2174 bv %r0(%r25) /* r22 */
2176 bv %r0(%r25) /* r23 */
2178 bv %r0(%r25) /* r24 - shadowed */
2180 bv %r0(%r25) /* r25 - shadowed */
2182 bv %r0(%r25) /* r26 */
2184 bv %r0(%r25) /* r27 */
2186 bv %r0(%r25) /* r28 */
2188 bv %r0(%r25) /* r29 */
2190 bv %r0(%r25) /* r30 */
2192 bv %r0(%r25) /* r31 */
2198 * set_register is used by the non access tlb miss handlers to
2199 * copy the value of r1 into the general register specified in
2204 bv %r0(%r25) /* r0 (silly, but it is a place holder) */
2206 bv %r0(%r25) /* r1 */
2208 bv %r0(%r25) /* r2 */
2210 bv %r0(%r25) /* r3 */
2212 bv %r0(%r25) /* r4 */
2214 bv %r0(%r25) /* r5 */
2216 bv %r0(%r25) /* r6 */
2218 bv %r0(%r25) /* r7 */
2220 bv %r0(%r25) /* r8 */
2222 bv %r0(%r25) /* r9 */
2224 bv %r0(%r25) /* r10 */
2226 bv %r0(%r25) /* r11 */
2228 bv %r0(%r25) /* r12 */
2230 bv %r0(%r25) /* r13 */
2232 bv %r0(%r25) /* r14 */
2234 bv %r0(%r25) /* r15 */
2236 bv %r0(%r25) /* r16 */
2238 bv %r0(%r25) /* r17 */
2240 bv %r0(%r25) /* r18 */
2242 bv %r0(%r25) /* r19 */
2244 bv %r0(%r25) /* r20 */
2246 bv %r0(%r25) /* r21 */
2248 bv %r0(%r25) /* r22 */
2250 bv %r0(%r25) /* r23 */
2252 bv %r0(%r25) /* r24 */
2254 bv %r0(%r25) /* r25 */
2256 bv %r0(%r25) /* r26 */
2258 bv %r0(%r25) /* r27 */
2260 bv %r0(%r25) /* r28 */
2262 bv %r0(%r25) /* r29 */
2264 bv %r0(%r25) /* r30 */
2266 bv %r0(%r25) /* r31 */