2 * Copyright (C) 2000, 2001 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 * These are routines to set up and handle interrupts from the
21 * sb1250 general purpose timer 0. We're using the timer as a
22 * system clock, so we set it up to run at 100 Hz. On every
23 * interrupt, we update our idea of what the time of day is,
24 * then call do_timer() in the architecture-independent kernel
25 * code to do general bookkeeping (e.g. update jiffies, run
26 * bottom halves, etc.)
28 #include <linux/interrupt.h>
29 #include <linux/sched.h>
30 #include <linux/spinlock.h>
31 #include <linux/kernel_stat.h>
34 #include <asm/addrspace.h>
38 #include <asm/sibyte/sb1250.h>
39 #include <asm/sibyte/sb1250_regs.h>
40 #include <asm/sibyte/sb1250_int.h>
41 #include <asm/sibyte/sb1250_scd.h>
44 #define IMR_IP2_VAL K_INT_MAP_I0
45 #define IMR_IP3_VAL K_INT_MAP_I1
46 #define IMR_IP4_VAL K_INT_MAP_I2
48 #define SB1250_HPT_NUM 3
49 #define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
50 #define SB1250_HPT_SHIFT ((sizeof(unsigned int)*8)-V_SCD_TIMER_WIDTH)
53 extern int sb1250_steal_irq(int irq);
55 static unsigned int sb1250_hpt_read(void);
56 static void sb1250_hpt_init(unsigned int);
58 static unsigned int hpt_offset;
60 void __init sb1250_hpt_setup(void)
62 int cpu = smp_processor_id();
65 /* Setup hpt using timer #3 but do not enable irq for it */
66 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
67 __raw_writeq(SB1250_HPT_VALUE,
68 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT)));
69 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
70 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
73 * we need to fill 32 bits, so just use the upper 23 bits and pretend
74 * the timer is going 512Mhz instead of 1Mhz
76 mips_hpt_frequency = V_SCD_TIMER_FREQ << SB1250_HPT_SHIFT;
77 mips_hpt_init = sb1250_hpt_init;
78 mips_hpt_read = sb1250_hpt_read;
83 void sb1250_time_init(void)
85 int cpu = smp_processor_id();
86 int irq = K_INT_TIMER_0+cpu;
88 /* Only have 4 general purpose timers, and we use last one as hpt */
93 sb1250_mask_irq(cpu, irq);
95 /* Map the timer interrupt to ip[4] of this cpu */
96 __raw_writeq(IMR_IP4_VAL,
97 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
100 /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
101 /* Disable the timer and set up the count */
102 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
103 #ifdef CONFIG_SIMULATION
104 __raw_writeq((50000 / HZ) - 1,
105 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
107 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
108 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
111 /* Set the timer running */
112 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
113 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
115 sb1250_unmask_irq(cpu, irq);
116 sb1250_steal_irq(irq);
118 * This interrupt is "special" in that it doesn't use the request_irq
119 * way to hook the irq line. The timer interrupt is initialized early
120 * enough to make this a major pain, and it's also firing enough to
121 * warrant a bit of special case code. sb1250_timer_interrupt is
122 * called directly from irq_handler.S when IP[4] is set during an
127 void sb1250_timer_interrupt(void)
129 int cpu = smp_processor_id();
130 int irq = K_INT_TIMER_0 + cpu;
133 ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
134 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
138 * CPU 0 handles the global timer interrupt job
140 ll_timer_interrupt(irq);
144 * other CPUs should just do profiling and process accounting
146 ll_local_timer_interrupt(irq);
151 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
152 * again. There's no easy way to set to a specific value so store init value
153 * in hpt_offset and subtract each time.
155 * Note: Timer isn't full 32bits so shift it into the upper part making
156 * it appear to run at a higher frequency.
158 static unsigned int sb1250_hpt_read(void)
162 count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
164 count = (SB1250_HPT_VALUE - count) << SB1250_HPT_SHIFT;
166 return count - hpt_offset;
169 static void sb1250_hpt_init(unsigned int count)