2 * Atheros AR724X PCI host controller driver
4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
5 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/spinlock.h>
13 #include <linux/irq.h>
14 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <asm/mach-ath79/ath79.h>
18 #include <asm/mach-ath79/ar71xx_regs.h>
20 #define AR724X_PCI_REG_RESET 0x18
21 #define AR724X_PCI_REG_INT_STATUS 0x4c
22 #define AR724X_PCI_REG_INT_MASK 0x50
24 #define AR724X_PCI_RESET_LINK_UP BIT(0)
26 #define AR724X_PCI_INT_DEV0 BIT(14)
28 #define AR724X_PCI_IRQ_COUNT 1
30 #define AR7240_BAR0_WAR_VALUE 0xffff
32 struct ar724x_pci_controller {
33 void __iomem *devcfg_base;
34 void __iomem *ctrl_base;
45 struct pci_controller pci_controller;
46 struct resource io_res;
47 struct resource mem_res;
50 static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
54 reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
55 return reset & AR724X_PCI_RESET_LINK_UP;
58 static inline struct ar724x_pci_controller *
59 pci_bus_to_ar724x_controller(struct pci_bus *bus)
61 struct pci_controller *hose;
63 hose = (struct pci_controller *) bus->sysdata;
64 return container_of(hose, struct ar724x_pci_controller, pci_controller);
67 static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
68 int size, uint32_t *value)
70 struct ar724x_pci_controller *apc;
75 apc = pci_bus_to_ar724x_controller(bus);
77 return PCIBIOS_DEVICE_NOT_FOUND;
80 return PCIBIOS_DEVICE_NOT_FOUND;
82 base = apc->devcfg_base;
84 spin_lock_irqsave(&apc->lock, flags);
85 data = __raw_readl(base + (where & ~3));
103 spin_unlock_irqrestore(&apc->lock, flags);
105 return PCIBIOS_BAD_REGISTER_NUMBER;
108 spin_unlock_irqrestore(&apc->lock, flags);
110 if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
111 apc->bar0_is_cached) {
112 /* use the cached value */
113 *value = apc->bar0_value;
118 return PCIBIOS_SUCCESSFUL;
121 static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
122 int size, uint32_t value)
124 struct ar724x_pci_controller *apc;
130 apc = pci_bus_to_ar724x_controller(bus);
132 return PCIBIOS_DEVICE_NOT_FOUND;
135 return PCIBIOS_DEVICE_NOT_FOUND;
137 if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
138 if (value != 0xffffffff) {
140 * WAR for a hw issue. If the BAR0 register of the
141 * device is set to the proper base address, the
142 * memory space of the device is not accessible.
144 * Cache the intended value so it can be read back,
145 * and write a SoC specific constant value to the
146 * BAR0 register in order to make the device memory
149 apc->bar0_is_cached = true;
150 apc->bar0_value = value;
152 value = AR7240_BAR0_WAR_VALUE;
154 apc->bar0_is_cached = false;
158 base = apc->devcfg_base;
160 spin_lock_irqsave(&apc->lock, flags);
161 data = __raw_readl(base + (where & ~3));
165 s = ((where & 3) * 8);
166 data &= ~(0xff << s);
167 data |= ((value & 0xff) << s);
170 s = ((where & 2) * 8);
171 data &= ~(0xffff << s);
172 data |= ((value & 0xffff) << s);
178 spin_unlock_irqrestore(&apc->lock, flags);
180 return PCIBIOS_BAD_REGISTER_NUMBER;
183 __raw_writel(data, base + (where & ~3));
185 __raw_readl(base + (where & ~3));
186 spin_unlock_irqrestore(&apc->lock, flags);
188 return PCIBIOS_SUCCESSFUL;
191 static struct pci_ops ar724x_pci_ops = {
192 .read = ar724x_pci_read,
193 .write = ar724x_pci_write,
196 static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
198 struct ar724x_pci_controller *apc;
202 apc = irq_get_handler_data(irq);
203 base = apc->ctrl_base;
205 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
206 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
208 if (pending & AR724X_PCI_INT_DEV0)
209 generic_handle_irq(apc->irq_base + 0);
212 spurious_interrupt();
215 static void ar724x_pci_irq_unmask(struct irq_data *d)
217 struct ar724x_pci_controller *apc;
222 apc = irq_data_get_irq_chip_data(d);
223 base = apc->ctrl_base;
224 offset = apc->irq_base - d->irq;
228 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
229 __raw_writel(t | AR724X_PCI_INT_DEV0,
230 base + AR724X_PCI_REG_INT_MASK);
232 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
236 static void ar724x_pci_irq_mask(struct irq_data *d)
238 struct ar724x_pci_controller *apc;
243 apc = irq_data_get_irq_chip_data(d);
244 base = apc->ctrl_base;
245 offset = apc->irq_base - d->irq;
249 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
250 __raw_writel(t & ~AR724X_PCI_INT_DEV0,
251 base + AR724X_PCI_REG_INT_MASK);
254 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
256 t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
257 __raw_writel(t | AR724X_PCI_INT_DEV0,
258 base + AR724X_PCI_REG_INT_STATUS);
261 __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
265 static struct irq_chip ar724x_pci_irq_chip = {
266 .name = "AR724X PCI ",
267 .irq_mask = ar724x_pci_irq_mask,
268 .irq_unmask = ar724x_pci_irq_unmask,
269 .irq_mask_ack = ar724x_pci_irq_mask,
272 static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
278 base = apc->ctrl_base;
280 __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
281 __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
283 apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
285 for (i = apc->irq_base;
286 i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
287 irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
289 irq_set_chip_data(i, apc);
292 irq_set_handler_data(apc->irq, apc);
293 irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler);
296 static int ar724x_pci_probe(struct platform_device *pdev)
298 struct ar724x_pci_controller *apc;
299 struct resource *res;
306 apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
311 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
315 apc->ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
316 if (apc->ctrl_base == NULL)
319 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
323 apc->devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
324 if (!apc->devcfg_base)
327 apc->irq = platform_get_irq(pdev, 0);
331 spin_lock_init(&apc->lock);
333 res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
337 apc->io_res.parent = res;
338 apc->io_res.name = "PCI IO space";
339 apc->io_res.start = res->start;
340 apc->io_res.end = res->end;
341 apc->io_res.flags = IORESOURCE_IO;
343 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
347 apc->mem_res.parent = res;
348 apc->mem_res.name = "PCI memory space";
349 apc->mem_res.start = res->start;
350 apc->mem_res.end = res->end;
351 apc->mem_res.flags = IORESOURCE_MEM;
353 apc->pci_controller.pci_ops = &ar724x_pci_ops;
354 apc->pci_controller.io_resource = &apc->io_res;
355 apc->pci_controller.mem_resource = &apc->mem_res;
357 apc->link_up = ar724x_pci_check_link(apc);
359 dev_warn(&pdev->dev, "PCIe link is down\n");
361 ar724x_pci_irq_init(apc, id);
363 register_pci_controller(&apc->pci_controller);
368 static struct platform_driver ar724x_pci_driver = {
369 .probe = ar724x_pci_probe,
371 .name = "ar724x-pci",
372 .owner = THIS_MODULE,
376 static int __init ar724x_pci_init(void)
378 return platform_driver_register(&ar724x_pci_driver);
381 postcore_initcall(ar724x_pci_init);