Pileus Git - ~andy/linux/blob - arch/mips/mti-malta/malta-time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20 #include <linux/types.h>
  21 #include <linux/i8253.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/sched.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/timex.h>
  28 #include <linux/mc146818rtc.h>
  29
  30 #include <asm/mipsregs.h>
  31 #include <asm/mipsmtregs.h>
  32 #include <asm/hardirq.h>
  33 #include <asm/irq.h>
  34 #include <asm/div64.h>
  35 #include <asm/setup.h>
  36 #include <asm/time.h>
  37 #include <asm/mc146818-time.h>
  38 #include <asm/msc01_ic.h>
  39 #include <asm/gic.h>
  40
  41 #include <asm/mips-boards/generic.h>
  42 #include <asm/mips-boards/prom.h>
  43
  44 #include <asm/mips-boards/maltaint.h>
  45
  46 unsigned long cpu_khz;
  47 int gic_frequency;
  48
  49 static int mips_cpu_timer_irq;
  50 static int mips_cpu_perf_irq;
  51 extern int cp0_perfcount_irq;
  52
  53 static void mips_timer_dispatch(void)
  54 {
  55         do_IRQ(mips_cpu_timer_irq);
  56 }
  57
  58 static void mips_perf_dispatch(void)
  59 {
  60         do_IRQ(mips_cpu_perf_irq);
  61 }
  62
  63 static unsigned int freqround(unsigned int freq, unsigned int amount)
  64 {
  65         freq += amount;
  66         freq -= freq % (amount*2);
  67         return freq;
  68 }
  69
  70 /*
  71  * Estimate CPU and GIC frequencies.
  72  */
  73 static void __init estimate_frequencies(void)
  74 {
  75         unsigned long flags;
  76         unsigned int count, start;
  77         unsigned int giccount = 0, gicstart = 0;
  78
  79         local_irq_save(flags);
  80
  81         /* Start counter exactly on falling edge of update flag. */
  82         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
  83         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
  84
  85         /* Initialize counters. */
  86         start = read_c0_count();
  87         if (gic_present)
  88                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
  89
  90         /* Read counter exactly on falling edge of update flag. */
  91         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
  92         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
  93
  94         count = read_c0_count();
  95         if (gic_present)
  96                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
  97
  98         local_irq_restore(flags);
  99
 100         count -= start;
 101         if (gic_present)
 102                 giccount -= gicstart;
 103
 104         mips_hpt_frequency = count;
 105         if (gic_present)
 106                 gic_frequency = giccount;
 107 }
 108
 109 void read_persistent_clock(struct timespec *ts)
 110 {
 111         ts->tv_sec = mc146818_get_cmos_time();
 112         ts->tv_nsec = 0;
 113 }
 114
 115 static void __init plat_perf_setup(void)
 116 {
 117 #ifdef MSC01E_INT_BASE
 118         if (cpu_has_veic) {
 119                 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
 120                 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
 121         } else
 122 #endif
 123         if (cp0_perfcount_irq >= 0) {
 124                 if (cpu_has_vint)
 125                         set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
 126                 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 127 #ifdef CONFIG_SMP
 128                 irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
 129 #endif
 130         }
 131 }
 132
 133 unsigned int __cpuinit get_c0_compare_int(void)
 134 {
 135 #ifdef MSC01E_INT_BASE
 136         if (cpu_has_veic) {
 137                 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
 138                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 139         } else
 140 #endif
 141         {
 142                 if (cpu_has_vint)
 143                         set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
 144                 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 145         }
 146
 147         return mips_cpu_timer_irq;
 148 }
 149
 150 void __init plat_time_init(void)
 151 {
 152         unsigned int prid = read_c0_prid() & 0xffff00;
 153         unsigned int freq;
 154
 155         estimate_frequencies();
 156
 157         freq = mips_hpt_frequency;
 158         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 159             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 160                 freq *= 2;
 161         freq = freqround(freq, 5000);
 162         pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000,
 163                (freq%1000000)*100/1000000);
 164         cpu_khz = freq / 1000;
 165
 166         if (gic_present) {
 167                 freq = freqround(gic_frequency, 5000);
 168                 pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000,
 169                        (freq%1000000)*100/1000000);
 170                 gic_clocksource_init(gic_frequency);
 171         } else
 172                 init_r4k_clocksource();
 173
 174 #ifdef CONFIG_I8253
 175         /* Only Malta has a PIT. */
 176         setup_pit_timer();
 177 #endif
 178
 179         mips_scroll_message();
 180
 181         plat_perf_setup();
 182 }