Pileus Git - ~andy/linux/blob - arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.
   6  *
   7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   8  * Copyright (C) 2000  MIPS Technologies, Inc.
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  22  *
  23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  24  * required for #float(switch) or #float(trap), where it catches all
  25  * COP1 instructions via the "CoProcessor Unusable" exception.
  26  *
  27  * More surprisingly it is also required for #float(ieee), to help out
  28  * the hardware fpu at the boundaries of the IEEE-754 representation
  29  * (denormalised values, infinities, underflow, etc).  It is made
  30  * quite nasty because emulation of some non-COP1 instructions is
  31  * required, e.g. in branch delay slots.
  32  *
  33  * Note if you know that you won't have an fpu, then you'll get much
  34  * better performance by compiling with -msoft-float!
  35  */
  36 #include <linux/sched.h>
  37 #include <linux/module.h>
  38 #include <linux/debugfs.h>
  39 #include <linux/perf_event.h>
  40
  41 #include <asm/inst.h>
  42 #include <asm/bootinfo.h>
  43 #include <asm/processor.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/signal.h>
  46 #include <asm/mipsregs.h>
  47 #include <asm/fpu_emulator.h>
  48 #include <asm/fpu.h>
  49 #include <asm/uaccess.h>
  50 #include <asm/branch.h>
  51
  52 #include "ieee754.h"
  53
  54 /* Strap kernel emulator for full MIPS IV emulation */
  55
  56 #ifdef __mips
  57 #undef __mips
  58 #endif
  59 #define __mips 4
  60
  61 /* Function which emulates a floating point instruction. */
  62
  63 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  64         mips_instruction);
  65
  66 #if __mips >= 4 && __mips != 32
  67 static int fpux_emu(struct pt_regs *,
  68         struct mips_fpu_struct *, mips_instruction, void *__user *);
  69 #endif
  70
  71 /* Further private data for which no space exists in mips_fpu_struct */
  72
  73 #ifdef CONFIG_DEBUG_FS
  74 DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
  75 #endif
  76
  77 /* Control registers */
  78
  79 #define FPCREG_RID      0       /* $0  = revision id */
  80 #define FPCREG_CSR      31      /* $31 = csr */
  81
  82 /* Determine rounding mode from the RM bits of the FCSR */
  83 #define modeindex(v) ((v) & FPU_CSR_RM)
  84
  85 /* microMIPS bitfields */
  86 #define MM_POOL32A_MINOR_MASK   0x3f
  87 #define MM_POOL32A_MINOR_SHIFT  0x6
  88 #define MM_MIPS32_COND_FC       0x30
  89
  90 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
  91 static const unsigned char ieee_rm[4] = {
  92         [FPU_CSR_RN] = IEEE754_RN,
  93         [FPU_CSR_RZ] = IEEE754_RZ,
  94         [FPU_CSR_RU] = IEEE754_RU,
  95         [FPU_CSR_RD] = IEEE754_RD,
  96 };
  97 /* Convert IEEE library modes to Mips rounding mode (0..3). */
  98 static const unsigned char mips_rm[4] = {
  99         [IEEE754_RN] = FPU_CSR_RN,
 100         [IEEE754_RZ] = FPU_CSR_RZ,
 101         [IEEE754_RD] = FPU_CSR_RD,
 102         [IEEE754_RU] = FPU_CSR_RU,
 103 };
 104
 105 #if __mips >= 4
 106 /* convert condition code register number to csr bit */
 107 static const unsigned int fpucondbit[8] = {
 108         FPU_CSR_COND0,
 109         FPU_CSR_COND1,
 110         FPU_CSR_COND2,
 111         FPU_CSR_COND3,
 112         FPU_CSR_COND4,
 113         FPU_CSR_COND5,
 114         FPU_CSR_COND6,
 115         FPU_CSR_COND7
 116 };
 117 #endif
 118
 119 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
 120 static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
 121
 122 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
 123 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
 124 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
 125 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
 126 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
 127
 128 /*
 129  * This functions translates a 32-bit microMIPS instruction
 130  * into a 32-bit MIPS32 instruction. Returns 0 on success
 131  * and SIGILL otherwise.
 132  */
 133 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
 134 {
 135         union mips_instruction insn = *insn_ptr;
 136         union mips_instruction mips32_insn = insn;
 137         int func, fmt, op;
 138
 139         switch (insn.mm_i_format.opcode) {
 140         case mm_ldc132_op:
 141                 mips32_insn.mm_i_format.opcode = ldc1_op;
 142                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 143                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 144                 break;
 145         case mm_lwc132_op:
 146                 mips32_insn.mm_i_format.opcode = lwc1_op;
 147                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 148                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 149                 break;
 150         case mm_sdc132_op:
 151                 mips32_insn.mm_i_format.opcode = sdc1_op;
 152                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 153                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 154                 break;
 155         case mm_swc132_op:
 156                 mips32_insn.mm_i_format.opcode = swc1_op;
 157                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 158                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 159                 break;
 160         case mm_pool32i_op:
 161                 /* NOTE: offset is << by 1 if in microMIPS mode. */
 162                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 163                     (insn.mm_i_format.rt == mm_bc1t_op)) {
 164                         mips32_insn.fb_format.opcode = cop1_op;
 165                         mips32_insn.fb_format.bc = bc_op;
 166                         mips32_insn.fb_format.flag =
 167                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 168                 } else
 169                         return SIGILL;
 170                 break;
 171         case mm_pool32f_op:
 172                 switch (insn.mm_fp0_format.func) {
 173                 case mm_32f_01_op:
 174                 case mm_32f_11_op:
 175                 case mm_32f_02_op:
 176                 case mm_32f_12_op:
 177                 case mm_32f_41_op:
 178                 case mm_32f_51_op:
 179                 case mm_32f_42_op:
 180                 case mm_32f_52_op:
 181                         op = insn.mm_fp0_format.func;
 182                         if (op == mm_32f_01_op)
 183                                 func = madd_s_op;
 184                         else if (op == mm_32f_11_op)
 185                                 func = madd_d_op;
 186                         else if (op == mm_32f_02_op)
 187                                 func = nmadd_s_op;
 188                         else if (op == mm_32f_12_op)
 189                                 func = nmadd_d_op;
 190                         else if (op == mm_32f_41_op)
 191                                 func = msub_s_op;
 192                         else if (op == mm_32f_51_op)
 193                                 func = msub_d_op;
 194                         else if (op == mm_32f_42_op)
 195                                 func = nmsub_s_op;
 196                         else
 197                                 func = nmsub_d_op;
 198                         mips32_insn.fp6_format.opcode = cop1x_op;
 199                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 200                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 201                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 202                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 203                         mips32_insn.fp6_format.func = func;
 204                         break;
 205                 case mm_32f_10_op:
 206                         func = -1;      /* Invalid */
 207                         op = insn.mm_fp5_format.op & 0x7;
 208                         if (op == mm_ldxc1_op)
 209                                 func = ldxc1_op;
 210                         else if (op == mm_sdxc1_op)
 211                                 func = sdxc1_op;
 212                         else if (op == mm_lwxc1_op)
 213                                 func = lwxc1_op;
 214                         else if (op == mm_swxc1_op)
 215                                 func = swxc1_op;
 216
 217                         if (func != -1) {
 218                                 mips32_insn.r_format.opcode = cop1x_op;
 219                                 mips32_insn.r_format.rs =
 220                                         insn.mm_fp5_format.base;
 221                                 mips32_insn.r_format.rt =
 222                                         insn.mm_fp5_format.index;
 223                                 mips32_insn.r_format.rd = 0;
 224                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 225                                 mips32_insn.r_format.func = func;
 226                         } else
 227                                 return SIGILL;
 228                         break;
 229                 case mm_32f_40_op:
 230                         op = -1;        /* Invalid */
 231                         if (insn.mm_fp2_format.op == mm_fmovt_op)
 232                                 op = 1;
 233                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
 234                                 op = 0;
 235                         if (op != -1) {
 236                                 mips32_insn.fp0_format.opcode = cop1_op;
 237                                 mips32_insn.fp0_format.fmt =
 238                                         sdps_format[insn.mm_fp2_format.fmt];
 239                                 mips32_insn.fp0_format.ft =
 240                                         (insn.mm_fp2_format.cc<<2) + op;
 241                                 mips32_insn.fp0_format.fs =
 242                                         insn.mm_fp2_format.fs;
 243                                 mips32_insn.fp0_format.fd =
 244                                         insn.mm_fp2_format.fd;
 245                                 mips32_insn.fp0_format.func = fmovc_op;
 246                         } else
 247                                 return SIGILL;
 248                         break;
 249                 case mm_32f_60_op:
 250                         func = -1;      /* Invalid */
 251                         if (insn.mm_fp0_format.op == mm_fadd_op)
 252                                 func = fadd_op;
 253                         else if (insn.mm_fp0_format.op == mm_fsub_op)
 254                                 func = fsub_op;
 255                         else if (insn.mm_fp0_format.op == mm_fmul_op)
 256                                 func = fmul_op;
 257                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
 258                                 func = fdiv_op;
 259                         if (func != -1) {
 260                                 mips32_insn.fp0_format.opcode = cop1_op;
 261                                 mips32_insn.fp0_format.fmt =
 262                                         sdps_format[insn.mm_fp0_format.fmt];
 263                                 mips32_insn.fp0_format.ft =
 264                                         insn.mm_fp0_format.ft;
 265                                 mips32_insn.fp0_format.fs =
 266                                         insn.mm_fp0_format.fs;
 267                                 mips32_insn.fp0_format.fd =
 268                                         insn.mm_fp0_format.fd;
 269                                 mips32_insn.fp0_format.func = func;
 270                         } else
 271                                 return SIGILL;
 272                         break;
 273                 case mm_32f_70_op:
 274                         func = -1;      /* Invalid */
 275                         if (insn.mm_fp0_format.op == mm_fmovn_op)
 276                                 func = fmovn_op;
 277                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
 278                                 func = fmovz_op;
 279                         if (func != -1) {
 280                                 mips32_insn.fp0_format.opcode = cop1_op;
 281                                 mips32_insn.fp0_format.fmt =
 282                                         sdps_format[insn.mm_fp0_format.fmt];
 283                                 mips32_insn.fp0_format.ft =
 284                                         insn.mm_fp0_format.ft;
 285                                 mips32_insn.fp0_format.fs =
 286                                         insn.mm_fp0_format.fs;
 287                                 mips32_insn.fp0_format.fd =
 288                                         insn.mm_fp0_format.fd;
 289                                 mips32_insn.fp0_format.func = func;
 290                         } else
 291                                 return SIGILL;
 292                         break;
 293                 case mm_32f_73_op:    /* POOL32FXF */
 294                         switch (insn.mm_fp1_format.op) {
 295                         case mm_movf0_op:
 296                         case mm_movf1_op:
 297                         case mm_movt0_op:
 298                         case mm_movt1_op:
 299                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 300                                     mm_movf0_op)
 301                                         op = 0;
 302                                 else
 303                                         op = 1;
 304                                 mips32_insn.r_format.opcode = spec_op;
 305                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 306                                 mips32_insn.r_format.rt =
 307                                         (insn.mm_fp4_format.cc << 2) + op;
 308                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 309                                 mips32_insn.r_format.re = 0;
 310                                 mips32_insn.r_format.func = movc_op;
 311                                 break;
 312                         case mm_fcvtd0_op:
 313                         case mm_fcvtd1_op:
 314                         case mm_fcvts0_op:
 315                         case mm_fcvts1_op:
 316                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 317                                     mm_fcvtd0_op) {
 318                                         func = fcvtd_op;
 319                                         fmt = swl_format[insn.mm_fp3_format.fmt];
 320                                 } else {
 321                                         func = fcvts_op;
 322                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
 323                                 }
 324                                 mips32_insn.fp0_format.opcode = cop1_op;
 325                                 mips32_insn.fp0_format.fmt = fmt;
 326                                 mips32_insn.fp0_format.ft = 0;
 327                                 mips32_insn.fp0_format.fs =
 328                                         insn.mm_fp3_format.fs;
 329                                 mips32_insn.fp0_format.fd =
 330                                         insn.mm_fp3_format.rt;
 331                                 mips32_insn.fp0_format.func = func;
 332                                 break;
 333                         case mm_fmov0_op:
 334                         case mm_fmov1_op:
 335                         case mm_fabs0_op:
 336                         case mm_fabs1_op:
 337                         case mm_fneg0_op:
 338                         case mm_fneg1_op:
 339                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 340                                     mm_fmov0_op)
 341                                         func = fmov_op;
 342                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
 343                                          mm_fabs0_op)
 344                                         func = fabs_op;
 345                                 else
 346                                         func = fneg_op;
 347                                 mips32_insn.fp0_format.opcode = cop1_op;
 348                                 mips32_insn.fp0_format.fmt =
 349                                         sdps_format[insn.mm_fp3_format.fmt];
 350                                 mips32_insn.fp0_format.ft = 0;
 351                                 mips32_insn.fp0_format.fs =
 352                                         insn.mm_fp3_format.fs;
 353                                 mips32_insn.fp0_format.fd =
 354                                         insn.mm_fp3_format.rt;
 355                                 mips32_insn.fp0_format.func = func;
 356                                 break;
 357                         case mm_ffloorl_op:
 358                         case mm_ffloorw_op:
 359                         case mm_fceill_op:
 360                         case mm_fceilw_op:
 361                         case mm_ftruncl_op:
 362                         case mm_ftruncw_op:
 363                         case mm_froundl_op:
 364                         case mm_froundw_op:
 365                         case mm_fcvtl_op:
 366                         case mm_fcvtw_op:
 367                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
 368                                         func = ffloorl_op;
 369                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 370                                         func = ffloor_op;
 371                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
 372                                         func = fceill_op;
 373                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
 374                                         func = fceil_op;
 375                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 376                                         func = ftruncl_op;
 377                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 378                                         func = ftrunc_op;
 379                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
 380                                         func = froundl_op;
 381                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
 382                                         func = fround_op;
 383                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 384                                         func = fcvtl_op;
 385                                 else
 386                                         func = fcvtw_op;
 387                                 mips32_insn.fp0_format.opcode = cop1_op;
 388                                 mips32_insn.fp0_format.fmt =
 389                                         sd_format[insn.mm_fp1_format.fmt];
 390                                 mips32_insn.fp0_format.ft = 0;
 391                                 mips32_insn.fp0_format.fs =
 392                                         insn.mm_fp1_format.fs;
 393                                 mips32_insn.fp0_format.fd =
 394                                         insn.mm_fp1_format.rt;
 395                                 mips32_insn.fp0_format.func = func;
 396                                 break;
 397                         case mm_frsqrt_op:
 398                         case mm_fsqrt_op:
 399                         case mm_frecip_op:
 400                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
 401                                         func = frsqrt_op;
 402                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 403                                         func = fsqrt_op;
 404                                 else
 405                                         func = frecip_op;
 406                                 mips32_insn.fp0_format.opcode = cop1_op;
 407                                 mips32_insn.fp0_format.fmt =
 408                                         sdps_format[insn.mm_fp1_format.fmt];
 409                                 mips32_insn.fp0_format.ft = 0;
 410                                 mips32_insn.fp0_format.fs =
 411                                         insn.mm_fp1_format.fs;
 412                                 mips32_insn.fp0_format.fd =
 413                                         insn.mm_fp1_format.rt;
 414                                 mips32_insn.fp0_format.func = func;
 415                                 break;
 416                         case mm_mfc1_op:
 417                         case mm_mtc1_op:
 418                         case mm_cfc1_op:
 419                         case mm_ctc1_op:
 420                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
 421                                         op = mfc_op;
 422                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
 423                                         op = mtc_op;
 424                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
 425                                         op = cfc_op;
 426                                 else
 427                                         op = ctc_op;
 428                                 mips32_insn.fp1_format.opcode = cop1_op;
 429                                 mips32_insn.fp1_format.op = op;
 430                                 mips32_insn.fp1_format.rt =
 431                                         insn.mm_fp1_format.rt;
 432                                 mips32_insn.fp1_format.fs =
 433                                         insn.mm_fp1_format.fs;
 434                                 mips32_insn.fp1_format.fd = 0;
 435                                 mips32_insn.fp1_format.func = 0;
 436                                 break;
 437                         default:
 438                                 return SIGILL;
 439                         }
 440                         break;
 441                 case mm_32f_74_op:      /* c.cond.fmt */
 442                         mips32_insn.fp0_format.opcode = cop1_op;
 443                         mips32_insn.fp0_format.fmt =
 444                                 sdps_format[insn.mm_fp4_format.fmt];
 445                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 446                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 447                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 448                         mips32_insn.fp0_format.func =
 449                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 450                         break;
 451                 default:
 452                         return SIGILL;
 453                 }
 454                 break;
 455         default:
 456                 return SIGILL;
 457         }
 458
 459         *insn_ptr = mips32_insn;
 460         return 0;
 461 }
 462
 463 int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 464                      unsigned long *contpc)
 465 {
 466         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 467         int bc_false = 0;
 468         unsigned int fcr31;
 469         unsigned int bit;
 470
 471         if (!cpu_has_mmips)
 472                 return 0;
 473
 474         switch (insn.mm_i_format.opcode) {
 475         case mm_pool32a_op:
 476                 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
 477                     mm_pool32axf_op) {
 478                         switch (insn.mm_i_format.simmediate >>
 479                                 MM_POOL32A_MINOR_SHIFT) {
 480                         case mm_jalr_op:
 481                         case mm_jalrhb_op:
 482                         case mm_jalrs_op:
 483                         case mm_jalrshb_op:
 484                                 if (insn.mm_i_format.rt != 0)   /* Not mm_jr */
 485                                         regs->regs[insn.mm_i_format.rt] =
 486                                                 regs->cp0_epc +
 487                                                 dec_insn.pc_inc +
 488                                                 dec_insn.next_pc_inc;
 489                                 *contpc = regs->regs[insn.mm_i_format.rs];
 490                                 return 1;
 491                         }
 492                 }
 493                 break;
 494         case mm_pool32i_op:
 495                 switch (insn.mm_i_format.rt) {
 496                 case mm_bltzals_op:
 497                 case mm_bltzal_op:
 498                         regs->regs[31] = regs->cp0_epc +
 499                                 dec_insn.pc_inc +
 500                                 dec_insn.next_pc_inc;
 501                         /* Fall through */
 502                 case mm_bltz_op:
 503                         if ((long)regs->regs[insn.mm_i_format.rs] < 0)
 504                                 *contpc = regs->cp0_epc +
 505                                         dec_insn.pc_inc +
 506                                         (insn.mm_i_format.simmediate << 1);
 507                         else
 508                                 *contpc = regs->cp0_epc +
 509                                         dec_insn.pc_inc +
 510                                         dec_insn.next_pc_inc;
 511                         return 1;
 512                 case mm_bgezals_op:
 513                 case mm_bgezal_op:
 514                         regs->regs[31] = regs->cp0_epc +
 515                                         dec_insn.pc_inc +
 516                                         dec_insn.next_pc_inc;
 517                         /* Fall through */
 518                 case mm_bgez_op:
 519                         if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
 520                                 *contpc = regs->cp0_epc +
 521                                         dec_insn.pc_inc +
 522                                         (insn.mm_i_format.simmediate << 1);
 523                         else
 524                                 *contpc = regs->cp0_epc +
 525                                         dec_insn.pc_inc +
 526                                         dec_insn.next_pc_inc;
 527                         return 1;
 528                 case mm_blez_op:
 529                         if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
 530                                 *contpc = regs->cp0_epc +
 531                                         dec_insn.pc_inc +
 532                                         (insn.mm_i_format.simmediate << 1);
 533                         else
 534                                 *contpc = regs->cp0_epc +
 535                                         dec_insn.pc_inc +
 536                                         dec_insn.next_pc_inc;
 537                         return 1;
 538                 case mm_bgtz_op:
 539                         if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
 540                                 *contpc = regs->cp0_epc +
 541                                         dec_insn.pc_inc +
 542                                         (insn.mm_i_format.simmediate << 1);
 543                         else
 544                                 *contpc = regs->cp0_epc +
 545                                         dec_insn.pc_inc +
 546                                         dec_insn.next_pc_inc;
 547                         return 1;
 548                 case mm_bc2f_op:
 549                 case mm_bc1f_op:
 550                         bc_false = 1;
 551                         /* Fall through */
 552                 case mm_bc2t_op:
 553                 case mm_bc1t_op:
 554                         preempt_disable();
 555                         if (is_fpu_owner())
 556                                 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
 557                         else
 558                                 fcr31 = current->thread.fpu.fcr31;
 559                         preempt_enable();
 560
 561                         if (bc_false)
 562                                 fcr31 = ~fcr31;
 563
 564                         bit = (insn.mm_i_format.rs >> 2);
 565                         bit += (bit != 0);
 566                         bit += 23;
 567                         if (fcr31 & (1 << bit))
 568                                 *contpc = regs->cp0_epc +
 569                                         dec_insn.pc_inc +
 570                                         (insn.mm_i_format.simmediate << 1);
 571                         else
 572                                 *contpc = regs->cp0_epc +
 573                                         dec_insn.pc_inc + dec_insn.next_pc_inc;
 574                         return 1;
 575                 }
 576                 break;
 577         case mm_pool16c_op:
 578                 switch (insn.mm_i_format.rt) {
 579                 case mm_jalr16_op:
 580                 case mm_jalrs16_op:
 581                         regs->regs[31] = regs->cp0_epc +
 582                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 583                         /* Fall through */
 584                 case mm_jr16_op:
 585                         *contpc = regs->regs[insn.mm_i_format.rs];
 586                         return 1;
 587                 }
 588                 break;
 589         case mm_beqz16_op:
 590                 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
 591                         *contpc = regs->cp0_epc +
 592                                 dec_insn.pc_inc +
 593                                 (insn.mm_b1_format.simmediate << 1);
 594                 else
 595                         *contpc = regs->cp0_epc +
 596                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 597                 return 1;
 598         case mm_bnez16_op:
 599                 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
 600                         *contpc = regs->cp0_epc +
 601                                 dec_insn.pc_inc +
 602                                 (insn.mm_b1_format.simmediate << 1);
 603                 else
 604                         *contpc = regs->cp0_epc +
 605                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 606                 return 1;
 607         case mm_b16_op:
 608                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 609                          (insn.mm_b0_format.simmediate << 1);
 610                 return 1;
 611         case mm_beq32_op:
 612                 if (regs->regs[insn.mm_i_format.rs] ==
 613                     regs->regs[insn.mm_i_format.rt])
 614                         *contpc = regs->cp0_epc +
 615                                 dec_insn.pc_inc +
 616                                 (insn.mm_i_format.simmediate << 1);
 617                 else
 618                         *contpc = regs->cp0_epc +
 619                                 dec_insn.pc_inc +
 620                                 dec_insn.next_pc_inc;
 621                 return 1;
 622         case mm_bne32_op:
 623                 if (regs->regs[insn.mm_i_format.rs] !=
 624                     regs->regs[insn.mm_i_format.rt])
 625                         *contpc = regs->cp0_epc +
 626                                 dec_insn.pc_inc +
 627                                 (insn.mm_i_format.simmediate << 1);
 628                 else
 629                         *contpc = regs->cp0_epc +
 630                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 631                 return 1;
 632         case mm_jalx32_op:
 633                 regs->regs[31] = regs->cp0_epc +
 634                         dec_insn.pc_inc + dec_insn.next_pc_inc;
 635                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 636                 *contpc >>= 28;
 637                 *contpc <<= 28;
 638                 *contpc |= (insn.j_format.target << 2);
 639                 return 1;
 640         case mm_jals32_op:
 641         case mm_jal32_op:
 642                 regs->regs[31] = regs->cp0_epc +
 643                         dec_insn.pc_inc + dec_insn.next_pc_inc;
 644                 /* Fall through */
 645         case mm_j32_op:
 646                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 647                 *contpc >>= 27;
 648                 *contpc <<= 27;
 649                 *contpc |= (insn.j_format.target << 1);
 650                 set_isa16_mode(*contpc);
 651                 return 1;
 652         }
 653         return 0;
 654 }
 655
 656 /*
 657  * Redundant with logic already in kernel/branch.c,
 658  * embedded in compute_return_epc.  At some point,
 659  * a single subroutine should be used across both
 660  * modules.
 661  */
 662 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 663                          unsigned long *contpc)
 664 {
 665         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 666         unsigned int fcr31;
 667         unsigned int bit = 0;
 668
 669         switch (insn.i_format.opcode) {
 670         case spec_op:
 671                 switch (insn.r_format.func) {
 672                 case jalr_op:
 673                         regs->regs[insn.r_format.rd] =
 674                                 regs->cp0_epc + dec_insn.pc_inc +
 675                                 dec_insn.next_pc_inc;
 676                         /* Fall through */
 677                 case jr_op:
 678                         *contpc = regs->regs[insn.r_format.rs];
 679                         return 1;
 680                 }
 681                 break;
 682         case bcond_op:
 683                 switch (insn.i_format.rt) {
 684                 case bltzal_op:
 685                 case bltzall_op:
 686                         regs->regs[31] = regs->cp0_epc +
 687                                 dec_insn.pc_inc +
 688                                 dec_insn.next_pc_inc;
 689                         /* Fall through */
 690                 case bltz_op:
 691                 case bltzl_op:
 692                         if ((long)regs->regs[insn.i_format.rs] < 0)
 693                                 *contpc = regs->cp0_epc +
 694                                         dec_insn.pc_inc +
 695                                         (insn.i_format.simmediate << 2);
 696                         else
 697                                 *contpc = regs->cp0_epc +
 698                                         dec_insn.pc_inc +
 699                                         dec_insn.next_pc_inc;
 700                         return 1;
 701                 case bgezal_op:
 702                 case bgezall_op:
 703                         regs->regs[31] = regs->cp0_epc +
 704                                 dec_insn.pc_inc +
 705                                 dec_insn.next_pc_inc;
 706                         /* Fall through */
 707                 case bgez_op:
 708                 case bgezl_op:
 709                         if ((long)regs->regs[insn.i_format.rs] >= 0)
 710                                 *contpc = regs->cp0_epc +
 711                                         dec_insn.pc_inc +
 712                                         (insn.i_format.simmediate << 2);
 713                         else
 714                                 *contpc = regs->cp0_epc +
 715                                         dec_insn.pc_inc +
 716                                         dec_insn.next_pc_inc;
 717                         return 1;
 718                 }
 719                 break;
 720         case jalx_op:
 721                 set_isa16_mode(bit);
 722         case jal_op:
 723                 regs->regs[31] = regs->cp0_epc +
 724                         dec_insn.pc_inc +
 725                         dec_insn.next_pc_inc;
 726                 /* Fall through */
 727         case j_op:
 728                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 729                 *contpc >>= 28;
 730                 *contpc <<= 28;
 731                 *contpc |= (insn.j_format.target << 2);
 732                 /* Set microMIPS mode bit: XOR for jalx. */
 733                 *contpc ^= bit;
 734                 return 1;
 735         case beq_op:
 736         case beql_op:
 737                 if (regs->regs[insn.i_format.rs] ==
 738                     regs->regs[insn.i_format.rt])
 739                         *contpc = regs->cp0_epc +
 740                                 dec_insn.pc_inc +
 741                                 (insn.i_format.simmediate << 2);
 742                 else
 743                         *contpc = regs->cp0_epc +
 744                                 dec_insn.pc_inc +
 745                                 dec_insn.next_pc_inc;
 746                 return 1;
 747         case bne_op:
 748         case bnel_op:
 749                 if (regs->regs[insn.i_format.rs] !=
 750                     regs->regs[insn.i_format.rt])
 751                         *contpc = regs->cp0_epc +
 752                                 dec_insn.pc_inc +
 753                                 (insn.i_format.simmediate << 2);
 754                 else
 755                         *contpc = regs->cp0_epc +
 756                                 dec_insn.pc_inc +
 757                                 dec_insn.next_pc_inc;
 758                 return 1;
 759         case blez_op:
 760         case blezl_op:
 761                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 762                         *contpc = regs->cp0_epc +
 763                                 dec_insn.pc_inc +
 764                                 (insn.i_format.simmediate << 2);
 765                 else
 766                         *contpc = regs->cp0_epc +
 767                                 dec_insn.pc_inc +
 768                                 dec_insn.next_pc_inc;
 769                 return 1;
 770         case bgtz_op:
 771         case bgtzl_op:
 772                 if ((long)regs->regs[insn.i_format.rs] > 0)
 773                         *contpc = regs->cp0_epc +
 774                                 dec_insn.pc_inc +
 775                                 (insn.i_format.simmediate << 2);
 776                 else
 777                         *contpc = regs->cp0_epc +
 778                                 dec_insn.pc_inc +
 779                                 dec_insn.next_pc_inc;
 780                 return 1;
 781 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 782         case lwc2_op: /* This is bbit0 on Octeon */
 783                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
 784                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 785                 else
 786                         *contpc = regs->cp0_epc + 8;
 787                 return 1;
 788         case ldc2_op: /* This is bbit032 on Octeon */
 789                 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
 790                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 791                 else
 792                         *contpc = regs->cp0_epc + 8;
 793                 return 1;
 794         case swc2_op: /* This is bbit1 on Octeon */
 795                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 796                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 797                 else
 798                         *contpc = regs->cp0_epc + 8;
 799                 return 1;
 800         case sdc2_op: /* This is bbit132 on Octeon */
 801                 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
 802                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 803                 else
 804                         *contpc = regs->cp0_epc + 8;
 805                 return 1;
 806 #endif
 807         case cop0_op:
 808         case cop1_op:
 809         case cop2_op:
 810         case cop1x_op:
 811                 if (insn.i_format.rs == bc_op) {
 812                         preempt_disable();
 813                         if (is_fpu_owner())
 814                                 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
 815                         else
 816                                 fcr31 = current->thread.fpu.fcr31;
 817                         preempt_enable();
 818
 819                         bit = (insn.i_format.rt >> 2);
 820                         bit += (bit != 0);
 821                         bit += 23;
 822                         switch (insn.i_format.rt & 3) {
 823                         case 0: /* bc1f */
 824                         case 2: /* bc1fl */
 825                                 if (~fcr31 & (1 << bit))
 826                                         *contpc = regs->cp0_epc +
 827                                                 dec_insn.pc_inc +
 828                                                 (insn.i_format.simmediate << 2);
 829                                 else
 830                                         *contpc = regs->cp0_epc +
 831                                                 dec_insn.pc_inc +
 832                                                 dec_insn.next_pc_inc;
 833                                 return 1;
 834                         case 1: /* bc1t */
 835                         case 3: /* bc1tl */
 836                                 if (fcr31 & (1 << bit))
 837                                         *contpc = regs->cp0_epc +
 838                                                 dec_insn.pc_inc +
 839                                                 (insn.i_format.simmediate << 2);
 840                                 else
 841                                         *contpc = regs->cp0_epc +
 842                                                 dec_insn.pc_inc +
 843                                                 dec_insn.next_pc_inc;
 844                                 return 1;
 845                         }
 846                 }
 847                 break;
 848         }
 849         return 0;
 850 }
 851
 852 /*
 853  * In the Linux kernel, we support selection of FPR format on the
 854  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
 855  * is hardwired to zero, which would imply a 32-bit FPU even for
 856  * 64-bit CPUs so we rather look at TIF_32BIT_REGS.
 857  * FPU emu is slow and bulky and optimizing this function offers fairly
 858  * sizeable benefits so we try to be clever and make this function return
 859  * a constant whenever possible, that is on 64-bit kernels without O32
 860  * compatibility enabled and on 32-bit kernels.
 861  */
 862 static inline int cop1_64bit(struct pt_regs *xcp)
 863 {
 864 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
 865         return 1;
 866 #elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32)
 867         return !test_thread_flag(TIF_32BIT_REGS);
 868 #else
 869         return 0;
 870 #endif
 871 }
 872
 873 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
 874                         (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
 875
 876 #define SITOREG(si, x)  (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
 877                         cop1_64bit(xcp) || !(x & 1) ? \
 878                         ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
 879                         ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
 880
 881 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
 882 #define DITOREG(di, x)  (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
 883
 884 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 885 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
 886 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
 887 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
 888
 889 /*
 890  * Emulate the single floating point instruction pointed at by EPC.
 891  * Two instructions if the instruction is in a branch delay slot.
 892  */
 893
 894 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 895                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 896 {
 897         mips_instruction ir;
 898         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 899         unsigned int cond;
 900         int pc_inc;
 901
 902         /* XXX NEC Vr54xx bug workaround */
 903         if (xcp->cp0_cause & CAUSEF_BD) {
 904                 if (dec_insn.micro_mips_mode) {
 905                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
 906                                 xcp->cp0_cause &= ~CAUSEF_BD;
 907                 } else {
 908                         if (!isBranchInstr(xcp, dec_insn, &contpc))
 909                                 xcp->cp0_cause &= ~CAUSEF_BD;
 910                 }
 911         }
 912
 913         if (xcp->cp0_cause & CAUSEF_BD) {
 914                 /*
 915                  * The instruction to be emulated is in a branch delay slot
 916                  * which means that we have to  emulate the branch instruction
 917                  * BEFORE we do the cop1 instruction.
 918                  *
 919                  * This branch could be a COP1 branch, but in that case we
 920                  * would have had a trap for that instruction, and would not
 921                  * come through this route.
 922                  *
 923                  * Linux MIPS branch emulator operates on context, updating the
 924                  * cp0_epc.
 925                  */
 926                 ir = dec_insn.next_insn;  /* process delay slot instr */
 927                 pc_inc = dec_insn.next_pc_inc;
 928         } else {
 929                 ir = dec_insn.insn;       /* process current instr */
 930                 pc_inc = dec_insn.pc_inc;
 931         }
 932
 933         /*
 934          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
 935          * instructions, we want to convert microMIPS FPU instructions
 936          * into MIPS32 instructions so that we could reuse all of the
 937          * FPU emulation code.
 938          *
 939          * NOTE: We cannot do this for branch instructions since they
 940          *       are not a subset. Example: Cannot emulate a 16-bit
 941          *       aligned target address with a MIPS32 instruction.
 942          */
 943         if (dec_insn.micro_mips_mode) {
 944                 /*
 945                  * If next instruction is a 16-bit instruction, then it
 946                  * it cannot be a FPU instruction. This could happen
 947                  * since we can be called for non-FPU instructions.
 948                  */
 949                 if ((pc_inc == 2) ||
 950                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
 951                          == SIGILL))
 952                         return SIGILL;
 953         }
 954
 955       emul:
 956         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
 957         MIPS_FPU_EMU_INC_STATS(emulated);
 958         switch (MIPSInst_OPCODE(ir)) {
 959         case ldc1_op:{
 960                 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 961                         MIPSInst_SIMM(ir));
 962                 u64 val;
 963
 964                 MIPS_FPU_EMU_INC_STATS(loads);
 965
 966                 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
 967                         MIPS_FPU_EMU_INC_STATS(errors);
 968                         *fault_addr = va;
 969                         return SIGBUS;
 970                 }
 971                 if (__get_user(val, va)) {
 972                         MIPS_FPU_EMU_INC_STATS(errors);
 973                         *fault_addr = va;
 974                         return SIGSEGV;
 975                 }
 976                 DITOREG(val, MIPSInst_RT(ir));
 977                 break;
 978         }
 979
 980         case sdc1_op:{
 981                 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 982                         MIPSInst_SIMM(ir));
 983                 u64 val;
 984
 985                 MIPS_FPU_EMU_INC_STATS(stores);
 986                 DIFROMREG(val, MIPSInst_RT(ir));
 987                 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
 988                         MIPS_FPU_EMU_INC_STATS(errors);
 989                         *fault_addr = va;
 990                         return SIGBUS;
 991                 }
 992                 if (__put_user(val, va)) {
 993                         MIPS_FPU_EMU_INC_STATS(errors);
 994                         *fault_addr = va;
 995                         return SIGSEGV;
 996                 }
 997                 break;
 998         }
 999
1000         case lwc1_op:{
1001                 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1002                         MIPSInst_SIMM(ir));
1003                 u32 val;
1004
1005                 MIPS_FPU_EMU_INC_STATS(loads);
1006                 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1007                         MIPS_FPU_EMU_INC_STATS(errors);
1008                         *fault_addr = va;
1009                         return SIGBUS;
1010                 }
1011                 if (__get_user(val, va)) {
1012                         MIPS_FPU_EMU_INC_STATS(errors);
1013                         *fault_addr = va;
1014                         return SIGSEGV;
1015                 }
1016                 SITOREG(val, MIPSInst_RT(ir));
1017                 break;
1018         }
1019
1020         case swc1_op:{
1021                 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1022                         MIPSInst_SIMM(ir));
1023                 u32 val;
1024
1025                 MIPS_FPU_EMU_INC_STATS(stores);
1026                 SIFROMREG(val, MIPSInst_RT(ir));
1027                 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1028                         MIPS_FPU_EMU_INC_STATS(errors);
1029                         *fault_addr = va;
1030                         return SIGBUS;
1031                 }
1032                 if (__put_user(val, va)) {
1033                         MIPS_FPU_EMU_INC_STATS(errors);
1034                         *fault_addr = va;
1035                         return SIGSEGV;
1036                 }
1037                 break;
1038         }
1039
1040         case cop1_op:
1041                 switch (MIPSInst_RS(ir)) {
1042
1043 #if defined(__mips64)
1044                 case dmfc_op:
1045                         /* copregister fs -> gpr[rt] */
1046                         if (MIPSInst_RT(ir) != 0) {
1047                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1048                                         MIPSInst_RD(ir));
1049                         }
1050                         break;
1051
1052                 case dmtc_op:
1053                         /* copregister fs <- rt */
1054                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1055                         break;
1056 #endif
1057
1058                 case mfc_op:
1059                         /* copregister rd -> gpr[rt] */
1060                         if (MIPSInst_RT(ir) != 0) {
1061                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1062                                         MIPSInst_RD(ir));
1063                         }
1064                         break;
1065
1066                 case mtc_op:
1067                         /* copregister rd <- rt */
1068                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1069                         break;
1070
1071                 case cfc_op:{
1072                         /* cop control register rd -> gpr[rt] */
1073                         u32 value;
1074
1075                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
1076                                 value = ctx->fcr31;
1077                                 value = (value & ~FPU_CSR_RM) |
1078                                         mips_rm[modeindex(value)];
1079 #ifdef CSRTRACE
1080                                 printk("%p gpr[%d]<-csr=%08x\n",
1081                                         (void *) (xcp->cp0_epc),
1082                                         MIPSInst_RT(ir), value);
1083 #endif
1084                         }
1085                         else if (MIPSInst_RD(ir) == FPCREG_RID)
1086                                 value = 0;
1087                         else
1088                                 value = 0;
1089                         if (MIPSInst_RT(ir))
1090                                 xcp->regs[MIPSInst_RT(ir)] = value;
1091                         break;
1092                 }
1093
1094                 case ctc_op:{
1095                         /* copregister rd <- rt */
1096                         u32 value;
1097
1098                         if (MIPSInst_RT(ir) == 0)
1099                                 value = 0;
1100                         else
1101                                 value = xcp->regs[MIPSInst_RT(ir)];
1102
1103                         /* we only have one writable control reg
1104                          */
1105                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
1106 #ifdef CSRTRACE
1107                                 printk("%p gpr[%d]->csr=%08x\n",
1108                                         (void *) (xcp->cp0_epc),
1109                                         MIPSInst_RT(ir), value);
1110 #endif
1111
1112                                 /*
1113                                  * Don't write reserved bits,
1114                                  * and convert to ieee library modes
1115                                  */
1116                                 ctx->fcr31 = (value &
1117                                                 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1118                                                 ieee_rm[modeindex(value)];
1119                         }
1120                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1121                                 return SIGFPE;
1122                         }
1123                         break;
1124                 }
1125
1126                 case bc_op:{
1127                         int likely = 0;
1128
1129                         if (xcp->cp0_cause & CAUSEF_BD)
1130                                 return SIGILL;
1131
1132 #if __mips >= 4
1133                         cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
1134 #else
1135                         cond = ctx->fcr31 & FPU_CSR_COND;
1136 #endif
1137                         switch (MIPSInst_RT(ir) & 3) {
1138                         case bcfl_op:
1139                                 likely = 1;
1140                         case bcf_op:
1141                                 cond = !cond;
1142                                 break;
1143                         case bctl_op:
1144                                 likely = 1;
1145                         case bct_op:
1146                                 break;
1147                         default:
1148                                 /* thats an illegal instruction */
1149                                 return SIGILL;
1150                         }
1151
1152                         xcp->cp0_cause |= CAUSEF_BD;
1153                         if (cond) {
1154                                 /* branch taken: emulate dslot
1155                                  * instruction
1156                                  */
1157                                 xcp->cp0_epc += dec_insn.pc_inc;
1158
1159                                 contpc = MIPSInst_SIMM(ir);
1160                                 ir = dec_insn.next_insn;
1161                                 if (dec_insn.micro_mips_mode) {
1162                                         contpc = (xcp->cp0_epc + (contpc << 1));
1163
1164                                         /* If 16-bit instruction, not FPU. */
1165                                         if ((dec_insn.next_pc_inc == 2) ||
1166                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1167
1168                                                 /*
1169                                                  * Since this instruction will
1170                                                  * be put on the stack with
1171                                                  * 32-bit words, get around
1172                                                  * this problem by putting a
1173                                                  * NOP16 as the second one.
1174                                                  */
1175                                                 if (dec_insn.next_pc_inc == 2)
1176                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1177
1178                                                 /*
1179                                                  * Single step the non-CP1
1180                                                  * instruction in the dslot.
1181                                                  */
1182                                                 return mips_dsemul(xcp, ir, contpc);
1183                                         }
1184                                 } else
1185                                         contpc = (xcp->cp0_epc + (contpc << 2));
1186
1187                                 switch (MIPSInst_OPCODE(ir)) {
1188                                 case lwc1_op:
1189                                 case swc1_op:
1190 #if (__mips >= 2 || defined(__mips64))
1191                                 case ldc1_op:
1192                                 case sdc1_op:
1193 #endif
1194                                 case cop1_op:
1195 #if __mips >= 4 && __mips != 32
1196                                 case cop1x_op:
1197 #endif
1198                                         /* its one of ours */
1199                                         goto emul;
1200 #if __mips >= 4
1201                                 case spec_op:
1202                                         if (MIPSInst_FUNC(ir) == movc_op)
1203                                                 goto emul;
1204                                         break;
1205 #endif
1206                                 }
1207
1208                                 /*
1209                                  * Single step the non-cp1
1210                                  * instruction in the dslot
1211                                  */
1212                                 return mips_dsemul(xcp, ir, contpc);
1213                         }
1214                         else {
1215                                 /* branch not taken */
1216                                 if (likely) {
1217                                         /*
1218                                          * branch likely nullifies
1219                                          * dslot if not taken
1220                                          */
1221                                         xcp->cp0_epc += dec_insn.pc_inc;
1222                                         contpc += dec_insn.pc_inc;
1223                                         /*
1224                                          * else continue & execute
1225                                          * dslot as normal insn
1226                                          */
1227                                 }
1228                         }
1229                         break;
1230                 }
1231
1232                 default:
1233                         if (!(MIPSInst_RS(ir) & 0x10))
1234                                 return SIGILL;
1235                         {
1236                                 int sig;
1237
1238                                 /* a real fpu computation instruction */
1239                                 if ((sig = fpu_emu(xcp, ctx, ir)))
1240                                         return sig;
1241                         }
1242                 }
1243                 break;
1244
1245 #if __mips >= 4 && __mips != 32
1246         case cop1x_op:{
1247                 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
1248                 if (sig)
1249                         return sig;
1250                 break;
1251         }
1252 #endif
1253
1254 #if __mips >= 4
1255         case spec_op:
1256                 if (MIPSInst_FUNC(ir) != movc_op)
1257                         return SIGILL;
1258                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1259                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1260                         xcp->regs[MIPSInst_RD(ir)] =
1261                                 xcp->regs[MIPSInst_RS(ir)];
1262                 break;
1263 #endif
1264
1265         default:
1266                 return SIGILL;
1267         }
1268
1269         /* we did it !! */
1270         xcp->cp0_epc = contpc;
1271         xcp->cp0_cause &= ~CAUSEF_BD;
1272
1273         return 0;
1274 }
1275
1276 /*
1277  * Conversion table from MIPS compare ops 48-63
1278  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1279  */
1280 static const unsigned char cmptab[8] = {
1281         0,                      /* cmp_0 (sig) cmp_sf */
1282         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1283         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1284         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1285         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1286         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1287         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1288         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1289 };
1290
1291
1292 #if __mips >= 4 && __mips != 32
1293
1294 /*
1295  * Additional MIPS4 instructions
1296  */
1297
1298 #define DEF3OP(name, p, f1, f2, f3) \
1299 static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
1300     ieee754##p t) \
1301 { \
1302         struct _ieee754_csr ieee754_csr_save; \
1303         s = f1(s, t); \
1304         ieee754_csr_save = ieee754_csr; \
1305         s = f2(s, r); \
1306         ieee754_csr_save.cx |= ieee754_csr.cx; \
1307         ieee754_csr_save.sx |= ieee754_csr.sx; \
1308         s = f3(s); \
1309         ieee754_csr.cx |= ieee754_csr_save.cx; \
1310         ieee754_csr.sx |= ieee754_csr_save.sx; \
1311         return s; \
1312 }
1313
1314 static ieee754dp fpemu_dp_recip(ieee754dp d)
1315 {
1316         return ieee754dp_div(ieee754dp_one(0), d);
1317 }
1318
1319 static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
1320 {
1321         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1322 }
1323
1324 static ieee754sp fpemu_sp_recip(ieee754sp s)
1325 {
1326         return ieee754sp_div(ieee754sp_one(0), s);
1327 }
1328
1329 static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
1330 {
1331         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1332 }
1333
1334 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1335 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1336 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1337 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1338 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1339 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1340 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1341 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1342
1343 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1344         mips_instruction ir, void *__user *fault_addr)
1345 {
1346         unsigned rcsr = 0;      /* resulting csr */
1347
1348         MIPS_FPU_EMU_INC_STATS(cp1xops);
1349
1350         switch (MIPSInst_FMA_FFMT(ir)) {
1351         case s_fmt:{            /* 0 */
1352
1353                 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
1354                 ieee754sp fd, fr, fs, ft;
1355                 u32 __user *va;
1356                 u32 val;
1357
1358                 switch (MIPSInst_FUNC(ir)) {
1359                 case lwxc1_op:
1360                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1361                                 xcp->regs[MIPSInst_FT(ir)]);
1362
1363                         MIPS_FPU_EMU_INC_STATS(loads);
1364                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1365                                 MIPS_FPU_EMU_INC_STATS(errors);
1366                                 *fault_addr = va;
1367                                 return SIGBUS;
1368                         }
1369                         if (__get_user(val, va)) {
1370                                 MIPS_FPU_EMU_INC_STATS(errors);
1371                                 *fault_addr = va;
1372                                 return SIGSEGV;
1373                         }
1374                         SITOREG(val, MIPSInst_FD(ir));
1375                         break;
1376
1377                 case swxc1_op:
1378                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1379                                 xcp->regs[MIPSInst_FT(ir)]);
1380
1381                         MIPS_FPU_EMU_INC_STATS(stores);
1382
1383                         SIFROMREG(val, MIPSInst_FS(ir));
1384                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1385                                 MIPS_FPU_EMU_INC_STATS(errors);
1386                                 *fault_addr = va;
1387                                 return SIGBUS;
1388                         }
1389                         if (put_user(val, va)) {
1390                                 MIPS_FPU_EMU_INC_STATS(errors);
1391                                 *fault_addr = va;
1392                                 return SIGSEGV;
1393                         }
1394                         break;
1395
1396                 case madd_s_op:
1397                         handler = fpemu_sp_madd;
1398                         goto scoptop;
1399                 case msub_s_op:
1400                         handler = fpemu_sp_msub;
1401                         goto scoptop;
1402                 case nmadd_s_op:
1403                         handler = fpemu_sp_nmadd;
1404                         goto scoptop;
1405                 case nmsub_s_op:
1406                         handler = fpemu_sp_nmsub;
1407                         goto scoptop;
1408
1409                       scoptop:
1410                         SPFROMREG(fr, MIPSInst_FR(ir));
1411                         SPFROMREG(fs, MIPSInst_FS(ir));
1412                         SPFROMREG(ft, MIPSInst_FT(ir));
1413                         fd = (*handler) (fr, fs, ft);
1414                         SPTOREG(fd, MIPSInst_FD(ir));
1415
1416                       copcsr:
1417                         if (ieee754_cxtest(IEEE754_INEXACT))
1418                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1419                         if (ieee754_cxtest(IEEE754_UNDERFLOW))
1420                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1421                         if (ieee754_cxtest(IEEE754_OVERFLOW))
1422                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1423                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1424                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1425
1426                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1427                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1428                                 /*printk ("SIGFPE: fpu csr = %08x\n",
1429                                    ctx->fcr31); */
1430                                 return SIGFPE;
1431                         }
1432
1433                         break;
1434
1435                 default:
1436                         return SIGILL;
1437                 }
1438                 break;
1439         }
1440
1441         case d_fmt:{            /* 1 */
1442                 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
1443                 ieee754dp fd, fr, fs, ft;
1444                 u64 __user *va;
1445                 u64 val;
1446
1447                 switch (MIPSInst_FUNC(ir)) {
1448                 case ldxc1_op:
1449                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1450                                 xcp->regs[MIPSInst_FT(ir)]);
1451
1452                         MIPS_FPU_EMU_INC_STATS(loads);
1453                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1454                                 MIPS_FPU_EMU_INC_STATS(errors);
1455                                 *fault_addr = va;
1456                                 return SIGBUS;
1457                         }
1458                         if (__get_user(val, va)) {
1459                                 MIPS_FPU_EMU_INC_STATS(errors);
1460                                 *fault_addr = va;
1461                                 return SIGSEGV;
1462                         }
1463                         DITOREG(val, MIPSInst_FD(ir));
1464                         break;
1465
1466                 case sdxc1_op:
1467                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1468                                 xcp->regs[MIPSInst_FT(ir)]);
1469
1470                         MIPS_FPU_EMU_INC_STATS(stores);
1471                         DIFROMREG(val, MIPSInst_FS(ir));
1472                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1473                                 MIPS_FPU_EMU_INC_STATS(errors);
1474                                 *fault_addr = va;
1475                                 return SIGBUS;
1476                         }
1477                         if (__put_user(val, va)) {
1478                                 MIPS_FPU_EMU_INC_STATS(errors);
1479                                 *fault_addr = va;
1480                                 return SIGSEGV;
1481                         }
1482                         break;
1483
1484                 case madd_d_op:
1485                         handler = fpemu_dp_madd;
1486                         goto dcoptop;
1487                 case msub_d_op:
1488                         handler = fpemu_dp_msub;
1489                         goto dcoptop;
1490                 case nmadd_d_op:
1491                         handler = fpemu_dp_nmadd;
1492                         goto dcoptop;
1493                 case nmsub_d_op:
1494                         handler = fpemu_dp_nmsub;
1495                         goto dcoptop;
1496
1497                       dcoptop:
1498                         DPFROMREG(fr, MIPSInst_FR(ir));
1499                         DPFROMREG(fs, MIPSInst_FS(ir));
1500                         DPFROMREG(ft, MIPSInst_FT(ir));
1501                         fd = (*handler) (fr, fs, ft);
1502                         DPTOREG(fd, MIPSInst_FD(ir));
1503                         goto copcsr;
1504
1505                 default:
1506                         return SIGILL;
1507                 }
1508                 break;
1509         }
1510
1511         case 0x7:               /* 7 */
1512                 if (MIPSInst_FUNC(ir) != pfetch_op) {
1513                         return SIGILL;
1514                 }
1515                 /* ignore prefx operation */
1516                 break;
1517
1518         default:
1519                 return SIGILL;
1520         }
1521
1522         return 0;
1523 }
1524 #endif
1525
1526
1527
1528 /*
1529  * Emulate a single COP1 arithmetic instruction.
1530  */
1531 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1532         mips_instruction ir)
1533 {
1534         int rfmt;               /* resulting format */
1535         unsigned rcsr = 0;      /* resulting csr */
1536         unsigned cond;
1537         union {
1538                 ieee754dp d;
1539                 ieee754sp s;
1540                 int w;
1541 #ifdef __mips64
1542                 s64 l;
1543 #endif
1544         } rv;                   /* resulting value */
1545
1546         MIPS_FPU_EMU_INC_STATS(cp1ops);
1547         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1548         case s_fmt:{            /* 0 */
1549                 union {
1550                         ieee754sp(*b) (ieee754sp, ieee754sp);
1551                         ieee754sp(*u) (ieee754sp);
1552                 } handler;
1553
1554                 switch (MIPSInst_FUNC(ir)) {
1555                         /* binary ops */
1556                 case fadd_op:
1557                         handler.b = ieee754sp_add;
1558                         goto scopbop;
1559                 case fsub_op:
1560                         handler.b = ieee754sp_sub;
1561                         goto scopbop;
1562                 case fmul_op:
1563                         handler.b = ieee754sp_mul;
1564                         goto scopbop;
1565                 case fdiv_op:
1566                         handler.b = ieee754sp_div;
1567                         goto scopbop;
1568
1569                         /* unary  ops */
1570 #if __mips >= 2 || defined(__mips64)
1571                 case fsqrt_op:
1572                         handler.u = ieee754sp_sqrt;
1573                         goto scopuop;
1574 #endif
1575 #if __mips >= 4 && __mips != 32
1576                 case frsqrt_op:
1577                         handler.u = fpemu_sp_rsqrt;
1578                         goto scopuop;
1579                 case frecip_op:
1580                         handler.u = fpemu_sp_recip;
1581                         goto scopuop;
1582 #endif
1583 #if __mips >= 4
1584                 case fmovc_op:
1585                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1586                         if (((ctx->fcr31 & cond) != 0) !=
1587                                 ((MIPSInst_FT(ir) & 1) != 0))
1588                                 return 0;
1589                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1590                         break;
1591                 case fmovz_op:
1592                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1593                                 return 0;
1594                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1595                         break;
1596                 case fmovn_op:
1597                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1598                                 return 0;
1599                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1600                         break;
1601 #endif
1602                 case fabs_op:
1603                         handler.u = ieee754sp_abs;
1604                         goto scopuop;
1605                 case fneg_op:
1606                         handler.u = ieee754sp_neg;
1607                         goto scopuop;
1608                 case fmov_op:
1609                         /* an easy one */
1610                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1611                         goto copcsr;
1612
1613                         /* binary op on handler */
1614                       scopbop:
1615                         {
1616                                 ieee754sp fs, ft;
1617
1618                                 SPFROMREG(fs, MIPSInst_FS(ir));
1619                                 SPFROMREG(ft, MIPSInst_FT(ir));
1620
1621                                 rv.s = (*handler.b) (fs, ft);
1622                                 goto copcsr;
1623                         }
1624                       scopuop:
1625                         {
1626                                 ieee754sp fs;
1627
1628                                 SPFROMREG(fs, MIPSInst_FS(ir));
1629                                 rv.s = (*handler.u) (fs);
1630                                 goto copcsr;
1631                         }
1632                       copcsr:
1633                         if (ieee754_cxtest(IEEE754_INEXACT))
1634                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1635                         if (ieee754_cxtest(IEEE754_UNDERFLOW))
1636                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1637                         if (ieee754_cxtest(IEEE754_OVERFLOW))
1638                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1639                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
1640                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1641                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1642                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1643                         break;
1644
1645                         /* unary conv ops */
1646                 case fcvts_op:
1647                         return SIGILL;  /* not defined */
1648                 case fcvtd_op:{
1649                         ieee754sp fs;
1650
1651                         SPFROMREG(fs, MIPSInst_FS(ir));
1652                         rv.d = ieee754dp_fsp(fs);
1653                         rfmt = d_fmt;
1654                         goto copcsr;
1655                 }
1656                 case fcvtw_op:{
1657                         ieee754sp fs;
1658
1659                         SPFROMREG(fs, MIPSInst_FS(ir));
1660                         rv.w = ieee754sp_tint(fs);
1661                         rfmt = w_fmt;
1662                         goto copcsr;
1663                 }
1664
1665 #if __mips >= 2 || defined(__mips64)
1666                 case fround_op:
1667                 case ftrunc_op:
1668                 case fceil_op:
1669                 case ffloor_op:{
1670                         unsigned int oldrm = ieee754_csr.rm;
1671                         ieee754sp fs;
1672
1673                         SPFROMREG(fs, MIPSInst_FS(ir));
1674                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1675                         rv.w = ieee754sp_tint(fs);
1676                         ieee754_csr.rm = oldrm;
1677                         rfmt = w_fmt;
1678                         goto copcsr;
1679                 }
1680 #endif /* __mips >= 2 */
1681
1682 #if defined(__mips64)
1683                 case fcvtl_op:{
1684                         ieee754sp fs;
1685
1686                         SPFROMREG(fs, MIPSInst_FS(ir));
1687                         rv.l = ieee754sp_tlong(fs);
1688                         rfmt = l_fmt;
1689                         goto copcsr;
1690                 }
1691
1692                 case froundl_op:
1693                 case ftruncl_op:
1694                 case fceill_op:
1695                 case ffloorl_op:{
1696                         unsigned int oldrm = ieee754_csr.rm;
1697                         ieee754sp fs;
1698
1699                         SPFROMREG(fs, MIPSInst_FS(ir));
1700                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1701                         rv.l = ieee754sp_tlong(fs);
1702                         ieee754_csr.rm = oldrm;
1703                         rfmt = l_fmt;
1704                         goto copcsr;
1705                 }
1706 #endif /* defined(__mips64) */
1707
1708                 default:
1709                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1710                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1711                                 ieee754sp fs, ft;
1712
1713                                 SPFROMREG(fs, MIPSInst_FS(ir));
1714                                 SPFROMREG(ft, MIPSInst_FT(ir));
1715                                 rv.w = ieee754sp_cmp(fs, ft,
1716                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1717                                 rfmt = -1;
1718                                 if ((cmpop & 0x8) && ieee754_cxtest
1719                                         (IEEE754_INVALID_OPERATION))
1720                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1721                                 else
1722                                         goto copcsr;
1723
1724                         }
1725                         else {
1726                                 return SIGILL;
1727                         }
1728                         break;
1729                 }
1730                 break;
1731         }
1732
1733         case d_fmt:{
1734                 union {
1735                         ieee754dp(*b) (ieee754dp, ieee754dp);
1736                         ieee754dp(*u) (ieee754dp);
1737                 } handler;
1738
1739                 switch (MIPSInst_FUNC(ir)) {
1740                         /* binary ops */
1741                 case fadd_op:
1742                         handler.b = ieee754dp_add;
1743                         goto dcopbop;
1744                 case fsub_op:
1745                         handler.b = ieee754dp_sub;
1746                         goto dcopbop;
1747                 case fmul_op:
1748                         handler.b = ieee754dp_mul;
1749                         goto dcopbop;
1750                 case fdiv_op:
1751                         handler.b = ieee754dp_div;
1752                         goto dcopbop;
1753
1754                         /* unary  ops */
1755 #if __mips >= 2 || defined(__mips64)
1756                 case fsqrt_op:
1757                         handler.u = ieee754dp_sqrt;
1758                         goto dcopuop;
1759 #endif
1760 #if __mips >= 4 && __mips != 32
1761                 case frsqrt_op:
1762                         handler.u = fpemu_dp_rsqrt;
1763                         goto dcopuop;
1764                 case frecip_op:
1765                         handler.u = fpemu_dp_recip;
1766                         goto dcopuop;
1767 #endif
1768 #if __mips >= 4
1769                 case fmovc_op:
1770                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1771                         if (((ctx->fcr31 & cond) != 0) !=
1772                                 ((MIPSInst_FT(ir) & 1) != 0))
1773                                 return 0;
1774                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1775                         break;
1776                 case fmovz_op:
1777                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1778                                 return 0;
1779                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1780                         break;
1781                 case fmovn_op:
1782                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1783                                 return 0;
1784                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1785                         break;
1786 #endif
1787                 case fabs_op:
1788                         handler.u = ieee754dp_abs;
1789                         goto dcopuop;
1790
1791                 case fneg_op:
1792                         handler.u = ieee754dp_neg;
1793                         goto dcopuop;
1794
1795                 case fmov_op:
1796                         /* an easy one */
1797                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1798                         goto copcsr;
1799
1800                         /* binary op on handler */
1801                       dcopbop:{
1802                                 ieee754dp fs, ft;
1803
1804                                 DPFROMREG(fs, MIPSInst_FS(ir));
1805                                 DPFROMREG(ft, MIPSInst_FT(ir));
1806
1807                                 rv.d = (*handler.b) (fs, ft);
1808                                 goto copcsr;
1809                         }
1810                       dcopuop:{
1811                                 ieee754dp fs;
1812
1813                                 DPFROMREG(fs, MIPSInst_FS(ir));
1814                                 rv.d = (*handler.u) (fs);
1815                                 goto copcsr;
1816                         }
1817
1818                         /* unary conv ops */
1819                 case fcvts_op:{
1820                         ieee754dp fs;
1821
1822                         DPFROMREG(fs, MIPSInst_FS(ir));
1823                         rv.s = ieee754sp_fdp(fs);
1824                         rfmt = s_fmt;
1825                         goto copcsr;
1826                 }
1827                 case fcvtd_op:
1828                         return SIGILL;  /* not defined */
1829
1830                 case fcvtw_op:{
1831                         ieee754dp fs;
1832
1833                         DPFROMREG(fs, MIPSInst_FS(ir));
1834                         rv.w = ieee754dp_tint(fs);      /* wrong */
1835                         rfmt = w_fmt;
1836                         goto copcsr;
1837                 }
1838
1839 #if __mips >= 2 || defined(__mips64)
1840                 case fround_op:
1841                 case ftrunc_op:
1842                 case fceil_op:
1843                 case ffloor_op:{
1844                         unsigned int oldrm = ieee754_csr.rm;
1845                         ieee754dp fs;
1846
1847                         DPFROMREG(fs, MIPSInst_FS(ir));
1848                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1849                         rv.w = ieee754dp_tint(fs);
1850                         ieee754_csr.rm = oldrm;
1851                         rfmt = w_fmt;
1852                         goto copcsr;
1853                 }
1854 #endif
1855
1856 #if defined(__mips64)
1857                 case fcvtl_op:{
1858                         ieee754dp fs;
1859
1860                         DPFROMREG(fs, MIPSInst_FS(ir));
1861                         rv.l = ieee754dp_tlong(fs);
1862                         rfmt = l_fmt;
1863                         goto copcsr;
1864                 }
1865
1866                 case froundl_op:
1867                 case ftruncl_op:
1868                 case fceill_op:
1869                 case ffloorl_op:{
1870                         unsigned int oldrm = ieee754_csr.rm;
1871                         ieee754dp fs;
1872
1873                         DPFROMREG(fs, MIPSInst_FS(ir));
1874                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1875                         rv.l = ieee754dp_tlong(fs);
1876                         ieee754_csr.rm = oldrm;
1877                         rfmt = l_fmt;
1878                         goto copcsr;
1879                 }
1880 #endif /* __mips >= 3 */
1881
1882                 default:
1883                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1884                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1885                                 ieee754dp fs, ft;
1886
1887                                 DPFROMREG(fs, MIPSInst_FS(ir));
1888                                 DPFROMREG(ft, MIPSInst_FT(ir));
1889                                 rv.w = ieee754dp_cmp(fs, ft,
1890                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1891                                 rfmt = -1;
1892                                 if ((cmpop & 0x8)
1893                                         &&
1894                                         ieee754_cxtest
1895                                         (IEEE754_INVALID_OPERATION))
1896                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1897                                 else
1898                                         goto copcsr;
1899
1900                         }
1901                         else {
1902                                 return SIGILL;
1903                         }
1904                         break;
1905                 }
1906                 break;
1907         }
1908
1909         case w_fmt:{
1910                 ieee754sp fs;
1911
1912                 switch (MIPSInst_FUNC(ir)) {
1913                 case fcvts_op:
1914                         /* convert word to single precision real */
1915                         SPFROMREG(fs, MIPSInst_FS(ir));
1916                         rv.s = ieee754sp_fint(fs.bits);
1917                         rfmt = s_fmt;
1918                         goto copcsr;
1919                 case fcvtd_op:
1920                         /* convert word to double precision real */
1921                         SPFROMREG(fs, MIPSInst_FS(ir));
1922                         rv.d = ieee754dp_fint(fs.bits);
1923                         rfmt = d_fmt;
1924                         goto copcsr;
1925                 default:
1926                         return SIGILL;
1927                 }
1928                 break;
1929         }
1930
1931 #if defined(__mips64)
1932         case l_fmt:{
1933                 switch (MIPSInst_FUNC(ir)) {
1934                 case fcvts_op:
1935                         /* convert long to single precision real */
1936                         rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1937                         rfmt = s_fmt;
1938                         goto copcsr;
1939                 case fcvtd_op:
1940                         /* convert long to double precision real */
1941                         rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1942                         rfmt = d_fmt;
1943                         goto copcsr;
1944                 default:
1945                         return SIGILL;
1946                 }
1947                 break;
1948         }
1949 #endif
1950
1951         default:
1952                 return SIGILL;
1953         }
1954
1955         /*
1956          * Update the fpu CSR register for this operation.
1957          * If an exception is required, generate a tidy SIGFPE exception,
1958          * without updating the result register.
1959          * Note: cause exception bits do not accumulate, they are rewritten
1960          * for each op; only the flag/sticky bits accumulate.
1961          */
1962         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1963         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1964                 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1965                 return SIGFPE;
1966         }
1967
1968         /*
1969          * Now we can safely write the result back to the register file.
1970          */
1971         switch (rfmt) {
1972         case -1:{
1973 #if __mips >= 4
1974                 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1975 #else
1976                 cond = FPU_CSR_COND;
1977 #endif
1978                 if (rv.w)
1979                         ctx->fcr31 |= cond;
1980                 else
1981                         ctx->fcr31 &= ~cond;
1982                 break;
1983         }
1984         case d_fmt:
1985                 DPTOREG(rv.d, MIPSInst_FD(ir));
1986                 break;
1987         case s_fmt:
1988                 SPTOREG(rv.s, MIPSInst_FD(ir));
1989                 break;
1990         case w_fmt:
1991                 SITOREG(rv.w, MIPSInst_FD(ir));
1992                 break;
1993 #if defined(__mips64)
1994         case l_fmt:
1995                 DITOREG(rv.l, MIPSInst_FD(ir));
1996                 break;
1997 #endif
1998         default:
1999                 return SIGILL;
2000         }
2001
2002         return 0;
2003 }
2004
2005 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2006         int has_fpu, void *__user *fault_addr)
2007 {
2008         unsigned long oldepc, prevepc;
2009         struct mm_decoded_insn dec_insn;
2010         u16 instr[4];
2011         u16 *instr_ptr;
2012         int sig = 0;
2013
2014         oldepc = xcp->cp0_epc;
2015         do {
2016                 prevepc = xcp->cp0_epc;
2017
2018                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2019                         /*
2020                          * Get next 2 microMIPS instructions and convert them
2021                          * into 32-bit instructions.
2022                          */
2023                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2024                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2025                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2026                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2027                                 MIPS_FPU_EMU_INC_STATS(errors);
2028                                 return SIGBUS;
2029                         }
2030                         instr_ptr = instr;
2031
2032                         /* Get first instruction. */
2033                         if (mm_insn_16bit(*instr_ptr)) {
2034                                 /* Duplicate the half-word. */
2035                                 dec_insn.insn = (*instr_ptr << 16) |
2036                                         (*instr_ptr);
2037                                 /* 16-bit instruction. */
2038                                 dec_insn.pc_inc = 2;
2039                                 instr_ptr += 1;
2040                         } else {
2041                                 dec_insn.insn = (*instr_ptr << 16) |
2042                                         *(instr_ptr+1);
2043                                 /* 32-bit instruction. */
2044                                 dec_insn.pc_inc = 4;
2045                                 instr_ptr += 2;
2046                         }
2047                         /* Get second instruction. */
2048                         if (mm_insn_16bit(*instr_ptr)) {
2049                                 /* Duplicate the half-word. */
2050                                 dec_insn.next_insn = (*instr_ptr << 16) |
2051                                         (*instr_ptr);
2052                                 /* 16-bit instruction. */
2053                                 dec_insn.next_pc_inc = 2;
2054                         } else {
2055                                 dec_insn.next_insn = (*instr_ptr << 16) |
2056                                         *(instr_ptr+1);
2057                                 /* 32-bit instruction. */
2058                                 dec_insn.next_pc_inc = 4;
2059                         }
2060                         dec_insn.micro_mips_mode = 1;
2061                 } else {
2062                         if ((get_user(dec_insn.insn,
2063                             (mips_instruction __user *) xcp->cp0_epc)) ||
2064                             (get_user(dec_insn.next_insn,
2065                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2066                                 MIPS_FPU_EMU_INC_STATS(errors);
2067                                 return SIGBUS;
2068                         }
2069                         dec_insn.pc_inc = 4;
2070                         dec_insn.next_pc_inc = 4;
2071                         dec_insn.micro_mips_mode = 0;
2072                 }
2073
2074                 if ((dec_insn.insn == 0) ||
2075                    ((dec_insn.pc_inc == 2) &&
2076                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
2077                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
2078                 else {
2079                         /*
2080                          * The 'ieee754_csr' is an alias of
2081                          * ctx->fcr31.  No need to copy ctx->fcr31 to
2082                          * ieee754_csr.  But ieee754_csr.rm is ieee
2083                          * library modes. (not mips rounding mode)
2084                          */
2085                         /* convert to ieee library modes */
2086                         ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
2087                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2088                         /* revert to mips rounding mode */
2089                         ieee754_csr.rm = mips_rm[ieee754_csr.rm];
2090                 }
2091
2092                 if (has_fpu)
2093                         break;
2094                 if (sig)
2095                         break;
2096
2097                 cond_resched();
2098         } while (xcp->cp0_epc > prevepc);
2099
2100         /* SIGILL indicates a non-fpu instruction */
2101         if (sig == SIGILL && xcp->cp0_epc != oldepc)
2102                 /* but if epc has advanced, then ignore it */
2103                 sig = 0;
2104
2105         return sig;
2106 }
2107
2108 #ifdef CONFIG_DEBUG_FS
2109
2110 static int fpuemu_stat_get(void *data, u64 *val)
2111 {
2112         int cpu;
2113         unsigned long sum = 0;
2114         for_each_online_cpu(cpu) {
2115                 struct mips_fpu_emulator_stats *ps;
2116                 local_t *pv;
2117                 ps = &per_cpu(fpuemustats, cpu);
2118                 pv = (void *)ps + (unsigned long)data;
2119                 sum += local_read(pv);
2120         }
2121         *val = sum;
2122         return 0;
2123 }
2124 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
2125
2126 extern struct dentry *mips_debugfs_dir;
2127 static int __init debugfs_fpuemu(void)
2128 {
2129         struct dentry *d, *dir;
2130
2131         if (!mips_debugfs_dir)
2132                 return -ENODEV;
2133         dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
2134         if (!dir)
2135                 return -ENOMEM;
2136
2137 #define FPU_STAT_CREATE(M)                                              \
2138         do {                                                            \
2139                 d = debugfs_create_file(#M , S_IRUGO, dir,              \
2140                         (void *)offsetof(struct mips_fpu_emulator_stats, M), \
2141                         &fops_fpuemu_stat);                             \
2142                 if (!d)                                                 \
2143                         return -ENOMEM;                                 \
2144         } while (0)
2145
2146         FPU_STAT_CREATE(emulated);
2147         FPU_STAT_CREATE(loads);
2148         FPU_STAT_CREATE(stores);
2149         FPU_STAT_CREATE(cp1ops);
2150         FPU_STAT_CREATE(cp1xops);
2151         FPU_STAT_CREATE(errors);
2152
2153         return 0;
2154 }
2155 __initcall(debugfs_fpuemu);
2156 #endif