Pileus Git - ~andy/linux/blob - arch/mips/kernel/ptrace32.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1992 Ross Biro
   7  * Copyright (C) Linus Torvalds
   8  * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
   9  * Copyright (C) 1996 David S. Miller
  10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  11  * Copyright (C) 1999 MIPS Technologies, Inc.
  12  * Copyright (C) 2000 Ulf Carlsson
  13  *
  14  * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
  15  * binaries.
  16  */
  17 #include <linux/compiler.h>
  18 #include <linux/compat.h>
  19 #include <linux/kernel.h>
  20 #include <linux/sched.h>
  21 #include <linux/mm.h>
  22 #include <linux/errno.h>
  23 #include <linux/ptrace.h>
  24 #include <linux/smp.h>
  25 #include <linux/user.h>
  26 #include <linux/security.h>
  27
  28 #include <asm/cpu.h>
  29 #include <asm/dsp.h>
  30 #include <asm/fpu.h>
  31 #include <asm/mipsregs.h>
  32 #include <asm/mipsmtregs.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/page.h>
  35 #include <asm/uaccess.h>
  36 #include <asm/bootinfo.h>
  37
  38 /*
  39  * Tracing a 32-bit process with a 64-bit strace and vice versa will not
  40  * work.  I don't know how to fix this.
  41  */
  42 long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
  43                         compat_ulong_t caddr, compat_ulong_t cdata)
  44 {
  45         int addr = caddr;
  46         int data = cdata;
  47         int ret;
  48
  49         switch (request) {
  50
  51         /*
  52          * Read 4 bytes of the other process' storage
  53          *  data is a pointer specifying where the user wants the
  54          *      4 bytes copied into
  55          *  addr is a pointer in the user's storage that contains an 8 byte
  56          *      address in the other process of the 4 bytes that is to be read
  57          * (this is run in a 32-bit process looking at a 64-bit process)
  58          * when I and D space are separate, these will need to be fixed.
  59          */
  60         case PTRACE_PEEKTEXT_3264:
  61         case PTRACE_PEEKDATA_3264: {
  62                 u32 tmp;
  63                 int copied;
  64                 u32 __user * addrOthers;
  65
  66                 ret = -EIO;
  67
  68                 /* Get the addr in the other process that we want to read */
  69                 if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
  70                         break;
  71
  72                 copied = access_process_vm(child, (u64)addrOthers, &tmp,
  73                                 sizeof(tmp), 0);
  74                 if (copied != sizeof(tmp))
  75                         break;
  76                 ret = put_user(tmp, (u32 __user *) (unsigned long) data);
  77                 break;
  78         }
  79
  80         /* Read the word at location addr in the USER area. */
  81         case PTRACE_PEEKUSR: {
  82                 struct pt_regs *regs;
  83                 fpureg_t *fregs;
  84                 unsigned int tmp;
  85
  86                 regs = task_pt_regs(child);
  87                 ret = 0;  /* Default return value. */
  88
  89                 switch (addr) {
  90                 case 0 ... 31:
  91                         tmp = regs->regs[addr];
  92                         break;
  93                 case FPR_BASE ... FPR_BASE + 31:
  94                         if (!tsk_used_math(child)) {
  95                                 /* FP not yet used */
  96                                 tmp = -1;
  97                                 break;
  98                         }
  99                         fregs = get_fpu_regs(child);
 100                         if (test_thread_flag(TIF_32BIT_FPREGS)) {
 101                                 /*
 102                                  * The odd registers are actually the high
 103                                  * order bits of the values stored in the even
 104                                  * registers - unless we're using r2k_switch.S.
 105                                  */
 106                                 if (addr & 1)
 107                                         tmp = fregs[(addr & ~1) - 32] >> 32;
 108                                 else
 109                                         tmp = fregs[addr - 32];
 110                                 break;
 111                         }
 112                         tmp = fregs[addr - FPR_BASE];
 113                         break;
 114                 case PC:
 115                         tmp = regs->cp0_epc;
 116                         break;
 117                 case CAUSE:
 118                         tmp = regs->cp0_cause;
 119                         break;
 120                 case BADVADDR:
 121                         tmp = regs->cp0_badvaddr;
 122                         break;
 123                 case MMHI:
 124                         tmp = regs->hi;
 125                         break;
 126                 case MMLO:
 127                         tmp = regs->lo;
 128                         break;
 129                 case FPC_CSR:
 130                         tmp = child->thread.fpu.fcr31;
 131                         break;
 132                 case FPC_EIR: { /* implementation / version register */
 133                         unsigned int flags;
 134 #ifdef CONFIG_MIPS_MT_SMTC
 135                         unsigned int irqflags;
 136                         unsigned int mtflags;
 137 #endif /* CONFIG_MIPS_MT_SMTC */
 138
 139                         preempt_disable();
 140                         if (!cpu_has_fpu) {
 141                                 preempt_enable();
 142                                 tmp = 0;
 143                                 break;
 144                         }
 145
 146 #ifdef CONFIG_MIPS_MT_SMTC
 147                         /* Read-modify-write of Status must be atomic */
 148                         local_irq_save(irqflags);
 149                         mtflags = dmt();
 150 #endif /* CONFIG_MIPS_MT_SMTC */
 151
 152                         if (cpu_has_mipsmt) {
 153                                 unsigned int vpflags = dvpe();
 154                                 flags = read_c0_status();
 155                                 __enable_fpu(FPU_AS_IS);
 156                                 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
 157                                 write_c0_status(flags);
 158                                 evpe(vpflags);
 159                         } else {
 160                                 flags = read_c0_status();
 161                                 __enable_fpu(FPU_AS_IS);
 162                                 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
 163                                 write_c0_status(flags);
 164                         }
 165 #ifdef CONFIG_MIPS_MT_SMTC
 166                         emt(mtflags);
 167                         local_irq_restore(irqflags);
 168 #endif /* CONFIG_MIPS_MT_SMTC */
 169                         preempt_enable();
 170                         break;
 171                 }
 172                 case DSP_BASE ... DSP_BASE + 5: {
 173                         dspreg_t *dregs;
 174
 175                         if (!cpu_has_dsp) {
 176                                 tmp = 0;
 177                                 ret = -EIO;
 178                                 goto out;
 179                         }
 180                         dregs = __get_dsp_regs(child);
 181                         tmp = (unsigned long) (dregs[addr - DSP_BASE]);
 182                         break;
 183                 }
 184                 case DSP_CONTROL:
 185                         if (!cpu_has_dsp) {
 186                                 tmp = 0;
 187                                 ret = -EIO;
 188                                 goto out;
 189                         }
 190                         tmp = child->thread.dsp.dspcontrol;
 191                         break;
 192                 default:
 193                         tmp = 0;
 194                         ret = -EIO;
 195                         goto out;
 196                 }
 197                 ret = put_user(tmp, (unsigned __user *) (unsigned long) data);
 198                 break;
 199         }
 200
 201         /*
 202          * Write 4 bytes into the other process' storage
 203          *  data is the 4 bytes that the user wants written
 204          *  addr is a pointer in the user's storage that contains an
 205          *      8 byte address in the other process where the 4 bytes
 206          *      that is to be written
 207          * (this is run in a 32-bit process looking at a 64-bit process)
 208          * when I and D space are separate, these will need to be fixed.
 209          */
 210         case PTRACE_POKETEXT_3264:
 211         case PTRACE_POKEDATA_3264: {
 212                 u32 __user * addrOthers;
 213
 214                 /* Get the addr in the other process that we want to write into */
 215                 ret = -EIO;
 216                 if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
 217                         break;
 218                 ret = 0;
 219                 if (access_process_vm(child, (u64)addrOthers, &data,
 220                                         sizeof(data), 1) == sizeof(data))
 221                         break;
 222                 ret = -EIO;
 223                 break;
 224         }
 225
 226         case PTRACE_POKEUSR: {
 227                 struct pt_regs *regs;
 228                 ret = 0;
 229                 regs = task_pt_regs(child);
 230
 231                 switch (addr) {
 232                 case 0 ... 31:
 233                         regs->regs[addr] = data;
 234                         break;
 235                 case FPR_BASE ... FPR_BASE + 31: {
 236                         fpureg_t *fregs = get_fpu_regs(child);
 237
 238                         if (!tsk_used_math(child)) {
 239                                 /* FP not yet used  */
 240                                 memset(&child->thread.fpu, ~0,
 241                                        sizeof(child->thread.fpu));
 242                                 child->thread.fpu.fcr31 = 0;
 243                         }
 244                         if (test_thread_flag(TIF_32BIT_FPREGS)) {
 245                                 /*
 246                                  * The odd registers are actually the high
 247                                  * order bits of the values stored in the even
 248                                  * registers - unless we're using r2k_switch.S.
 249                                  */
 250                                 if (addr & 1) {
 251                                         fregs[(addr & ~1) - FPR_BASE] &=
 252                                                 0xffffffff;
 253                                         fregs[(addr & ~1) - FPR_BASE] |=
 254                                                 ((u64)data) << 32;
 255                                 } else {
 256                                         fregs[addr - FPR_BASE] &= ~0xffffffffLL;
 257                                         fregs[addr - FPR_BASE] |= data;
 258                                 }
 259                                 break;
 260                         }
 261                         fregs[addr - FPR_BASE] = data;
 262                         break;
 263                 }
 264                 case PC:
 265                         regs->cp0_epc = data;
 266                         break;
 267                 case MMHI:
 268                         regs->hi = data;
 269                         break;
 270                 case MMLO:
 271                         regs->lo = data;
 272                         break;
 273                 case FPC_CSR:
 274                         child->thread.fpu.fcr31 = data;
 275                         break;
 276                 case DSP_BASE ... DSP_BASE + 5: {
 277                         dspreg_t *dregs;
 278
 279                         if (!cpu_has_dsp) {
 280                                 ret = -EIO;
 281                                 break;
 282                         }
 283
 284                         dregs = __get_dsp_regs(child);
 285                         dregs[addr - DSP_BASE] = data;
 286                         break;
 287                 }
 288                 case DSP_CONTROL:
 289                         if (!cpu_has_dsp) {
 290                                 ret = -EIO;
 291                                 break;
 292                         }
 293                         child->thread.dsp.dspcontrol = data;
 294                         break;
 295                 default:
 296                         /* The rest are not allowed. */
 297                         ret = -EIO;
 298                         break;
 299                 }
 300                 break;
 301                 }
 302
 303         case PTRACE_GETREGS:
 304                 ret = ptrace_getregs(child, (__s64 __user *) (__u64) data);
 305                 break;
 306
 307         case PTRACE_SETREGS:
 308                 ret = ptrace_setregs(child, (__s64 __user *) (__u64) data);
 309                 break;
 310
 311         case PTRACE_GETFPREGS:
 312                 ret = ptrace_getfpregs(child, (__u32 __user *) (__u64) data);
 313                 break;
 314
 315         case PTRACE_SETFPREGS:
 316                 ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
 317                 break;
 318
 319         case PTRACE_GET_THREAD_AREA:
 320                 ret = put_user(task_thread_info(child)->tp_value,
 321                                 (unsigned int __user *) (unsigned long) data);
 322                 break;
 323
 324         case PTRACE_GET_THREAD_AREA_3264:
 325                 ret = put_user(task_thread_info(child)->tp_value,
 326                                 (unsigned long __user *) (unsigned long) data);
 327                 break;
 328
 329         case PTRACE_GET_WATCH_REGS:
 330                 ret = ptrace_get_watch_regs(child,
 331                         (struct pt_watch_regs __user *) (unsigned long) addr);
 332                 break;
 333
 334         case PTRACE_SET_WATCH_REGS:
 335                 ret = ptrace_set_watch_regs(child,
 336                         (struct pt_watch_regs __user *) (unsigned long) addr);
 337                 break;
 338
 339         default:
 340                 ret = compat_ptrace_request(child, request, addr, data);
 341                 break;
 342         }
 343 out:
 344         return ret;
 345 }