Pileus Git - ~andy/linux/blob - arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/fpu.h>
  24 #include <asm/mipsregs.h>
  25 #include <asm/watch.h>
  26 #include <asm/elf.h>
  27 #include <asm/spram.h>
  28 #include <asm/uaccess.h>
  29
  30 /*
  31  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  32  * the implementation of the "wait" feature differs between CPU families. This
  33  * points to the function that implements CPU specific wait.
  34  * The wait instruction stops the pipeline and reduces the power consumption of
  35  * the CPU very much.
  36  */
  37 void (*cpu_wait)(void);
  38 EXPORT_SYMBOL(cpu_wait);
  39
  40 static void r3081_wait(void)
  41 {
  42         unsigned long cfg = read_c0_conf();
  43         write_c0_conf(cfg | R30XX_CONF_HALT);
  44 }
  45
  46 static void r39xx_wait(void)
  47 {
  48         local_irq_disable();
  49         if (!need_resched())
  50                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  51         local_irq_enable();
  52 }
  53
  54 extern void r4k_wait(void);
  55
  56 /*
  57  * This variant is preferable as it allows testing need_resched and going to
  58  * sleep depending on the outcome atomically.  Unfortunately the "It is
  59  * implementation-dependent whether the pipeline restarts when a non-enabled
  60  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  61  * using this version a gamble.
  62  */
  63 void r4k_wait_irqoff(void)
  64 {
  65         local_irq_disable();
  66         if (!need_resched())
  67                 __asm__("       .set    push            \n"
  68                         "       .set    mips3           \n"
  69                         "       wait                    \n"
  70                         "       .set    pop             \n");
  71         local_irq_enable();
  72         __asm__("       .globl __pastwait       \n"
  73                 "__pastwait:                    \n");
  74 }
  75
  76 /*
  77  * The RM7000 variant has to handle erratum 38.  The workaround is to not
  78  * have any pending stores when the WAIT instruction is executed.
  79  */
  80 static void rm7k_wait_irqoff(void)
  81 {
  82         local_irq_disable();
  83         if (!need_resched())
  84                 __asm__(
  85                 "       .set    push                                    \n"
  86                 "       .set    mips3                                   \n"
  87                 "       .set    noat                                    \n"
  88                 "       mfc0    $1, $12                                 \n"
  89                 "       sync                                            \n"
  90                 "       mtc0    $1, $12         # stalls until W stage  \n"
  91                 "       wait                                            \n"
  92                 "       mtc0    $1, $12         # stalls until W stage  \n"
  93                 "       .set    pop                                     \n");
  94         local_irq_enable();
  95 }
  96
  97 /*
  98  * The Au1xxx wait is available only if using 32khz counter or
  99  * external timer source, but specifically not CP0 Counter.
 100  * alchemy/common/time.c may override cpu_wait!
 101  */
 102 static void au1k_wait(void)
 103 {
 104         __asm__("       .set    mips3                   \n"
 105                 "       cache   0x14, 0(%0)             \n"
 106                 "       cache   0x14, 32(%0)            \n"
 107                 "       sync                            \n"
 108                 "       nop                             \n"
 109                 "       wait                            \n"
 110                 "       nop                             \n"
 111                 "       nop                             \n"
 112                 "       nop                             \n"
 113                 "       nop                             \n"
 114                 "       .set    mips0                   \n"
 115                 : : "r" (au1k_wait));
 116 }
 117
 118 static int __initdata nowait;
 119
 120 static int __init wait_disable(char *s)
 121 {
 122         nowait = 1;
 123
 124         return 1;
 125 }
 126
 127 __setup("nowait", wait_disable);
 128
 129 static int __cpuinitdata mips_fpu_disabled;
 130
 131 static int __init fpu_disable(char *s)
 132 {
 133         cpu_data[0].options &= ~MIPS_CPU_FPU;
 134         mips_fpu_disabled = 1;
 135
 136         return 1;
 137 }
 138
 139 __setup("nofpu", fpu_disable);
 140
 141 int __cpuinitdata mips_dsp_disabled;
 142
 143 static int __init dsp_disable(char *s)
 144 {
 145         cpu_data[0].ases &= ~MIPS_ASE_DSP;
 146         mips_dsp_disabled = 1;
 147
 148         return 1;
 149 }
 150
 151 __setup("nodsp", dsp_disable);
 152
 153 void __init check_wait(void)
 154 {
 155         struct cpuinfo_mips *c = &current_cpu_data;
 156
 157         if (nowait) {
 158                 printk("Wait instruction disabled.\n");
 159                 return;
 160         }
 161
 162         switch (c->cputype) {
 163         case CPU_R3081:
 164         case CPU_R3081E:
 165                 cpu_wait = r3081_wait;
 166                 break;
 167         case CPU_TX3927:
 168                 cpu_wait = r39xx_wait;
 169                 break;
 170         case CPU_R4200:
 171 /*      case CPU_R4300: */
 172         case CPU_R4600:
 173         case CPU_R4640:
 174         case CPU_R4650:
 175         case CPU_R4700:
 176         case CPU_R5000:
 177         case CPU_R5500:
 178         case CPU_NEVADA:
 179         case CPU_4KC:
 180         case CPU_4KEC:
 181         case CPU_4KSC:
 182         case CPU_5KC:
 183         case CPU_25KF:
 184         case CPU_PR4450:
 185         case CPU_BMIPS3300:
 186         case CPU_BMIPS4350:
 187         case CPU_BMIPS4380:
 188         case CPU_BMIPS5000:
 189         case CPU_CAVIUM_OCTEON:
 190         case CPU_CAVIUM_OCTEON_PLUS:
 191         case CPU_CAVIUM_OCTEON2:
 192         case CPU_JZRISC:
 193         case CPU_XLR:
 194         case CPU_XLP:
 195                 cpu_wait = r4k_wait;
 196                 break;
 197
 198         case CPU_RM7000:
 199                 cpu_wait = rm7k_wait_irqoff;
 200                 break;
 201
 202         case CPU_M14KC:
 203         case CPU_24K:
 204         case CPU_34K:
 205         case CPU_1004K:
 206                 cpu_wait = r4k_wait;
 207                 if (read_c0_config7() & MIPS_CONF7_WII)
 208                         cpu_wait = r4k_wait_irqoff;
 209                 break;
 210
 211         case CPU_74K:
 212                 cpu_wait = r4k_wait;
 213                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
 214                         cpu_wait = r4k_wait_irqoff;
 215                 break;
 216
 217         case CPU_TX49XX:
 218                 cpu_wait = r4k_wait_irqoff;
 219                 break;
 220         case CPU_ALCHEMY:
 221                 cpu_wait = au1k_wait;
 222                 break;
 223         case CPU_20KC:
 224                 /*
 225                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 226                  * WAIT on Rev2.0 and Rev3.0 has E16.
 227                  * Rev3.1 WAIT is nop, why bother
 228                  */
 229                 if ((c->processor_id & 0xff) <= 0x64)
 230                         break;
 231
 232                 /*
 233                  * Another rev is incremeting c0_count at a reduced clock
 234                  * rate while in WAIT mode.  So we basically have the choice
 235                  * between using the cp0 timer as clocksource or avoiding
 236                  * the WAIT instruction.  Until more details are known,
 237                  * disable the use of WAIT for 20Kc entirely.
 238                    cpu_wait = r4k_wait;
 239                  */
 240                 break;
 241         case CPU_RM9000:
 242                 if ((c->processor_id & 0x00ff) >= 0x40)
 243                         cpu_wait = r4k_wait;
 244                 break;
 245         default:
 246                 break;
 247         }
 248 }
 249
 250 static inline void check_errata(void)
 251 {
 252         struct cpuinfo_mips *c = &current_cpu_data;
 253
 254         switch (c->cputype) {
 255         case CPU_34K:
 256                 /*
 257                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 258                  * This code only handles VPE0, any SMP/SMTC/RTOS code
 259                  * making use of VPE1 will be responsable for that VPE.
 260                  */
 261                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 262                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 263                 break;
 264         default:
 265                 break;
 266         }
 267 }
 268
 269 void __init check_bugs32(void)
 270 {
 271         check_errata();
 272 }
 273
 274 /*
 275  * Probe whether cpu has config register by trying to play with
 276  * alternate cache bit and see whether it matters.
 277  * It's used by cpu_probe to distinguish between R3000A and R3081.
 278  */
 279 static inline int cpu_has_confreg(void)
 280 {
 281 #ifdef CONFIG_CPU_R3000
 282         extern unsigned long r3k_cache_size(unsigned long);
 283         unsigned long size1, size2;
 284         unsigned long cfg = read_c0_conf();
 285
 286         size1 = r3k_cache_size(ST0_ISC);
 287         write_c0_conf(cfg ^ R30XX_CONF_AC);
 288         size2 = r3k_cache_size(ST0_ISC);
 289         write_c0_conf(cfg);
 290         return size1 != size2;
 291 #else
 292         return 0;
 293 #endif
 294 }
 295
 296 static inline void set_elf_platform(int cpu, const char *plat)
 297 {
 298         if (cpu == 0)
 299                 __elf_platform = plat;
 300 }
 301
 302 /*
 303  * Get the FPU Implementation/Revision.
 304  */
 305 static inline unsigned long cpu_get_fpu_id(void)
 306 {
 307         unsigned long tmp, fpu_id;
 308
 309         tmp = read_c0_status();
 310         __enable_fpu();
 311         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 312         write_c0_status(tmp);
 313         return fpu_id;
 314 }
 315
 316 /*
 317  * Check the CPU has an FPU the official way.
 318  */
 319 static inline int __cpu_has_fpu(void)
 320 {
 321         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 322 }
 323
 324 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 325 {
 326 #ifdef __NEED_VMBITS_PROBE
 327         write_c0_entryhi(0x3fffffffffffe000ULL);
 328         back_to_back_c0_hazard();
 329         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 330 #endif
 331 }
 332
 333 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 334                 | MIPS_CPU_COUNTER)
 335
 336 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 337 {
 338         switch (c->processor_id & 0xff00) {
 339         case PRID_IMP_R2000:
 340                 c->cputype = CPU_R2000;
 341                 __cpu_name[cpu] = "R2000";
 342                 c->isa_level = MIPS_CPU_ISA_I;
 343                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 344                              MIPS_CPU_NOFPUEX;
 345                 if (__cpu_has_fpu())
 346                         c->options |= MIPS_CPU_FPU;
 347                 c->tlbsize = 64;
 348                 break;
 349         case PRID_IMP_R3000:
 350                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
 351                         if (cpu_has_confreg()) {
 352                                 c->cputype = CPU_R3081E;
 353                                 __cpu_name[cpu] = "R3081";
 354                         } else {
 355                                 c->cputype = CPU_R3000A;
 356                                 __cpu_name[cpu] = "R3000A";
 357                         }
 358                         break;
 359                 } else {
 360                         c->cputype = CPU_R3000;
 361                         __cpu_name[cpu] = "R3000";
 362                 }
 363                 c->isa_level = MIPS_CPU_ISA_I;
 364                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 365                              MIPS_CPU_NOFPUEX;
 366                 if (__cpu_has_fpu())
 367                         c->options |= MIPS_CPU_FPU;
 368                 c->tlbsize = 64;
 369                 break;
 370         case PRID_IMP_R4000:
 371                 if (read_c0_config() & CONF_SC) {
 372                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 373                                 c->cputype = CPU_R4400PC;
 374                                 __cpu_name[cpu] = "R4400PC";
 375                         } else {
 376                                 c->cputype = CPU_R4000PC;
 377                                 __cpu_name[cpu] = "R4000PC";
 378                         }
 379                 } else {
 380                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 381                                 c->cputype = CPU_R4400SC;
 382                                 __cpu_name[cpu] = "R4400SC";
 383                         } else {
 384                                 c->cputype = CPU_R4000SC;
 385                                 __cpu_name[cpu] = "R4000SC";
 386                         }
 387                 }
 388
 389                 c->isa_level = MIPS_CPU_ISA_III;
 390                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 391                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 392                              MIPS_CPU_LLSC;
 393                 c->tlbsize = 48;
 394                 break;
 395         case PRID_IMP_VR41XX:
 396                 switch (c->processor_id & 0xf0) {
 397                 case PRID_REV_VR4111:
 398                         c->cputype = CPU_VR4111;
 399                         __cpu_name[cpu] = "NEC VR4111";
 400                         break;
 401                 case PRID_REV_VR4121:
 402                         c->cputype = CPU_VR4121;
 403                         __cpu_name[cpu] = "NEC VR4121";
 404                         break;
 405                 case PRID_REV_VR4122:
 406                         if ((c->processor_id & 0xf) < 0x3) {
 407                                 c->cputype = CPU_VR4122;
 408                                 __cpu_name[cpu] = "NEC VR4122";
 409                         } else {
 410                                 c->cputype = CPU_VR4181A;
 411                                 __cpu_name[cpu] = "NEC VR4181A";
 412                         }
 413                         break;
 414                 case PRID_REV_VR4130:
 415                         if ((c->processor_id & 0xf) < 0x4) {
 416                                 c->cputype = CPU_VR4131;
 417                                 __cpu_name[cpu] = "NEC VR4131";
 418                         } else {
 419                                 c->cputype = CPU_VR4133;
 420                                 __cpu_name[cpu] = "NEC VR4133";
 421                         }
 422                         break;
 423                 default:
 424                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 425                         c->cputype = CPU_VR41XX;
 426                         __cpu_name[cpu] = "NEC Vr41xx";
 427                         break;
 428                 }
 429                 c->isa_level = MIPS_CPU_ISA_III;
 430                 c->options = R4K_OPTS;
 431                 c->tlbsize = 32;
 432                 break;
 433         case PRID_IMP_R4300:
 434                 c->cputype = CPU_R4300;
 435                 __cpu_name[cpu] = "R4300";
 436                 c->isa_level = MIPS_CPU_ISA_III;
 437                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 438                              MIPS_CPU_LLSC;
 439                 c->tlbsize = 32;
 440                 break;
 441         case PRID_IMP_R4600:
 442                 c->cputype = CPU_R4600;
 443                 __cpu_name[cpu] = "R4600";
 444                 c->isa_level = MIPS_CPU_ISA_III;
 445                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 446                              MIPS_CPU_LLSC;
 447                 c->tlbsize = 48;
 448                 break;
 449         #if 0
 450         case PRID_IMP_R4650:
 451                 /*
 452                  * This processor doesn't have an MMU, so it's not
 453                  * "real easy" to run Linux on it. It is left purely
 454                  * for documentation.  Commented out because it shares
 455                  * it's c0_prid id number with the TX3900.
 456                  */
 457                 c->cputype = CPU_R4650;
 458                 __cpu_name[cpu] = "R4650";
 459                 c->isa_level = MIPS_CPU_ISA_III;
 460                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 461                 c->tlbsize = 48;
 462                 break;
 463         #endif
 464         case PRID_IMP_TX39:
 465                 c->isa_level = MIPS_CPU_ISA_I;
 466                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 467
 468                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 469                         c->cputype = CPU_TX3927;
 470                         __cpu_name[cpu] = "TX3927";
 471                         c->tlbsize = 64;
 472                 } else {
 473                         switch (c->processor_id & 0xff) {
 474                         case PRID_REV_TX3912:
 475                                 c->cputype = CPU_TX3912;
 476                                 __cpu_name[cpu] = "TX3912";
 477                                 c->tlbsize = 32;
 478                                 break;
 479                         case PRID_REV_TX3922:
 480                                 c->cputype = CPU_TX3922;
 481                                 __cpu_name[cpu] = "TX3922";
 482                                 c->tlbsize = 64;
 483                                 break;
 484                         }
 485                 }
 486                 break;
 487         case PRID_IMP_R4700:
 488                 c->cputype = CPU_R4700;
 489                 __cpu_name[cpu] = "R4700";
 490                 c->isa_level = MIPS_CPU_ISA_III;
 491                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 492                              MIPS_CPU_LLSC;
 493                 c->tlbsize = 48;
 494                 break;
 495         case PRID_IMP_TX49:
 496                 c->cputype = CPU_TX49XX;
 497                 __cpu_name[cpu] = "R49XX";
 498                 c->isa_level = MIPS_CPU_ISA_III;
 499                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 500                 if (!(c->processor_id & 0x08))
 501                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 502                 c->tlbsize = 48;
 503                 break;
 504         case PRID_IMP_R5000:
 505                 c->cputype = CPU_R5000;
 506                 __cpu_name[cpu] = "R5000";
 507                 c->isa_level = MIPS_CPU_ISA_IV;
 508                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 509                              MIPS_CPU_LLSC;
 510                 c->tlbsize = 48;
 511                 break;
 512         case PRID_IMP_R5432:
 513                 c->cputype = CPU_R5432;
 514                 __cpu_name[cpu] = "R5432";
 515                 c->isa_level = MIPS_CPU_ISA_IV;
 516                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 517                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 518                 c->tlbsize = 48;
 519                 break;
 520         case PRID_IMP_R5500:
 521                 c->cputype = CPU_R5500;
 522                 __cpu_name[cpu] = "R5500";
 523                 c->isa_level = MIPS_CPU_ISA_IV;
 524                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 525                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 526                 c->tlbsize = 48;
 527                 break;
 528         case PRID_IMP_NEVADA:
 529                 c->cputype = CPU_NEVADA;
 530                 __cpu_name[cpu] = "Nevada";
 531                 c->isa_level = MIPS_CPU_ISA_IV;
 532                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 533                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 534                 c->tlbsize = 48;
 535                 break;
 536         case PRID_IMP_R6000:
 537                 c->cputype = CPU_R6000;
 538                 __cpu_name[cpu] = "R6000";
 539                 c->isa_level = MIPS_CPU_ISA_II;
 540                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 541                              MIPS_CPU_LLSC;
 542                 c->tlbsize = 32;
 543                 break;
 544         case PRID_IMP_R6000A:
 545                 c->cputype = CPU_R6000A;
 546                 __cpu_name[cpu] = "R6000A";
 547                 c->isa_level = MIPS_CPU_ISA_II;
 548                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 549                              MIPS_CPU_LLSC;
 550                 c->tlbsize = 32;
 551                 break;
 552         case PRID_IMP_RM7000:
 553                 c->cputype = CPU_RM7000;
 554                 __cpu_name[cpu] = "RM7000";
 555                 c->isa_level = MIPS_CPU_ISA_IV;
 556                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 557                              MIPS_CPU_LLSC;
 558                 /*
 559                  * Undocumented RM7000:  Bit 29 in the info register of
 560                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 561                  * entries.
 562                  *
 563                  * 29      1 =>    64 entry JTLB
 564                  *         0 =>    48 entry JTLB
 565                  */
 566                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 567                 break;
 568         case PRID_IMP_RM9000:
 569                 c->cputype = CPU_RM9000;
 570                 __cpu_name[cpu] = "RM9000";
 571                 c->isa_level = MIPS_CPU_ISA_IV;
 572                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 573                              MIPS_CPU_LLSC;
 574                 /*
 575                  * Bit 29 in the info register of the RM9000
 576                  * indicates if the TLB has 48 or 64 entries.
 577                  *
 578                  * 29      1 =>    64 entry JTLB
 579                  *         0 =>    48 entry JTLB
 580                  */
 581                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 582                 break;
 583         case PRID_IMP_R8000:
 584                 c->cputype = CPU_R8000;
 585                 __cpu_name[cpu] = "RM8000";
 586                 c->isa_level = MIPS_CPU_ISA_IV;
 587                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 588                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 589                              MIPS_CPU_LLSC;
 590                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 591                 break;
 592         case PRID_IMP_R10000:
 593                 c->cputype = CPU_R10000;
 594                 __cpu_name[cpu] = "R10000";
 595                 c->isa_level = MIPS_CPU_ISA_IV;
 596                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 597                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 598                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 599                              MIPS_CPU_LLSC;
 600                 c->tlbsize = 64;
 601                 break;
 602         case PRID_IMP_R12000:
 603                 c->cputype = CPU_R12000;
 604                 __cpu_name[cpu] = "R12000";
 605                 c->isa_level = MIPS_CPU_ISA_IV;
 606                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 607                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 608                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 609                              MIPS_CPU_LLSC;
 610                 c->tlbsize = 64;
 611                 break;
 612         case PRID_IMP_R14000:
 613                 c->cputype = CPU_R14000;
 614                 __cpu_name[cpu] = "R14000";
 615                 c->isa_level = MIPS_CPU_ISA_IV;
 616                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 617                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 618                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 619                              MIPS_CPU_LLSC;
 620                 c->tlbsize = 64;
 621                 break;
 622         case PRID_IMP_LOONGSON2:
 623                 c->cputype = CPU_LOONGSON2;
 624                 __cpu_name[cpu] = "ICT Loongson-2";
 625
 626                 switch (c->processor_id & PRID_REV_MASK) {
 627                 case PRID_REV_LOONGSON2E:
 628                         set_elf_platform(cpu, "loongson2e");
 629                         break;
 630                 case PRID_REV_LOONGSON2F:
 631                         set_elf_platform(cpu, "loongson2f");
 632                         break;
 633                 }
 634
 635                 c->isa_level = MIPS_CPU_ISA_III;
 636                 c->options = R4K_OPTS |
 637                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 638                              MIPS_CPU_32FPR;
 639                 c->tlbsize = 64;
 640                 break;
 641         }
 642 }
 643
 644 static char unknown_isa[] __cpuinitdata = KERN_ERR \
 645         "Unsupported ISA type, c0.config0: %d.";
 646
 647 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 648 {
 649         unsigned int config0;
 650         int isa;
 651
 652         config0 = read_c0_config();
 653
 654         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 655                 c->options |= MIPS_CPU_TLB;
 656         isa = (config0 & MIPS_CONF_AT) >> 13;
 657         switch (isa) {
 658         case 0:
 659                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 660                 case 0:
 661                         c->isa_level = MIPS_CPU_ISA_M32R1;
 662                         break;
 663                 case 1:
 664                         c->isa_level = MIPS_CPU_ISA_M32R2;
 665                         break;
 666                 default:
 667                         goto unknown;
 668                 }
 669                 break;
 670         case 2:
 671                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 672                 case 0:
 673                         c->isa_level = MIPS_CPU_ISA_M64R1;
 674                         break;
 675                 case 1:
 676                         c->isa_level = MIPS_CPU_ISA_M64R2;
 677                         break;
 678                 default:
 679                         goto unknown;
 680                 }
 681                 break;
 682         default:
 683                 goto unknown;
 684         }
 685
 686         return config0 & MIPS_CONF_M;
 687
 688 unknown:
 689         panic(unknown_isa, config0);
 690 }
 691
 692 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 693 {
 694         unsigned int config1;
 695
 696         config1 = read_c0_config1();
 697
 698         if (config1 & MIPS_CONF1_MD)
 699                 c->ases |= MIPS_ASE_MDMX;
 700         if (config1 & MIPS_CONF1_WR)
 701                 c->options |= MIPS_CPU_WATCH;
 702         if (config1 & MIPS_CONF1_CA)
 703                 c->ases |= MIPS_ASE_MIPS16;
 704         if (config1 & MIPS_CONF1_EP)
 705                 c->options |= MIPS_CPU_EJTAG;
 706         if (config1 & MIPS_CONF1_FP) {
 707                 c->options |= MIPS_CPU_FPU;
 708                 c->options |= MIPS_CPU_32FPR;
 709         }
 710         if (cpu_has_tlb)
 711                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 712
 713         return config1 & MIPS_CONF_M;
 714 }
 715
 716 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 717 {
 718         unsigned int config2;
 719
 720         config2 = read_c0_config2();
 721
 722         if (config2 & MIPS_CONF2_SL)
 723                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 724
 725         return config2 & MIPS_CONF_M;
 726 }
 727
 728 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 729 {
 730         unsigned int config3;
 731
 732         config3 = read_c0_config3();
 733
 734         if (config3 & MIPS_CONF3_SM)
 735                 c->ases |= MIPS_ASE_SMARTMIPS;
 736         if (config3 & MIPS_CONF3_DSP)
 737                 c->ases |= MIPS_ASE_DSP;
 738         if (config3 & MIPS_CONF3_VINT)
 739                 c->options |= MIPS_CPU_VINT;
 740         if (config3 & MIPS_CONF3_VEIC)
 741                 c->options |= MIPS_CPU_VEIC;
 742         if (config3 & MIPS_CONF3_MT)
 743                 c->ases |= MIPS_ASE_MIPSMT;
 744         if (config3 & MIPS_CONF3_ULRI)
 745                 c->options |= MIPS_CPU_ULRI;
 746
 747         return config3 & MIPS_CONF_M;
 748 }
 749
 750 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 751 {
 752         unsigned int config4;
 753
 754         config4 = read_c0_config4();
 755
 756         if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
 757             && cpu_has_tlb)
 758                 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 759
 760         c->kscratch_mask = (config4 >> 16) & 0xff;
 761
 762         return config4 & MIPS_CONF_M;
 763 }
 764
 765 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 766 {
 767         int ok;
 768
 769         /* MIPS32 or MIPS64 compliant CPU.  */
 770         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 771                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 772
 773         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 774
 775         ok = decode_config0(c);                 /* Read Config registers.  */
 776         BUG_ON(!ok);                            /* Arch spec violation!  */
 777         if (ok)
 778                 ok = decode_config1(c);
 779         if (ok)
 780                 ok = decode_config2(c);
 781         if (ok)
 782                 ok = decode_config3(c);
 783         if (ok)
 784                 ok = decode_config4(c);
 785
 786         mips_probe_watch_registers(c);
 787
 788         if (cpu_has_mips_r2)
 789                 c->core = read_c0_ebase() & 0x3ff;
 790 }
 791
 792 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 793 {
 794         decode_configs(c);
 795         switch (c->processor_id & 0xff00) {
 796         case PRID_IMP_4KC:
 797                 c->cputype = CPU_4KC;
 798                 __cpu_name[cpu] = "MIPS 4Kc";
 799                 break;
 800         case PRID_IMP_4KEC:
 801         case PRID_IMP_4KECR2:
 802                 c->cputype = CPU_4KEC;
 803                 __cpu_name[cpu] = "MIPS 4KEc";
 804                 break;
 805         case PRID_IMP_4KSC:
 806         case PRID_IMP_4KSD:
 807                 c->cputype = CPU_4KSC;
 808                 __cpu_name[cpu] = "MIPS 4KSc";
 809                 break;
 810         case PRID_IMP_5KC:
 811                 c->cputype = CPU_5KC;
 812                 __cpu_name[cpu] = "MIPS 5Kc";
 813                 break;
 814         case PRID_IMP_5KE:
 815                 c->cputype = CPU_5KE;
 816                 __cpu_name[cpu] = "MIPS 5KE";
 817                 break;
 818         case PRID_IMP_20KC:
 819                 c->cputype = CPU_20KC;
 820                 __cpu_name[cpu] = "MIPS 20Kc";
 821                 break;
 822         case PRID_IMP_24K:
 823         case PRID_IMP_24KE:
 824                 c->cputype = CPU_24K;
 825                 __cpu_name[cpu] = "MIPS 24Kc";
 826                 break;
 827         case PRID_IMP_25KF:
 828                 c->cputype = CPU_25KF;
 829                 __cpu_name[cpu] = "MIPS 25Kc";
 830                 break;
 831         case PRID_IMP_34K:
 832                 c->cputype = CPU_34K;
 833                 __cpu_name[cpu] = "MIPS 34Kc";
 834                 break;
 835         case PRID_IMP_74K:
 836                 c->cputype = CPU_74K;
 837                 __cpu_name[cpu] = "MIPS 74Kc";
 838                 break;
 839         case PRID_IMP_M14KC:
 840                 c->cputype = CPU_M14KC;
 841                 __cpu_name[cpu] = "MIPS M14Kc";
 842                 break;
 843         case PRID_IMP_1004K:
 844                 c->cputype = CPU_1004K;
 845                 __cpu_name[cpu] = "MIPS 1004Kc";
 846                 break;
 847         }
 848
 849         spram_config();
 850 }
 851
 852 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 853 {
 854         decode_configs(c);
 855         switch (c->processor_id & 0xff00) {
 856         case PRID_IMP_AU1_REV1:
 857         case PRID_IMP_AU1_REV2:
 858                 c->cputype = CPU_ALCHEMY;
 859                 switch ((c->processor_id >> 24) & 0xff) {
 860                 case 0:
 861                         __cpu_name[cpu] = "Au1000";
 862                         break;
 863                 case 1:
 864                         __cpu_name[cpu] = "Au1500";
 865                         break;
 866                 case 2:
 867                         __cpu_name[cpu] = "Au1100";
 868                         break;
 869                 case 3:
 870                         __cpu_name[cpu] = "Au1550";
 871                         break;
 872                 case 4:
 873                         __cpu_name[cpu] = "Au1200";
 874                         if ((c->processor_id & 0xff) == 2)
 875                                 __cpu_name[cpu] = "Au1250";
 876                         break;
 877                 case 5:
 878                         __cpu_name[cpu] = "Au1210";
 879                         break;
 880                 default:
 881                         __cpu_name[cpu] = "Au1xxx";
 882                         break;
 883                 }
 884                 break;
 885         }
 886 }
 887
 888 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 889 {
 890         decode_configs(c);
 891
 892         switch (c->processor_id & 0xff00) {
 893         case PRID_IMP_SB1:
 894                 c->cputype = CPU_SB1;
 895                 __cpu_name[cpu] = "SiByte SB1";
 896                 /* FPU in pass1 is known to have issues. */
 897                 if ((c->processor_id & 0xff) < 0x02)
 898                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 899                 break;
 900         case PRID_IMP_SB1A:
 901                 c->cputype = CPU_SB1A;
 902                 __cpu_name[cpu] = "SiByte SB1A";
 903                 break;
 904         }
 905 }
 906
 907 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 908 {
 909         decode_configs(c);
 910         switch (c->processor_id & 0xff00) {
 911         case PRID_IMP_SR71000:
 912                 c->cputype = CPU_SR71000;
 913                 __cpu_name[cpu] = "Sandcraft SR71000";
 914                 c->scache.ways = 8;
 915                 c->tlbsize = 64;
 916                 break;
 917         }
 918 }
 919
 920 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 921 {
 922         decode_configs(c);
 923         switch (c->processor_id & 0xff00) {
 924         case PRID_IMP_PR4450:
 925                 c->cputype = CPU_PR4450;
 926                 __cpu_name[cpu] = "Philips PR4450";
 927                 c->isa_level = MIPS_CPU_ISA_M32R1;
 928                 break;
 929         }
 930 }
 931
 932 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 933 {
 934         decode_configs(c);
 935         switch (c->processor_id & 0xff00) {
 936         case PRID_IMP_BMIPS32_REV4:
 937         case PRID_IMP_BMIPS32_REV8:
 938                 c->cputype = CPU_BMIPS32;
 939                 __cpu_name[cpu] = "Broadcom BMIPS32";
 940                 set_elf_platform(cpu, "bmips32");
 941                 break;
 942         case PRID_IMP_BMIPS3300:
 943         case PRID_IMP_BMIPS3300_ALT:
 944         case PRID_IMP_BMIPS3300_BUG:
 945                 c->cputype = CPU_BMIPS3300;
 946                 __cpu_name[cpu] = "Broadcom BMIPS3300";
 947                 set_elf_platform(cpu, "bmips3300");
 948                 break;
 949         case PRID_IMP_BMIPS43XX: {
 950                 int rev = c->processor_id & 0xff;
 951
 952                 if (rev >= PRID_REV_BMIPS4380_LO &&
 953                                 rev <= PRID_REV_BMIPS4380_HI) {
 954                         c->cputype = CPU_BMIPS4380;
 955                         __cpu_name[cpu] = "Broadcom BMIPS4380";
 956                         set_elf_platform(cpu, "bmips4380");
 957                 } else {
 958                         c->cputype = CPU_BMIPS4350;
 959                         __cpu_name[cpu] = "Broadcom BMIPS4350";
 960                         set_elf_platform(cpu, "bmips4350");
 961                 }
 962                 break;
 963         }
 964         case PRID_IMP_BMIPS5000:
 965                 c->cputype = CPU_BMIPS5000;
 966                 __cpu_name[cpu] = "Broadcom BMIPS5000";
 967                 set_elf_platform(cpu, "bmips5000");
 968                 c->options |= MIPS_CPU_ULRI;
 969                 break;
 970         }
 971 }
 972
 973 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 974 {
 975         decode_configs(c);
 976         switch (c->processor_id & 0xff00) {
 977         case PRID_IMP_CAVIUM_CN38XX:
 978         case PRID_IMP_CAVIUM_CN31XX:
 979         case PRID_IMP_CAVIUM_CN30XX:
 980                 c->cputype = CPU_CAVIUM_OCTEON;
 981                 __cpu_name[cpu] = "Cavium Octeon";
 982                 goto platform;
 983         case PRID_IMP_CAVIUM_CN58XX:
 984         case PRID_IMP_CAVIUM_CN56XX:
 985         case PRID_IMP_CAVIUM_CN50XX:
 986         case PRID_IMP_CAVIUM_CN52XX:
 987                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
 988                 __cpu_name[cpu] = "Cavium Octeon+";
 989 platform:
 990                 set_elf_platform(cpu, "octeon");
 991                 break;
 992         case PRID_IMP_CAVIUM_CN61XX:
 993         case PRID_IMP_CAVIUM_CN63XX:
 994         case PRID_IMP_CAVIUM_CN66XX:
 995         case PRID_IMP_CAVIUM_CN68XX:
 996                 c->cputype = CPU_CAVIUM_OCTEON2;
 997                 __cpu_name[cpu] = "Cavium Octeon II";
 998                 set_elf_platform(cpu, "octeon2");
 999                 break;
1000         default:
1001                 printk(KERN_INFO "Unknown Octeon chip!\n");
1002                 c->cputype = CPU_UNKNOWN;
1003                 break;
1004         }
1005 }
1006
1007 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1008 {
1009         decode_configs(c);
1010         /* JZRISC does not implement the CP0 counter. */
1011         c->options &= ~MIPS_CPU_COUNTER;
1012         switch (c->processor_id & 0xff00) {
1013         case PRID_IMP_JZRISC:
1014                 c->cputype = CPU_JZRISC;
1015                 __cpu_name[cpu] = "Ingenic JZRISC";
1016                 break;
1017         default:
1018                 panic("Unknown Ingenic Processor ID!");
1019                 break;
1020         }
1021 }
1022
1023 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1024 {
1025         decode_configs(c);
1026
1027         if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1028                 c->cputype = CPU_ALCHEMY;
1029                 __cpu_name[cpu] = "Au1300";
1030                 /* following stuff is not for Alchemy */
1031                 return;
1032         }
1033
1034         c->options = (MIPS_CPU_TLB       |
1035                         MIPS_CPU_4KEX    |
1036                         MIPS_CPU_COUNTER |
1037                         MIPS_CPU_DIVEC   |
1038                         MIPS_CPU_WATCH   |
1039                         MIPS_CPU_EJTAG   |
1040                         MIPS_CPU_LLSC);
1041
1042         switch (c->processor_id & 0xff00) {
1043         case PRID_IMP_NETLOGIC_XLP8XX:
1044         case PRID_IMP_NETLOGIC_XLP3XX:
1045                 c->cputype = CPU_XLP;
1046                 __cpu_name[cpu] = "Netlogic XLP";
1047                 break;
1048
1049         case PRID_IMP_NETLOGIC_XLR732:
1050         case PRID_IMP_NETLOGIC_XLR716:
1051         case PRID_IMP_NETLOGIC_XLR532:
1052         case PRID_IMP_NETLOGIC_XLR308:
1053         case PRID_IMP_NETLOGIC_XLR532C:
1054         case PRID_IMP_NETLOGIC_XLR516C:
1055         case PRID_IMP_NETLOGIC_XLR508C:
1056         case PRID_IMP_NETLOGIC_XLR308C:
1057                 c->cputype = CPU_XLR;
1058                 __cpu_name[cpu] = "Netlogic XLR";
1059                 break;
1060
1061         case PRID_IMP_NETLOGIC_XLS608:
1062         case PRID_IMP_NETLOGIC_XLS408:
1063         case PRID_IMP_NETLOGIC_XLS404:
1064         case PRID_IMP_NETLOGIC_XLS208:
1065         case PRID_IMP_NETLOGIC_XLS204:
1066         case PRID_IMP_NETLOGIC_XLS108:
1067         case PRID_IMP_NETLOGIC_XLS104:
1068         case PRID_IMP_NETLOGIC_XLS616B:
1069         case PRID_IMP_NETLOGIC_XLS608B:
1070         case PRID_IMP_NETLOGIC_XLS416B:
1071         case PRID_IMP_NETLOGIC_XLS412B:
1072         case PRID_IMP_NETLOGIC_XLS408B:
1073         case PRID_IMP_NETLOGIC_XLS404B:
1074                 c->cputype = CPU_XLR;
1075                 __cpu_name[cpu] = "Netlogic XLS";
1076                 break;
1077
1078         default:
1079                 pr_info("Unknown Netlogic chip id [%02x]!\n",
1080                        c->processor_id);
1081                 c->cputype = CPU_XLR;
1082                 break;
1083         }
1084
1085         if (c->cputype == CPU_XLP) {
1086                 c->isa_level = MIPS_CPU_ISA_M64R2;
1087                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1088                 /* This will be updated again after all threads are woken up */
1089                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1090         } else {
1091                 c->isa_level = MIPS_CPU_ISA_M64R1;
1092                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1093         }
1094 }
1095
1096 #ifdef CONFIG_64BIT
1097 /* For use by uaccess.h */
1098 u64 __ua_limit;
1099 EXPORT_SYMBOL(__ua_limit);
1100 #endif
1101
1102 const char *__cpu_name[NR_CPUS];
1103 const char *__elf_platform;
1104
1105 __cpuinit void cpu_probe(void)
1106 {
1107         struct cpuinfo_mips *c = &current_cpu_data;
1108         unsigned int cpu = smp_processor_id();
1109
1110         c->processor_id = PRID_IMP_UNKNOWN;
1111         c->fpu_id       = FPIR_IMP_NONE;
1112         c->cputype      = CPU_UNKNOWN;
1113
1114         c->processor_id = read_c0_prid();
1115         switch (c->processor_id & 0xff0000) {
1116         case PRID_COMP_LEGACY:
1117                 cpu_probe_legacy(c, cpu);
1118                 break;
1119         case PRID_COMP_MIPS:
1120                 cpu_probe_mips(c, cpu);
1121                 break;
1122         case PRID_COMP_ALCHEMY:
1123                 cpu_probe_alchemy(c, cpu);
1124                 break;
1125         case PRID_COMP_SIBYTE:
1126                 cpu_probe_sibyte(c, cpu);
1127                 break;
1128         case PRID_COMP_BROADCOM:
1129                 cpu_probe_broadcom(c, cpu);
1130                 break;
1131         case PRID_COMP_SANDCRAFT:
1132                 cpu_probe_sandcraft(c, cpu);
1133                 break;
1134         case PRID_COMP_NXP:
1135                 cpu_probe_nxp(c, cpu);
1136                 break;
1137         case PRID_COMP_CAVIUM:
1138                 cpu_probe_cavium(c, cpu);
1139                 break;
1140         case PRID_COMP_INGENIC:
1141                 cpu_probe_ingenic(c, cpu);
1142                 break;
1143         case PRID_COMP_NETLOGIC:
1144                 cpu_probe_netlogic(c, cpu);
1145                 break;
1146         }
1147
1148         BUG_ON(!__cpu_name[cpu]);
1149         BUG_ON(c->cputype == CPU_UNKNOWN);
1150
1151         /*
1152          * Platform code can force the cpu type to optimize code
1153          * generation. In that case be sure the cpu type is correctly
1154          * manually setup otherwise it could trigger some nasty bugs.
1155          */
1156         BUG_ON(current_cpu_type() != c->cputype);
1157
1158         if (mips_fpu_disabled)
1159                 c->options &= ~MIPS_CPU_FPU;
1160
1161         if (mips_dsp_disabled)
1162                 c->ases &= ~MIPS_ASE_DSP;
1163
1164         if (c->options & MIPS_CPU_FPU) {
1165                 c->fpu_id = cpu_get_fpu_id();
1166
1167                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1168                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
1169                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
1170                     c->isa_level == MIPS_CPU_ISA_M64R2) {
1171                         if (c->fpu_id & MIPS_FPIR_3D)
1172                                 c->ases |= MIPS_ASE_MIPS3D;
1173                 }
1174         }
1175
1176         if (cpu_has_mips_r2)
1177                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1178         else
1179                 c->srsets = 1;
1180
1181         cpu_probe_vmbits(c);
1182
1183 #ifdef CONFIG_64BIT
1184         if (cpu == 0)
1185                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1186 #endif
1187 }
1188
1189 __cpuinit void cpu_report(void)
1190 {
1191         struct cpuinfo_mips *c = &current_cpu_data;
1192
1193         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1194                c->processor_id, cpu_name_string());
1195         if (c->options & MIPS_CPU_FPU)
1196                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1197 }