2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2007 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
9 #include <linux/init.h>
10 #include <linux/console.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
14 #include <linux/serial.h>
15 #include <linux/smp.h>
16 #include <linux/types.h>
17 #include <linux/string.h> /* for memset */
18 #include <linux/tty.h>
19 #include <linux/time.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial_8250.h>
24 #include <asm/processor.h>
25 #include <asm/reboot.h>
26 #include <asm/smp-ops.h>
27 #include <asm/system.h>
28 #include <asm/irq_cpu.h>
29 #include <asm/mipsregs.h>
30 #include <asm/bootinfo.h>
31 #include <asm/sections.h>
34 #include <asm/octeon/octeon.h>
35 #include <asm/octeon/pci-octeon.h>
36 #include <asm/octeon/cvmx-mio-defs.h>
38 #ifdef CONFIG_CAVIUM_DECODE_RSL
39 extern void cvmx_interrupt_rsl_decode(void);
40 extern int __cvmx_interrupt_ecc_report_single_bit_errors;
41 extern void cvmx_interrupt_rsl_enable(void);
44 extern struct plat_smp_ops octeon_smp_ops;
47 extern void pci_console_init(const char *arg);
50 static unsigned long long MAX_MEMORY = 512ull << 20;
52 struct octeon_boot_descriptor *octeon_boot_desc_ptr;
54 struct cvmx_bootinfo *octeon_bootinfo;
55 EXPORT_SYMBOL(octeon_bootinfo);
57 #ifdef CONFIG_CAVIUM_RESERVE32
58 uint64_t octeon_reserve32_memory;
59 EXPORT_SYMBOL(octeon_reserve32_memory);
62 static int octeon_uart;
64 extern asmlinkage void handle_int(void);
65 extern asmlinkage void plat_irq_dispatch(void);
68 * Return non zero if we are currently running in the Octeon simulator
72 int octeon_is_simulation(void)
74 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
76 EXPORT_SYMBOL(octeon_is_simulation);
79 * Return true if Octeon is in PCI Host mode. This means
80 * Linux can control the PCI bus.
82 * Returns Non zero if Octeon in host mode.
84 int octeon_is_pci_host(void)
87 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
94 * Get the clock rate of Octeon
96 * Returns Clock rate in HZ
98 uint64_t octeon_get_clock_rate(void)
100 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
102 return sysinfo->cpu_clock_hz;
104 EXPORT_SYMBOL(octeon_get_clock_rate);
106 static u64 octeon_io_clock_rate;
108 u64 octeon_get_io_clock_rate(void)
110 return octeon_io_clock_rate;
112 EXPORT_SYMBOL(octeon_get_io_clock_rate);
116 * Write to the LCD display connected to the bootbus. This display
117 * exists on most Cavium evaluation boards. If it doesn't exist, then
118 * this function doesn't do anything.
120 * @s: String to write
122 void octeon_write_lcd(const char *s)
124 if (octeon_bootinfo->led_display_base_addr) {
125 void __iomem *lcd_address =
126 ioremap_nocache(octeon_bootinfo->led_display_base_addr,
129 for (i = 0; i < 8; i++, s++) {
131 iowrite8(*s, lcd_address + i);
133 iowrite8(' ', lcd_address + i);
135 iounmap(lcd_address);
140 * Return the console uart passed by the bootloader
142 * Returns uart (0 or 1)
144 int octeon_get_boot_uart(void)
147 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
150 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
157 * Get the coremask Linux was booted on.
161 int octeon_get_boot_coremask(void)
163 return octeon_boot_desc_ptr->core_mask;
167 * Check the hardware BIST results for a CPU
169 void octeon_check_cpu_bist(void)
171 const int coreid = cvmx_get_core_num();
172 unsigned long long mask;
173 unsigned long long bist_val;
175 /* Check BIST results for COP0 registers */
176 mask = 0x1f00000000ull;
177 bist_val = read_octeon_c0_icacheerr();
179 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
182 bist_val = read_octeon_c0_dcacheerr();
184 pr_err("Core%d L1 Dcache parity error: "
185 "CacheErr(dcache) = 0x%llx\n",
188 mask = 0xfc00000000000000ull;
189 bist_val = read_c0_cvmmemctl();
191 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
194 write_octeon_c0_dcacheerr(0);
200 * @command: Command to pass to the bootloader. Currently ignored.
202 static void octeon_restart(char *command)
204 /* Disable all watchdogs before soft reset. They don't get cleared */
207 for_each_online_cpu(cpu)
208 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
210 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
215 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
220 * Permanently stop a core.
224 static void octeon_kill_core(void *arg)
227 if (octeon_is_simulation()) {
228 /* The simulator needs the watchdog to stop for dead cores */
229 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
230 /* A break instruction causes the simulator stop a core */
231 asm volatile ("sync\nbreak");
239 static void octeon_halt(void)
241 smp_call_function(octeon_kill_core, NULL, 0);
243 switch (octeon_bootinfo->board_type) {
244 case CVMX_BOARD_TYPE_NAO38:
245 /* Driving a 1 to GPIO 12 shuts off this board */
246 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
247 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
250 octeon_write_lcd("PowerOff");
254 octeon_kill_core(NULL);
258 * Handle all the error condition interrupts that might occur.
261 #ifdef CONFIG_CAVIUM_DECODE_RSL
262 static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id)
264 cvmx_interrupt_rsl_decode();
270 * Return a string representing the system type
274 const char *octeon_board_type_string(void)
276 static char name[80];
277 sprintf(name, "%s (%s)",
278 cvmx_board_type_to_string(octeon_bootinfo->board_type),
279 octeon_model_get_string(read_c0_prid()));
283 const char *get_system_type(void)
284 __attribute__ ((alias("octeon_board_type_string")));
286 void octeon_user_io_init(void)
288 union octeon_cvmemctl cvmmemctl;
289 union cvmx_iob_fau_timeout fau_timeout;
290 union cvmx_pow_nw_tim nm_tim;
293 /* Get the current settings for CP0_CVMMEMCTL_REG */
294 cvmmemctl.u64 = read_c0_cvmmemctl();
295 /* R/W If set, marked write-buffer entries time out the same
296 * as as other entries; if clear, marked write-buffer entries
297 * use the maximum timeout. */
298 cvmmemctl.s.dismarkwblongto = 1;
299 /* R/W If set, a merged store does not clear the write-buffer
300 * entry timeout state. */
301 cvmmemctl.s.dismrgclrwbto = 0;
302 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
303 * word location for an IOBDMA. The other 8 bits come from the
304 * SCRADDR field of the IOBDMA. */
305 cvmmemctl.s.iobdmascrmsb = 0;
306 /* R/W If set, SYNCWS and SYNCS only order marked stores; if
307 * clear, SYNCWS and SYNCS only order unmarked
308 * stores. SYNCWSMARKED has no effect when DISSYNCWS is
310 cvmmemctl.s.syncwsmarked = 0;
311 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
312 cvmmemctl.s.dissyncws = 0;
313 /* R/W If set, no stall happens on write buffer full. */
314 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
315 cvmmemctl.s.diswbfst = 1;
317 cvmmemctl.s.diswbfst = 0;
318 /* R/W If set (and SX set), supervisor-level loads/stores can
319 * use XKPHYS addresses with <48>==0 */
320 cvmmemctl.s.xkmemenas = 0;
322 /* R/W If set (and UX set), user-level loads/stores can use
323 * XKPHYS addresses with VA<48>==0 */
324 cvmmemctl.s.xkmemenau = 0;
326 /* R/W If set (and SX set), supervisor-level loads/stores can
327 * use XKPHYS addresses with VA<48>==1 */
328 cvmmemctl.s.xkioenas = 0;
330 /* R/W If set (and UX set), user-level loads/stores can use
331 * XKPHYS addresses with VA<48>==1 */
332 cvmmemctl.s.xkioenau = 0;
334 /* R/W If set, all stores act as SYNCW (NOMERGE must be set
335 * when this is set) RW, reset to 0. */
336 cvmmemctl.s.allsyncw = 0;
338 /* R/W If set, no stores merge, and all stores reach the
339 * coherent bus in order. */
340 cvmmemctl.s.nomerge = 0;
341 /* R/W Selects the bit in the counter used for DID time-outs 0
342 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
343 * between 1x and 2x this interval. For example, with
344 * DIDTTO=3, expiration interval is between 16K and 32K. */
345 cvmmemctl.s.didtto = 0;
346 /* R/W If set, the (mem) CSR clock never turns off. */
347 cvmmemctl.s.csrckalwys = 0;
348 /* R/W If set, mclk never turns off. */
349 cvmmemctl.s.mclkalwys = 0;
350 /* R/W Selects the bit in the counter used for write buffer
351 * flush time-outs (WBFLT+11) is the bit position in an
352 * internal counter used to determine expiration. The write
353 * buffer expires between 1x and 2x this interval. For
354 * example, with WBFLT = 0, a write buffer expires between 2K
355 * and 4K cycles after the write buffer entry is allocated. */
356 cvmmemctl.s.wbfltime = 0;
357 /* R/W If set, do not put Istream in the L2 cache. */
358 cvmmemctl.s.istrnol2 = 0;
361 * R/W The write buffer threshold. As per erratum Core-14752
362 * for CN63XX, a sc/scd might fail if the write buffer is
363 * full. Lowering WBTHRESH greatly lowers the chances of the
364 * write buffer ever being full and triggering the erratum.
366 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
367 cvmmemctl.s.wbthresh = 4;
369 cvmmemctl.s.wbthresh = 10;
371 /* R/W If set, CVMSEG is available for loads/stores in
372 * kernel/debug mode. */
373 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
374 cvmmemctl.s.cvmsegenak = 1;
376 cvmmemctl.s.cvmsegenak = 0;
378 /* R/W If set, CVMSEG is available for loads/stores in
379 * supervisor mode. */
380 cvmmemctl.s.cvmsegenas = 0;
381 /* R/W If set, CVMSEG is available for loads/stores in user
383 cvmmemctl.s.cvmsegenau = 0;
384 /* R/W Size of local memory in cache blocks, 54 (6912 bytes)
385 * is max legal value. */
386 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
388 write_c0_cvmmemctl(cvmmemctl.u64);
390 if (smp_processor_id() == 0)
391 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
392 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
393 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
395 /* Move the performance counter interrupts to IRQ 6 */
396 cvmctl = read_c0_cvmctl();
399 write_c0_cvmctl(cvmctl);
401 /* Set a default for the hardware timeouts */
403 fau_timeout.s.tout_val = 0xfff;
404 /* Disable tagwait FAU timeout */
405 fau_timeout.s.tout_enb = 0;
406 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
411 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
413 write_octeon_c0_icacheerr(0);
414 write_c0_derraddr1(0);
418 * Early entry point for arch setup
420 void __init prom_init(void)
422 struct cvmx_sysinfo *sysinfo;
423 const int coreid = cvmx_get_core_num();
426 #ifdef CONFIG_CAVIUM_RESERVE32
430 * The bootloader passes a pointer to the boot descriptor in
431 * $a3, this is available as fw_arg3.
433 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
435 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
436 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
438 sysinfo = cvmx_sysinfo_get();
439 memset(sysinfo, 0, sizeof(*sysinfo));
440 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
441 sysinfo->phy_mem_desc_ptr =
442 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
443 sysinfo->core_mask = octeon_bootinfo->core_mask;
444 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
445 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
446 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
447 sysinfo->board_type = octeon_bootinfo->board_type;
448 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
449 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
450 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
451 sizeof(sysinfo->mac_addr_base));
452 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
453 memcpy(sysinfo->board_serial_number,
454 octeon_bootinfo->board_serial_number,
455 sizeof(sysinfo->board_serial_number));
456 sysinfo->compact_flash_common_base_addr =
457 octeon_bootinfo->compact_flash_common_base_addr;
458 sysinfo->compact_flash_attribute_base_addr =
459 octeon_bootinfo->compact_flash_attribute_base_addr;
460 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
461 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
462 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
464 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
465 /* I/O clock runs at a different rate than the CPU. */
466 union cvmx_mio_rst_boot rst_boot;
467 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
468 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
470 octeon_io_clock_rate = sysinfo->cpu_clock_hz;
474 * Only enable the LED controller if we're running on a CN38XX, CN58XX,
475 * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
477 if (!octeon_is_simulation() &&
478 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
479 cvmx_write_csr(CVMX_LED_EN, 0);
480 cvmx_write_csr(CVMX_LED_PRT, 0);
481 cvmx_write_csr(CVMX_LED_DBG, 0);
482 cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
483 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
484 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
485 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
486 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
487 cvmx_write_csr(CVMX_LED_EN, 1);
489 #ifdef CONFIG_CAVIUM_RESERVE32
491 * We need to temporarily allocate all memory in the reserve32
492 * region. This makes sure the kernel doesn't allocate this
493 * memory when it is getting memory from the
494 * bootloader. Later, after the memory allocations are
495 * complete, the reserve32 will be freed.
497 * Allocate memory for RESERVED32 aligned on 2MB boundary. This
498 * is in case we later use hugetlb entries with it.
500 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
502 "CAVIUM_RESERVE32", 0);
504 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
506 octeon_reserve32_memory = addr;
509 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
510 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
511 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
513 uint32_t ebase = read_c0_ebase() & 0x3ffff000;
514 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
516 cvmx_l2c_lock_mem_region(ebase, 0x100);
518 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
519 /* General exception */
520 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
522 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
523 /* Interrupt handler */
524 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
526 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
527 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
528 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
530 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
531 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
536 octeon_check_cpu_bist();
538 octeon_uart = octeon_get_boot_uart();
541 * Disable All CIU Interrupts. The ones we need will be
542 * enabled later. Read the SUM register so we know the write
545 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
546 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
547 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
548 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
549 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
552 octeon_write_lcd("LinuxSMP");
554 octeon_write_lcd("Linux");
557 #ifdef CONFIG_CAVIUM_GDB
559 * When debugging the linux kernel, force the cores to enter
560 * the debug exception handler to break in.
562 if (octeon_get_boot_debug_flag()) {
563 cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num());
564 cvmx_read_csr(CVMX_CIU_DINT);
569 * BIST should always be enabled when doing a soft reset. L2
570 * Cache locking for instance is not cleared unless BIST is
571 * enabled. Unfortunately due to a chip errata G-200 for
572 * Cn38XX and CN31XX, BIST msut be disabled on these parts.
574 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
575 OCTEON_IS_MODEL(OCTEON_CN31XX))
576 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
578 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
580 /* Default to 64MB in the simulator to speed things up */
581 if (octeon_is_simulation())
582 MAX_MEMORY = 64ull << 20;
585 argc = octeon_boot_desc_ptr->argc;
586 for (i = 0; i < argc; i++) {
588 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
589 if ((strncmp(arg, "MEM=", 4) == 0) ||
590 (strncmp(arg, "mem=", 4) == 0)) {
591 sscanf(arg + 4, "%llu", &MAX_MEMORY);
594 MAX_MEMORY = 32ull << 30;
595 } else if (strcmp(arg, "ecc_verbose") == 0) {
596 #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC
597 __cvmx_interrupt_ecc_report_single_bit_errors = 1;
598 pr_notice("Reporting of single bit ECC errors is "
601 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
602 sizeof(arcs_cmdline) - 1) {
603 strcat(arcs_cmdline, " ");
604 strcat(arcs_cmdline, arg);
608 if (strstr(arcs_cmdline, "console=") == NULL) {
609 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
610 strcat(arcs_cmdline, " console=ttyS0,115200");
612 if (octeon_uart == 1)
613 strcat(arcs_cmdline, " console=ttyS1,115200");
615 strcat(arcs_cmdline, " console=ttyS0,115200");
619 if (octeon_is_simulation()) {
621 * The simulator uses a mtdram device pre filled with
622 * the filesystem. Also specify the calibration delay
623 * to avoid calculating it every time.
625 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
628 mips_hpt_frequency = octeon_get_clock_rate();
630 octeon_init_cvmcount();
631 octeon_setup_delays();
633 _machine_restart = octeon_restart;
634 _machine_halt = octeon_halt;
636 octeon_user_io_init();
637 register_smp_ops(&octeon_smp_ops);
640 /* Exclude a single page from the regions obtained in plat_mem_setup. */
641 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
643 if (addr > *mem && addr < *mem + *size) {
644 u64 inc = addr - *mem;
645 add_memory_region(*mem, inc, BOOT_MEM_RAM);
650 if (addr == *mem && *size > PAGE_SIZE) {
656 void __init plat_mem_setup(void)
658 uint64_t mem_alloc_size;
664 /* First add the init memory we will be returning. */
665 memory = __pa_symbol(&__init_begin) & PAGE_MASK;
666 mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory;
667 if (mem_alloc_size > 0) {
668 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
669 total += mem_alloc_size;
673 * The Mips memory init uses the first memory location for
674 * some memory vectors. When SPARSEMEM is in use, it doesn't
675 * verify that the size is big enough for the final
676 * vectors. Making the smallest chuck 4MB seems to be enough
677 * to consistantly work.
679 mem_alloc_size = 4 << 20;
680 if (mem_alloc_size > MAX_MEMORY)
681 mem_alloc_size = MAX_MEMORY;
684 * When allocating memory, we want incrementing addresses from
685 * bootmem_alloc so the code in add_memory_region can merge
686 * regions next to each other.
689 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
690 && (total < MAX_MEMORY)) {
691 #if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR)
692 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
693 __pa_symbol(&__init_end), -1,
695 CVMX_BOOTMEM_FLAG_NO_LOCKING);
696 #elif defined(CONFIG_HIGHMEM)
697 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31,
699 CVMX_BOOTMEM_FLAG_NO_LOCKING);
701 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20,
703 CVMX_BOOTMEM_FLAG_NO_LOCKING);
706 u64 size = mem_alloc_size;
709 * exclude a page at the beginning and end of
710 * the 256MB PCIe 'hole' so the kernel will not
711 * try to allocate multi-page buffers that
712 * span the discontinuity.
714 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
716 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
717 CVMX_PCIE_BAR1_PHYS_SIZE,
721 * This function automatically merges address
722 * regions next to each other if they are
723 * received in incrementing order.
726 add_memory_region(memory, size, BOOT_MEM_RAM);
727 total += mem_alloc_size;
732 cvmx_bootmem_unlock();
734 #ifdef CONFIG_CAVIUM_RESERVE32
736 * Now that we've allocated the kernel memory it is safe to
737 * free the reserved region. We free it here so that builtin
738 * drivers can use the memory.
740 if (octeon_reserve32_memory)
741 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
742 #endif /* CONFIG_CAVIUM_RESERVE32 */
745 panic("Unable to allocate memory from "
746 "cvmx_bootmem_phy_alloc\n");
750 * Emit one character to the boot UART. Exported for use by the
753 int prom_putchar(char c)
757 /* Spin until there is room */
759 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
760 } while ((lsrval & 0x20) == 0);
763 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
766 EXPORT_SYMBOL(prom_putchar);
768 void prom_free_prom_memory(void)
770 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
771 /* Check for presence of Core-14449 fix. */
777 asm volatile("# before" : : : "memory");
784 "1:\tlw %0,-12($31)\n\t"
786 : "=r" (insn) : : "$31", "memory");
788 if ((insn >> 26) != 0x33)
789 panic("No PREF instruction at Core-14449 probe point.\n");
791 if (((insn >> 16) & 0x1f) != 28)
792 panic("Core-14449 WAR not in place (%04x).\n"
793 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn);
795 #ifdef CONFIG_CAVIUM_DECODE_RSL
796 cvmx_interrupt_rsl_enable();
798 /* Add an interrupt handler for general failures. */
799 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
800 "RML/RSL", octeon_rlm_interrupt)) {
801 panic("Unable to request_irq(OCTEON_IRQ_RML)\n");