Pileus Git - ~andy/linux/blob - arch/mips/cavium-octeon/csrc-octeon.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2007 by Ralf Baechle
   7  * Copyright (C) 2009, 2012 Cavium, Inc.
   8  */
   9 #include <linux/clocksource.h>
  10 #include <linux/export.h>
  11 #include <linux/init.h>
  12 #include <linux/smp.h>
  13
  14 #include <asm/cpu-info.h>
  15 #include <asm/cpu-type.h>
  16 #include <asm/time.h>
  17
  18 #include <asm/octeon/octeon.h>
  19 #include <asm/octeon/cvmx-ipd-defs.h>
  20 #include <asm/octeon/cvmx-mio-defs.h>
  21
  22
  23 static u64 f;
  24 static u64 rdiv;
  25 static u64 sdiv;
  26 static u64 octeon_udelay_factor;
  27 static u64 octeon_ndelay_factor;
  28
  29 void __init octeon_setup_delays(void)
  30 {
  31         octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
  32         /*
  33          * For __ndelay we divide by 2^16, so the factor is multiplied
  34          * by the same amount.
  35          */
  36         octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
  37
  38         preset_lpj = octeon_get_clock_rate() / HZ;
  39
  40         if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
  41                 union cvmx_mio_rst_boot rst_boot;
  42                 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
  43                 rdiv = rst_boot.s.c_mul;        /* CPU clock */
  44                 sdiv = rst_boot.s.pnr_mul;      /* I/O clock */
  45                 f = (0x8000000000000000ull / sdiv) * 2;
  46         }
  47 }
  48
  49 /*
  50  * Set the current core's cvmcount counter to the value of the
  51  * IPD_CLK_COUNT.  We do this on all cores as they are brought
  52  * on-line.  This allows for a read from a local cpu register to
  53  * access a synchronized counter.
  54  *
  55  * On CPU_CAVIUM_OCTEON2 the IPD_CLK_COUNT is scaled by rdiv/sdiv.
  56  */
  57 void octeon_init_cvmcount(void)
  58 {
  59         unsigned long flags;
  60         unsigned loops = 2;
  61
  62         /* Clobber loops so GCC will not unroll the following while loop. */
  63         asm("" : "+r" (loops));
  64
  65         local_irq_save(flags);
  66         /*
  67          * Loop several times so we are executing from the cache,
  68          * which should give more deterministic timing.
  69          */
  70         while (loops--) {
  71                 u64 ipd_clk_count = cvmx_read_csr(CVMX_IPD_CLK_COUNT);
  72                 if (rdiv != 0) {
  73                         ipd_clk_count *= rdiv;
  74                         if (f != 0) {
  75                                 asm("dmultu\t%[cnt],%[f]\n\t"
  76                                     "mfhi\t%[cnt]"
  77                                     : [cnt] "+r" (ipd_clk_count)
  78                                     : [f] "r" (f)
  79                                     : "hi", "lo");
  80                         }
  81                 }
  82                 write_c0_cvmcount(ipd_clk_count);
  83         }
  84         local_irq_restore(flags);
  85 }
  86
  87 static cycle_t octeon_cvmcount_read(struct clocksource *cs)
  88 {
  89         return read_c0_cvmcount();
  90 }
  91
  92 static struct clocksource clocksource_mips = {
  93         .name           = "OCTEON_CVMCOUNT",
  94         .read           = octeon_cvmcount_read,
  95         .mask           = CLOCKSOURCE_MASK(64),
  96         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  97 };
  98
  99 unsigned long long notrace sched_clock(void)
 100 {
 101         /* 64-bit arithmatic can overflow, so use 128-bit.  */
 102         u64 t1, t2, t3;
 103         unsigned long long rv;
 104         u64 mult = clocksource_mips.mult;
 105         u64 shift = clocksource_mips.shift;
 106         u64 cnt = read_c0_cvmcount();
 107
 108         asm (
 109                 "dmultu\t%[cnt],%[mult]\n\t"
 110                 "nor\t%[t1],$0,%[shift]\n\t"
 111                 "mfhi\t%[t2]\n\t"
 112                 "mflo\t%[t3]\n\t"
 113                 "dsll\t%[t2],%[t2],1\n\t"
 114                 "dsrlv\t%[rv],%[t3],%[shift]\n\t"
 115                 "dsllv\t%[t1],%[t2],%[t1]\n\t"
 116                 "or\t%[rv],%[t1],%[rv]\n\t"
 117                 : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3)
 118                 : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
 119                 : "hi", "lo");
 120         return rv;
 121 }
 122
 123 void __init plat_time_init(void)
 124 {
 125         clocksource_mips.rating = 300;
 126         clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate());
 127 }
 128
 129 void __udelay(unsigned long us)
 130 {
 131         u64 cur, end, inc;
 132
 133         cur = read_c0_cvmcount();
 134
 135         inc = us * octeon_udelay_factor;
 136         end = cur + inc;
 137
 138         while (end > cur)
 139                 cur = read_c0_cvmcount();
 140 }
 141 EXPORT_SYMBOL(__udelay);
 142
 143 void __ndelay(unsigned long ns)
 144 {
 145         u64 cur, end, inc;
 146
 147         cur = read_c0_cvmcount();
 148
 149         inc = ((ns * octeon_ndelay_factor) >> 16);
 150         end = cur + inc;
 151
 152         while (end > cur)
 153                 cur = read_c0_cvmcount();
 154 }
 155 EXPORT_SYMBOL(__ndelay);
 156
 157 void __delay(unsigned long loops)
 158 {
 159         u64 cur, end;
 160
 161         cur = read_c0_cvmcount();
 162         end = cur + loops;
 163
 164         while (end > cur)
 165                 cur = read_c0_cvmcount();
 166 }
 167 EXPORT_SYMBOL(__delay);
 168
 169
 170 /**
 171  * octeon_io_clk_delay - wait for a given number of io clock cycles to pass.
 172  *
 173  * We scale the wait by the clock ratio, and then wait for the
 174  * corresponding number of core clocks.
 175  *
 176  * @count: The number of clocks to wait.
 177  */
 178 void octeon_io_clk_delay(unsigned long count)
 179 {
 180         u64 cur, end;
 181
 182         cur = read_c0_cvmcount();
 183         if (rdiv != 0) {
 184                 end = count * rdiv;
 185                 if (f != 0) {
 186                         asm("dmultu\t%[cnt],%[f]\n\t"
 187                                 "mfhi\t%[cnt]"
 188                                 : [cnt] "+r" (end)
 189                                 : [f] "r" (f)
 190                                 : "hi", "lo");
 191                 }
 192                 end = cur + end;
 193         } else {
 194                 end = cur + count;
 195         }
 196         while (end > cur)
 197                 cur = read_c0_cvmcount();
 198 }
 199 EXPORT_SYMBOL(octeon_io_clk_delay);