Pileus Git - ~andy/linux/blob - arch/mips/ath79/mach-db120.c

   1 /*
   2  * Atheros DB120 reference board support
   3  *
   4  * Copyright (c) 2011 Qualcomm Atheros
   5  * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 #include <linux/pci.h>
  22 #include <linux/ath9k_platform.h>
  23
  24 #include "machtypes.h"
  25 #include "dev-gpio-buttons.h"
  26 #include "dev-leds-gpio.h"
  27 #include "dev-spi.h"
  28 #include "dev-wmac.h"
  29 #include "pci.h"
  30
  31 #define DB120_GPIO_LED_WLAN_5G          12
  32 #define DB120_GPIO_LED_WLAN_2G          13
  33 #define DB120_GPIO_LED_STATUS           14
  34 #define DB120_GPIO_LED_WPS              15
  35
  36 #define DB120_GPIO_BTN_WPS              16
  37
  38 #define DB120_KEYS_POLL_INTERVAL        20      /* msecs */
  39 #define DB120_KEYS_DEBOUNCE_INTERVAL    (3 * DB120_KEYS_POLL_INTERVAL)
  40
  41 #define DB120_WMAC_CALDATA_OFFSET 0x1000
  42 #define DB120_PCIE_CALDATA_OFFSET 0x5000
  43
  44 static struct gpio_led db120_leds_gpio[] __initdata = {
  45         {
  46                 .name           = "db120:green:status",
  47                 .gpio           = DB120_GPIO_LED_STATUS,
  48                 .active_low     = 1,
  49         },
  50         {
  51                 .name           = "db120:green:wps",
  52                 .gpio           = DB120_GPIO_LED_WPS,
  53                 .active_low     = 1,
  54         },
  55         {
  56                 .name           = "db120:green:wlan-5g",
  57                 .gpio           = DB120_GPIO_LED_WLAN_5G,
  58                 .active_low     = 1,
  59         },
  60         {
  61                 .name           = "db120:green:wlan-2g",
  62                 .gpio           = DB120_GPIO_LED_WLAN_2G,
  63                 .active_low     = 1,
  64         },
  65 };
  66
  67 static struct gpio_keys_button db120_gpio_keys[] __initdata = {
  68         {
  69                 .desc           = "WPS button",
  70                 .type           = EV_KEY,
  71                 .code           = KEY_WPS_BUTTON,
  72                 .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL,
  73                 .gpio           = DB120_GPIO_BTN_WPS,
  74                 .active_low     = 1,
  75         },
  76 };
  77
  78 static struct spi_board_info db120_spi_info[] = {
  79         {
  80                 .bus_num        = 0,
  81                 .chip_select    = 0,
  82                 .max_speed_hz   = 25000000,
  83                 .modalias       = "s25sl064a",
  84         }
  85 };
  86
  87 static struct ath79_spi_platform_data db120_spi_data = {
  88         .bus_num        = 0,
  89         .num_chipselect = 1,
  90 };
  91
  92 #ifdef CONFIG_PCI
  93 static struct ath9k_platform_data db120_ath9k_data;
  94
  95 static int db120_pci_plat_dev_init(struct pci_dev *dev)
  96 {
  97         switch (PCI_SLOT(dev->devfn)) {
  98         case 0:
  99                 dev->dev.platform_data = &db120_ath9k_data;
 100                 break;
 101         }
 102
 103         return 0;
 104 }
 105
 106 static void __init db120_pci_init(u8 *eeprom)
 107 {
 108         memcpy(db120_ath9k_data.eeprom_data, eeprom,
 109                sizeof(db120_ath9k_data.eeprom_data));
 110
 111         ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
 112         ath79_register_pci();
 113 }
 114 #else
 115 static inline void db120_pci_init(void) {}
 116 #endif /* CONFIG_PCI */
 117
 118 static void __init db120_setup(void)
 119 {
 120         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 121
 122         ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
 123                                  db120_leds_gpio);
 124         ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
 125                                         ARRAY_SIZE(db120_gpio_keys),
 126                                         db120_gpio_keys);
 127         ath79_register_spi(&db120_spi_data, db120_spi_info,
 128                            ARRAY_SIZE(db120_spi_info));
 129         ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
 130         db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
 131 }
 132
 133 MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
 134              db120_setup);