3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Db1x00 board setup.
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 #include <linux/gpio.h>
31 #include <linux/init.h>
32 #include <linux/interrupt.h>
35 #include <asm/mach-au1x00/au1000.h>
36 #include <asm/mach-au1x00/au1xxx_eth.h>
37 #include <asm/mach-db1x00/db1x00.h>
38 #include <asm/mach-db1x00/bcsr.h>
39 #include <asm/reboot.h>
43 #ifdef CONFIG_MIPS_DB1500
44 char irq_tab_alchemy[][5] __initdata = {
45 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
46 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
49 static void bosporus_power_off(void)
51 printk(KERN_INFO "It's now safe to turn off power\n");
53 asm volatile (".set mips3 ; wait ; .set mips0");
56 const char *get_system_type(void)
58 return "Alchemy Bosporus Gateway Reference";
63 * Micrel/Kendin 5 port switch attached to MAC0,
64 * MAC0 is associated with PHY address 5 (== WAN port)
65 * MAC1 is not associated with any PHY, since it's connected directly
67 * no interrupts are used
69 static struct au1000_eth_platform_data eth0_pdata = {
70 .phy_static_config = 1,
74 #ifdef CONFIG_MIPS_BOSPORUS
75 char irq_tab_alchemy[][5] __initdata = {
76 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
77 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */
78 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
84 #ifdef CONFIG_MIPS_MIRAGE
85 char irq_tab_alchemy[][5] __initdata = {
86 [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
87 [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
88 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
91 static void mirage_power_off(void)
93 alchemy_gpio_direction_output(210, 1);
96 const char *get_system_type(void)
98 return "Alchemy Mirage";
102 #ifdef CONFIG_MIPS_DB1550
103 char irq_tab_alchemy[][5] __initdata = {
104 [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
105 [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
106 [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
110 #if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
111 static void mips_softreset(void)
113 asm volatile ("jr\t%0" : : "r"(0xbfc00000));
118 const char *get_system_type(void)
120 return "Alchemy Db1x00";
124 void __init board_setup(void)
126 unsigned long bcsr1, bcsr2;
129 bcsr1 = DB1000_BCSR_PHYS_ADDR;
130 bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
134 #ifdef CONFIG_MIPS_DB1000
135 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
137 #ifdef CONFIG_MIPS_DB1500
138 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
140 #ifdef CONFIG_MIPS_DB1100
141 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
143 #ifdef CONFIG_MIPS_BOSPORUS
144 au1xxx_override_eth_cfg(0, ð0_pdata);
146 printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
148 #ifdef CONFIG_MIPS_MIRAGE
149 printk(KERN_INFO "AMD Alchemy Mirage Board\n");
151 #ifdef CONFIG_MIPS_DB1550
152 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
154 bcsr1 = DB1550_BCSR_PHYS_ADDR;
155 bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
158 /* initialize board register space */
159 bcsr_init(bcsr1, bcsr2);
161 /* Not valid for Au1550 */
162 #if defined(CONFIG_IRDA) && \
163 (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
164 /* Set IRFIRSEL instead of GPIO15 */
165 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
166 au_writel(pin_func, SYS_PINFUNC);
167 /* Power off until the driver is in use */
168 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
169 BCSR_RESETS_IRDA_MODE_OFF);
171 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
173 /* Enable GPIO[31:0] inputs */
174 alchemy_gpio1_input_enable();
176 #ifdef CONFIG_MIPS_MIRAGE
177 /* GPIO[20] is output */
178 alchemy_gpio_direction_output(20, 0);
180 /* Set GPIO[210:208] instead of SSI_0 */
181 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
183 /* Set GPIO[215:211] for LEDs */
186 /* Set GPIO[214:213] for more LEDs */
189 /* Set GPIO[207:200] instead of PCMCIA/LCD */
190 pin_func |= SYS_PF_LCD | SYS_PF_PC;
191 au_writel(pin_func, SYS_PINFUNC);
194 * Enable speaker amplifier. This should
195 * be part of the audio driver.
197 alchemy_gpio_direction_output(209, 1);
199 pm_power_off = mirage_power_off;
200 _machine_halt = mirage_power_off;
201 _machine_restart = (void(*)(char *))mips_softreset;
204 #ifdef CONFIG_MIPS_BOSPORUS
205 pm_power_off = bosporus_power_off;
206 _machine_halt = bosporus_power_off;
207 _machine_restart = (void(*)(char *))mips_softreset;
212 static int __init db1x00_init_irq(void)
214 #if defined(CONFIG_MIPS_MIRAGE)
215 set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
216 #elif defined(CONFIG_MIPS_DB1550)
217 set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
218 set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
219 set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
220 set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
221 set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
222 set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
223 #elif defined(CONFIG_MIPS_DB1500)
224 set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
225 set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
226 set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
227 set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
228 set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
229 set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
230 #elif defined(CONFIG_MIPS_DB1100)
231 set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
232 set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
233 set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
234 set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
235 set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
236 set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
237 #elif defined(CONFIG_MIPS_DB1000)
238 set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
239 set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
240 set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
241 set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
242 set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
243 set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
247 arch_initcall(db1x00_init_irq);