Pileus Git - ~andy/linux/blob - arch/microblaze/kernel/timer.c

   1 /*
   2  * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2007-2009 PetaLogix
   4  * Copyright (C) 2006 Atmark Techno, Inc.
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License. See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/param.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/profile.h>
  16 #include <linux/irq.h>
  17 #include <linux/delay.h>
  18 #include <linux/sched.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/clocksource.h>
  23 #include <linux/clockchips.h>
  24 #include <linux/io.h>
  25 #include <linux/bug.h>
  26 #include <asm/cpuinfo.h>
  27 #include <asm/setup.h>
  28 #include <asm/prom.h>
  29 #include <asm/irq.h>
  30 #include <linux/cnt32_to_63.h>
  31
  32 static unsigned int timer_baseaddr;
  33
  34 static unsigned int freq_div_hz;
  35 static unsigned int timer_clock_freq;
  36
  37 #define TCSR0   (0x00)
  38 #define TLR0    (0x04)
  39 #define TCR0    (0x08)
  40 #define TCSR1   (0x10)
  41 #define TLR1    (0x14)
  42 #define TCR1    (0x18)
  43
  44 #define TCSR_MDT        (1<<0)
  45 #define TCSR_UDT        (1<<1)
  46 #define TCSR_GENT       (1<<2)
  47 #define TCSR_CAPT       (1<<3)
  48 #define TCSR_ARHT       (1<<4)
  49 #define TCSR_LOAD       (1<<5)
  50 #define TCSR_ENIT       (1<<6)
  51 #define TCSR_ENT        (1<<7)
  52 #define TCSR_TINT       (1<<8)
  53 #define TCSR_PWMA       (1<<9)
  54 #define TCSR_ENALL      (1<<10)
  55
  56 static inline void microblaze_timer0_stop(void)
  57 {
  58         out_be32(timer_baseaddr + TCSR0,
  59                  in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT);
  60 }
  61
  62 static inline void microblaze_timer0_start_periodic(unsigned long load_val)
  63 {
  64         if (!load_val)
  65                 load_val = 1;
  66         /* loading value to timer reg */
  67         out_be32(timer_baseaddr + TLR0, load_val);
  68
  69         /* load the initial value */
  70         out_be32(timer_baseaddr + TCSR0, TCSR_LOAD);
  71
  72         /* see timer data sheet for detail
  73          * !ENALL - don't enable 'em all
  74          * !PWMA - disable pwm
  75          * TINT - clear interrupt status
  76          * ENT- enable timer itself
  77          * ENIT - enable interrupt
  78          * !LOAD - clear the bit to let go
  79          * ARHT - auto reload
  80          * !CAPT - no external trigger
  81          * !GENT - no external signal
  82          * UDT - set the timer as down counter
  83          * !MDT0 - generate mode
  84          */
  85         out_be32(timer_baseaddr + TCSR0,
  86                         TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
  87 }
  88
  89 static inline void microblaze_timer0_start_oneshot(unsigned long load_val)
  90 {
  91         if (!load_val)
  92                 load_val = 1;
  93         /* loading value to timer reg */
  94         out_be32(timer_baseaddr + TLR0, load_val);
  95
  96         /* load the initial value */
  97         out_be32(timer_baseaddr + TCSR0, TCSR_LOAD);
  98
  99         out_be32(timer_baseaddr + TCSR0,
 100                         TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
 101 }
 102
 103 static int microblaze_timer_set_next_event(unsigned long delta,
 104                                         struct clock_event_device *dev)
 105 {
 106         pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
 107         microblaze_timer0_start_oneshot(delta);
 108         return 0;
 109 }
 110
 111 static void microblaze_timer_set_mode(enum clock_event_mode mode,
 112                                 struct clock_event_device *evt)
 113 {
 114         switch (mode) {
 115         case CLOCK_EVT_MODE_PERIODIC:
 116                 pr_info("%s: periodic\n", __func__);
 117                 microblaze_timer0_start_periodic(freq_div_hz);
 118                 break;
 119         case CLOCK_EVT_MODE_ONESHOT:
 120                 pr_info("%s: oneshot\n", __func__);
 121                 break;
 122         case CLOCK_EVT_MODE_UNUSED:
 123                 pr_info("%s: unused\n", __func__);
 124                 break;
 125         case CLOCK_EVT_MODE_SHUTDOWN:
 126                 pr_info("%s: shutdown\n", __func__);
 127                 microblaze_timer0_stop();
 128                 break;
 129         case CLOCK_EVT_MODE_RESUME:
 130                 pr_info("%s: resume\n", __func__);
 131                 break;
 132         }
 133 }
 134
 135 static struct clock_event_device clockevent_microblaze_timer = {
 136         .name           = "microblaze_clockevent",
 137         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 138         .shift          = 8,
 139         .rating         = 300,
 140         .set_next_event = microblaze_timer_set_next_event,
 141         .set_mode       = microblaze_timer_set_mode,
 142 };
 143
 144 static inline void timer_ack(void)
 145 {
 146         out_be32(timer_baseaddr + TCSR0, in_be32(timer_baseaddr + TCSR0));
 147 }
 148
 149 static irqreturn_t timer_interrupt(int irq, void *dev_id)
 150 {
 151         struct clock_event_device *evt = &clockevent_microblaze_timer;
 152 #ifdef CONFIG_HEART_BEAT
 153         heartbeat();
 154 #endif
 155         timer_ack();
 156         evt->event_handler(evt);
 157         return IRQ_HANDLED;
 158 }
 159
 160 static struct irqaction timer_irqaction = {
 161         .handler = timer_interrupt,
 162         .flags = IRQF_DISABLED | IRQF_TIMER,
 163         .name = "timer",
 164         .dev_id = &clockevent_microblaze_timer,
 165 };
 166
 167 static __init void microblaze_clockevent_init(void)
 168 {
 169         clockevent_microblaze_timer.mult =
 170                 div_sc(timer_clock_freq, NSEC_PER_SEC,
 171                                 clockevent_microblaze_timer.shift);
 172         clockevent_microblaze_timer.max_delta_ns =
 173                 clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer);
 174         clockevent_microblaze_timer.min_delta_ns =
 175                 clockevent_delta2ns(1, &clockevent_microblaze_timer);
 176         clockevent_microblaze_timer.cpumask = cpumask_of(0);
 177         clockevents_register_device(&clockevent_microblaze_timer);
 178 }
 179
 180 static cycle_t microblaze_read(struct clocksource *cs)
 181 {
 182         /* reading actual value of timer 1 */
 183         return (cycle_t) (in_be32(timer_baseaddr + TCR1));
 184 }
 185
 186 static struct timecounter microblaze_tc = {
 187         .cc = NULL,
 188 };
 189
 190 static cycle_t microblaze_cc_read(const struct cyclecounter *cc)
 191 {
 192         return microblaze_read(NULL);
 193 }
 194
 195 static struct cyclecounter microblaze_cc = {
 196         .read = microblaze_cc_read,
 197         .mask = CLOCKSOURCE_MASK(32),
 198         .shift = 8,
 199 };
 200
 201 static int __init init_microblaze_timecounter(void)
 202 {
 203         microblaze_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC,
 204                                 microblaze_cc.shift);
 205
 206         timecounter_init(&microblaze_tc, &microblaze_cc, sched_clock());
 207
 208         return 0;
 209 }
 210
 211 static struct clocksource clocksource_microblaze = {
 212         .name           = "microblaze_clocksource",
 213         .rating         = 300,
 214         .read           = microblaze_read,
 215         .mask           = CLOCKSOURCE_MASK(32),
 216         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 217 };
 218
 219 static int __init microblaze_clocksource_init(void)
 220 {
 221         if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq))
 222                 panic("failed to register clocksource");
 223
 224         /* stop timer1 */
 225         out_be32(timer_baseaddr + TCSR1,
 226                  in_be32(timer_baseaddr + TCSR1) & ~TCSR_ENT);
 227         /* start timer1 - up counting without interrupt */
 228         out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);
 229
 230         /* register timecounter - for ftrace support */
 231         init_microblaze_timecounter();
 232         return 0;
 233 }
 234
 235 /*
 236  * We have to protect accesses before timer initialization
 237  * and return 0 for sched_clock function below.
 238  */
 239 static int timer_initialized;
 240
 241 static void __init xilinx_timer_init(struct device_node *timer)
 242 {
 243         u32 irq;
 244         u32 timer_num = 1;
 245         const void *prop;
 246
 247         timer_baseaddr = be32_to_cpup(of_get_property(timer, "reg", NULL));
 248         timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);
 249         irq = irq_of_parse_and_map(timer, 0);
 250         timer_num = be32_to_cpup(of_get_property(timer,
 251                                                 "xlnx,one-timer-only", NULL));
 252         if (timer_num) {
 253                 pr_emerg("Please   enable two timers in HW\n");
 254                 BUG();
 255         }
 256
 257         pr_info("%s #0 at 0x%08x, irq=%d\n",
 258                 timer->name, timer_baseaddr, irq);
 259
 260         /* If there is clock-frequency property than use it */
 261         prop = of_get_property(timer, "clock-frequency", NULL);
 262         if (prop)
 263                 timer_clock_freq = be32_to_cpup(prop);
 264         else
 265                 timer_clock_freq = cpuinfo.cpu_clock_freq;
 266
 267         freq_div_hz = timer_clock_freq / HZ;
 268
 269         setup_irq(irq, &timer_irqaction);
 270 #ifdef CONFIG_HEART_BEAT
 271         setup_heartbeat();
 272 #endif
 273         microblaze_clocksource_init();
 274         microblaze_clockevent_init();
 275         timer_initialized = 1;
 276 }
 277
 278 unsigned long long notrace sched_clock(void)
 279 {
 280         if (timer_initialized) {
 281                 struct clocksource *cs = &clocksource_microblaze;
 282
 283                 cycle_t cyc = cnt32_to_63(cs->read(NULL)) & LLONG_MAX;
 284                 return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
 285         }
 286         return 0;
 287 }
 288
 289 CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a",
 290                        xilinx_timer_init);