2 * Copyright (C) 2009,2010,2011 Imagination Technologies Ltd.
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/atomic.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
14 #include <linux/sched.h>
15 #include <linux/interrupt.h>
16 #include <linux/cache.h>
17 #include <linux/profile.h>
18 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/cpu.h>
22 #include <linux/smp.h>
23 #include <linux/seq_file.h>
24 #include <linux/irq.h>
25 #include <linux/bootmem.h>
27 #include <asm/cacheflush.h>
28 #include <asm/cachepart.h>
29 #include <asm/core_reg.h>
31 #include <asm/global_lock.h>
32 #include <asm/metag_mem.h>
33 #include <asm/mmu_context.h>
34 #include <asm/pgtable.h>
35 #include <asm/pgalloc.h>
36 #include <asm/processor.h>
37 #include <asm/setup.h>
38 #include <asm/tlbflush.h>
39 #include <asm/hwthread.h>
40 #include <asm/traps.h>
42 #define SYSC_DCPART(n) (SYSC_DCPART0 + SYSC_xCPARTn_STRIDE * (n))
43 #define SYSC_ICPART(n) (SYSC_ICPART0 + SYSC_xCPARTn_STRIDE * (n))
45 DECLARE_PER_CPU(PTBI, pTBI);
47 void *secondary_data_stack;
50 * structures for inter-processor calls
51 * - A collection of single bit ipi messages.
55 unsigned long ipi_count;
59 static DEFINE_PER_CPU(struct ipi_data, ipi_data) = {
60 .lock = __SPIN_LOCK_UNLOCKED(ipi_data.lock),
63 static DEFINE_SPINLOCK(boot_lock);
66 * "thread" is assumed to be a valid Meta hardware thread ID.
68 int __cpuinit boot_secondary(unsigned int thread, struct task_struct *idle)
73 * set synchronisation state between this boot processor
74 * and the secondary one
76 spin_lock(&boot_lock);
78 core_reg_write(TXUPC_ID, 0, thread, (unsigned int)secondary_startup);
79 core_reg_write(TXUPC_ID, 1, thread, 0);
82 * Give the thread privilege (PSTAT) and clear potentially problematic
83 * bits in the process (namely ISTAT, CBMarker, CBMarkerI, LSM_STEP).
85 core_reg_write(TXUCT_ID, TXSTATUS_REGNUM, thread, TXSTATUS_PSTAT_BIT);
87 /* Clear the minim enable bit. */
88 val = core_reg_read(TXUCT_ID, TXPRIVEXT_REGNUM, thread);
89 core_reg_write(TXUCT_ID, TXPRIVEXT_REGNUM, thread, val & ~0x80);
92 * set the ThreadEnable bit (0x1) in the TXENABLE register
93 * for the specified thread - off it goes!
95 val = core_reg_read(TXUCT_ID, TXENABLE_REGNUM, thread);
96 core_reg_write(TXUCT_ID, TXENABLE_REGNUM, thread, val | 0x1);
99 * now the secondary core is starting up let it run its
100 * calibrations, then wait for it to finish
102 spin_unlock(&boot_lock);
108 * describe_cachepart_change: describe a change to cache partitions.
109 * @thread: Hardware thread number.
110 * @label: Label of cache type, e.g. "dcache" or "icache".
111 * @sz: Total size of the cache.
112 * @old: Old cache partition configuration (*CPART* register).
113 * @new: New cache partition configuration (*CPART* register).
115 * If the cache partition has changed, prints a message to the log describing
118 static __cpuinit void describe_cachepart_change(unsigned int thread,
124 unsigned int lor1, land1, gor1, gand1;
125 unsigned int lor2, land2, gor2, gand2;
126 unsigned int diff = old ^ new;
131 pr_info("Thread %d: %s partition changed:", thread, label);
132 if (diff & (SYSC_xCPARTL_OR_BITS | SYSC_xCPARTL_AND_BITS)) {
133 lor1 = (old & SYSC_xCPARTL_OR_BITS) >> SYSC_xCPARTL_OR_S;
134 lor2 = (new & SYSC_xCPARTL_OR_BITS) >> SYSC_xCPARTL_OR_S;
135 land1 = (old & SYSC_xCPARTL_AND_BITS) >> SYSC_xCPARTL_AND_S;
136 land2 = (new & SYSC_xCPARTL_AND_BITS) >> SYSC_xCPARTL_AND_S;
137 pr_cont(" L:%#x+%#x->%#x+%#x",
139 ((land1 + 1) * sz) >> 4,
141 ((land2 + 1) * sz) >> 4);
143 if (diff & (SYSC_xCPARTG_OR_BITS | SYSC_xCPARTG_AND_BITS)) {
144 gor1 = (old & SYSC_xCPARTG_OR_BITS) >> SYSC_xCPARTG_OR_S;
145 gor2 = (new & SYSC_xCPARTG_OR_BITS) >> SYSC_xCPARTG_OR_S;
146 gand1 = (old & SYSC_xCPARTG_AND_BITS) >> SYSC_xCPARTG_AND_S;
147 gand2 = (new & SYSC_xCPARTG_AND_BITS) >> SYSC_xCPARTG_AND_S;
148 pr_cont(" G:%#x+%#x->%#x+%#x",
150 ((gand1 + 1) * sz) >> 4,
152 ((gand2 + 1) * sz) >> 4);
154 if (diff & SYSC_CWRMODE_BIT)
156 (new & SYSC_CWRMODE_BIT) ? "+" : "-");
157 if (diff & SYSC_DCPART_GCON_BIT)
159 (new & SYSC_DCPART_GCON_BIT) ? "+" : "-");
164 * setup_smp_cache: ensure cache coherency for new SMP thread.
165 * @thread: New hardware thread number.
167 * Ensures that coherency is enabled and that the threads share the same cache
170 static __cpuinit void setup_smp_cache(unsigned int thread)
172 unsigned int this_thread, lflags;
173 unsigned int dcsz, dcpart_this, dcpart_old, dcpart_new;
174 unsigned int icsz, icpart_old, icpart_new;
177 * Copy over the current thread's cache partition configuration to the
178 * new thread so that they share cache partitions.
180 __global_lock2(lflags);
181 this_thread = hard_processor_id();
182 /* Share dcache partition */
183 dcpart_this = metag_in32(SYSC_DCPART(this_thread));
184 dcpart_old = metag_in32(SYSC_DCPART(thread));
185 dcpart_new = dcpart_this;
186 #if PAGE_OFFSET < LINGLOBAL_BASE
188 * For the local data cache to be coherent the threads must also have
191 dcpart_new |= SYSC_DCPART_GCON_BIT;
192 metag_out32(dcpart_new, SYSC_DCPART(this_thread));
194 metag_out32(dcpart_new, SYSC_DCPART(thread));
195 /* Share icache partition too */
196 icpart_new = metag_in32(SYSC_ICPART(this_thread));
197 icpart_old = metag_in32(SYSC_ICPART(thread));
198 metag_out32(icpart_new, SYSC_ICPART(thread));
199 __global_unlock2(lflags);
202 * Log if the cache partitions were altered so the user is aware of any
203 * potential unintentional cache wastage.
205 dcsz = get_dcache_size();
206 icsz = get_dcache_size();
207 describe_cachepart_change(this_thread, "dcache", dcsz,
208 dcpart_this, dcpart_new);
209 describe_cachepart_change(thread, "dcache", dcsz,
210 dcpart_old, dcpart_new);
211 describe_cachepart_change(thread, "icache", icsz,
212 icpart_old, icpart_new);
215 int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
217 unsigned int thread = cpu_2_hwthread_id[cpu];
220 load_pgd(swapper_pg_dir, thread);
224 setup_smp_cache(thread);
227 * Tell the secondary CPU where to find its idle thread's stack.
229 secondary_data_stack = task_stack_page(idle);
234 * Now bring the CPU into our world.
236 ret = boot_secondary(thread, idle);
238 unsigned long timeout;
241 * CPU was successfully started, wait for it
242 * to come online or time out.
244 timeout = jiffies + HZ;
245 while (time_before(jiffies, timeout)) {
253 if (!cpu_online(cpu))
257 secondary_data_stack = NULL;
260 pr_crit("CPU%u: processor failed to boot\n", cpu);
263 * FIXME: We need to clean up the new idle thread. --rmk
270 #ifdef CONFIG_HOTPLUG_CPU
271 static DECLARE_COMPLETION(cpu_killed);
274 * __cpu_disable runs on the processor to be shutdown.
276 int __cpuexit __cpu_disable(void)
278 unsigned int cpu = smp_processor_id();
281 * Take this CPU offline. Once we clear this, we can't return,
282 * and we must not schedule until we're ready to give up the cpu.
284 set_cpu_online(cpu, false);
287 * OK - migrate IRQs away from this CPU
292 * Flush user cache and TLB mappings, and then remove this CPU
293 * from the vm mask set of all processes.
296 local_flush_tlb_all();
298 clear_tasks_mm_cpumask(cpu);
304 * called on the thread which is asking for a CPU to be shutdown -
305 * waits until shutdown has completed, or it is timed out.
307 void __cpuexit __cpu_die(unsigned int cpu)
309 if (!wait_for_completion_timeout(&cpu_killed, msecs_to_jiffies(1)))
310 pr_err("CPU%u: unable to kill\n", cpu);
314 * Called from the idle thread for the CPU which has been shutdown.
316 * Note that we do not return from this function. If this cpu is
317 * brought online again it will need to run secondary_startup().
319 void __cpuexit cpu_die(void)
324 complete(&cpu_killed);
326 asm ("XOR TXENABLE, D0Re0,D0Re0\n");
328 #endif /* CONFIG_HOTPLUG_CPU */
331 * Called by both boot and secondaries to move global data into
332 * per-processor storage.
334 void __cpuinit smp_store_cpu_info(unsigned int cpuid)
336 struct cpuinfo_metag *cpu_info = &per_cpu(cpu_data, cpuid);
338 cpu_info->loops_per_jiffy = loops_per_jiffy;
342 * This is the secondary CPU boot entry. We're using this CPUs
343 * idle thread stack and the global page tables.
345 asmlinkage void secondary_start_kernel(void)
347 struct mm_struct *mm = &init_mm;
348 unsigned int cpu = smp_processor_id();
351 * All kernel threads share the same mm context; grab a
352 * reference and switch to it.
354 atomic_inc(&mm->mm_users);
355 atomic_inc(&mm->mm_count);
356 current->active_mm = mm;
357 cpumask_set_cpu(cpu, mm_cpumask(mm));
358 enter_lazy_tlb(mm, current);
359 local_flush_tlb_all();
362 * TODO: Some day it might be useful for each Linux CPU to
363 * have its own TBI structure. That would allow each Linux CPU
364 * to run different interrupt handlers for the same IRQ
367 * For now, simply copying the pointer to the boot CPU's TBI
368 * structure is sufficient because we always want to run the
369 * same interrupt handler whatever CPU takes the interrupt.
371 per_cpu(pTBI, cpu) = __TBI(TBID_ISTAT_BIT);
373 if (!per_cpu(pTBI, cpu))
374 panic("No TBI found!");
376 per_cpu_trap_init(cpu);
382 notify_cpu_starting(cpu);
384 pr_info("CPU%u (thread %u): Booted secondary processor\n",
385 cpu, cpu_2_hwthread_id[cpu]);
388 smp_store_cpu_info(cpu);
391 * OK, now it's safe to let the boot CPU continue
393 set_cpu_online(cpu, true);
396 * Enable local interrupts.
398 tbi_startup_interrupt(TBID_SIGNUM_TRT);
402 * OK, it's off to the idle thread for us
404 cpu_startup_entry(CPUHP_ONLINE);
407 void __init smp_cpus_done(unsigned int max_cpus)
410 unsigned long bogosum = 0;
412 for_each_online_cpu(cpu)
413 bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
415 pr_info("SMP: Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
417 bogosum / (500000/HZ),
418 (bogosum / (5000/HZ)) % 100);
421 void __init smp_prepare_cpus(unsigned int max_cpus)
423 unsigned int cpu = smp_processor_id();
425 init_new_context(current, &init_mm);
426 current_thread_info()->cpu = cpu;
428 smp_store_cpu_info(cpu);
429 init_cpu_present(cpu_possible_mask);
432 void __init smp_prepare_boot_cpu(void)
434 unsigned int cpu = smp_processor_id();
436 per_cpu(pTBI, cpu) = __TBI(TBID_ISTAT_BIT);
438 if (!per_cpu(pTBI, cpu))
439 panic("No TBI found!");
442 static void smp_cross_call(cpumask_t callmap, enum ipi_msg_type msg);
444 static void send_ipi_message(const struct cpumask *mask, enum ipi_msg_type msg)
451 local_irq_save(flags);
453 for_each_cpu(cpu, mask) {
454 struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
456 spin_lock(&ipi->lock);
459 * KICK interrupts are queued in hardware so we'll get
460 * multiple interrupts if we call smp_cross_call()
461 * multiple times for one msg. The problem is that we
462 * only have one bit for each message - we can't queue
465 * The first time through ipi_handler() we'll clear
466 * the msg bit, having done all the work. But when we
467 * return we'll get _another_ interrupt (and another,
468 * and another until we've handled all the queued
469 * KICKs). Running ipi_handler() when there's no work
470 * to do is bad because that's how kick handler
471 * chaining detects who the KICK was intended for.
472 * See arch/metag/kernel/kick.c for more details.
474 * So only add 'cpu' to 'map' if we haven't already
475 * queued a KICK interrupt for 'msg'.
477 if (!(ipi->bits & (1 << msg))) {
478 ipi->bits |= 1 << msg;
479 cpumask_set_cpu(cpu, &map);
482 spin_unlock(&ipi->lock);
486 * Call the platform specific cross-CPU call function.
488 smp_cross_call(map, msg);
490 local_irq_restore(flags);
493 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
495 send_ipi_message(mask, IPI_CALL_FUNC);
498 void arch_send_call_function_single_ipi(int cpu)
500 send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
503 void show_ipi_list(struct seq_file *p)
509 for_each_present_cpu(cpu)
510 seq_printf(p, " %10lu", per_cpu(ipi_data, cpu).ipi_count);
515 static DEFINE_SPINLOCK(stop_lock);
518 * Main handler for inter-processor interrupts
520 * For Meta, the ipimask now only identifies a single
521 * category of IPI (Bit 1 IPIs have been replaced by a
522 * different mechanism):
524 * Bit 0 - Inter-processor function call
526 static int do_IPI(struct pt_regs *regs)
528 unsigned int cpu = smp_processor_id();
529 struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
530 struct pt_regs *old_regs = set_irq_regs(regs);
531 unsigned long msgs, nextmsg;
536 spin_lock(&ipi->lock);
538 nextmsg = msgs & -msgs;
539 ipi->bits &= ~nextmsg;
540 spin_unlock(&ipi->lock);
545 nextmsg = ffz(~nextmsg);
552 generic_smp_call_function_interrupt();
555 case IPI_CALL_FUNC_SINGLE:
556 generic_smp_call_function_single_interrupt();
560 pr_crit("CPU%u: Unknown IPI message 0x%lx\n",
566 set_irq_regs(old_regs);
571 void smp_send_reschedule(int cpu)
573 send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
576 static void stop_this_cpu(void *data)
578 unsigned int cpu = smp_processor_id();
580 if (system_state == SYSTEM_BOOTING ||
581 system_state == SYSTEM_RUNNING) {
582 spin_lock(&stop_lock);
583 pr_crit("CPU%u: stopping\n", cpu);
585 spin_unlock(&stop_lock);
588 set_cpu_online(cpu, false);
592 hard_processor_halt(HALT_OK);
595 void smp_send_stop(void)
597 smp_call_function(stop_this_cpu, NULL, 0);
603 int setup_profiling_timer(unsigned int multiplier)
609 * We use KICKs for inter-processor interrupts.
611 * For every CPU in "callmap" the IPI data must already have been
612 * stored in that CPU's "ipi_data" member prior to calling this
615 static void kick_raise_softirq(cpumask_t callmap, unsigned int irq)
619 for_each_cpu(cpu, &callmap) {
622 thread = cpu_2_hwthread_id[cpu];
624 BUG_ON(thread == BAD_HWTHREAD_ID);
626 metag_out32(1, T0KICKI + (thread * TnXKICK_STRIDE));
630 static TBIRES ipi_handler(TBIRES State, int SigNum, int Triggers,
631 int Inst, PTBI pTBI, int *handled)
633 *handled = do_IPI((struct pt_regs *)State.Sig.pCtx);
638 static struct kick_irq_handler ipi_irq = {
642 static void smp_cross_call(cpumask_t callmap, enum ipi_msg_type msg)
644 kick_raise_softirq(callmap, 1);
647 static inline unsigned int get_core_count(void)
650 unsigned int ret = 0;
652 for (i = 0; i < CONFIG_NR_CPUS; i++) {
653 if (core_reg_read(TXUCT_ID, TXENABLE_REGNUM, i))
661 * Initialise the CPU possible map early - this describes the CPUs
662 * which may be present or become present in the system.
664 void __init smp_init_cpus(void)
666 unsigned int i, ncores = get_core_count();
668 /* If no hwthread_map early param was set use default mapping */
669 for (i = 0; i < NR_CPUS; i++)
670 if (cpu_2_hwthread_id[i] == BAD_HWTHREAD_ID) {
671 cpu_2_hwthread_id[i] = i;
672 hwthread_id_2_cpu[i] = i;
675 for (i = 0; i < ncores; i++)
676 set_cpu_possible(i, true);
678 kick_register_func(&ipi_irq);