2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/kernel.h>
41 #include <linux/sched.h>
42 #include <linux/kernel_stat.h>
43 #include <linux/smp_lock.h>
44 #include <linux/bootmem.h>
45 #include <linux/notifier.h>
46 #include <linux/cpu.h>
47 #include <linux/percpu.h>
49 #include <linux/delay.h>
50 #include <linux/mc146818rtc.h>
51 #include <asm/tlbflush.h>
53 #include <asm/arch_hooks.h>
57 #include <mach_apic.h>
58 #include <mach_wakecpu.h>
59 #include <smpboot_hooks.h>
61 /* Set if we find a B stepping CPU */
62 static int __devinitdata smp_b_stepping;
64 /* Number of siblings per CPU package */
65 int smp_num_siblings = 1;
67 EXPORT_SYMBOL(smp_num_siblings);
70 /* Last level cache ID of each logical CPU */
71 int cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID};
73 /* representing HT siblings of each logical CPU */
74 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
75 EXPORT_SYMBOL(cpu_sibling_map);
77 /* representing HT and core siblings of each logical CPU */
78 cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
79 EXPORT_SYMBOL(cpu_core_map);
81 /* bitmap of online cpus */
82 cpumask_t cpu_online_map __read_mostly;
83 EXPORT_SYMBOL(cpu_online_map);
85 cpumask_t cpu_callin_map;
86 cpumask_t cpu_callout_map;
87 EXPORT_SYMBOL(cpu_callout_map);
88 cpumask_t cpu_possible_map;
89 EXPORT_SYMBOL(cpu_possible_map);
90 static cpumask_t smp_commenced_mask;
92 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
93 * is no way to resync one AP against BP. TBD: for prescott and above, we
94 * should use IA64's algorithm
96 static int __devinitdata tsc_sync_disabled;
98 /* Per CPU bogomips and other parameters */
99 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
100 EXPORT_SYMBOL(cpu_data);
102 u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
103 { [0 ... NR_CPUS-1] = 0xff };
104 EXPORT_SYMBOL(x86_cpu_to_apicid);
106 u8 apicid_2_node[MAX_APICID];
109 * Trampoline 80x86 program as an array.
112 extern unsigned char trampoline_data [];
113 extern unsigned char trampoline_end [];
114 static unsigned char *trampoline_base;
115 static int trampoline_exec;
117 static void map_cpu_to_logical_apicid(void);
119 /* State of each CPU. */
120 DEFINE_PER_CPU(int, cpu_state) = { 0 };
123 * Currently trivial. Write the real->protected mode
124 * bootstrap into the page concerned. The caller
125 * has made sure it's suitably aligned.
128 static unsigned long __devinit setup_trampoline(void)
130 memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
131 return virt_to_phys(trampoline_base);
135 * We are called very early to get the low memory for the
136 * SMP bootup trampoline page.
138 void __init smp_alloc_memory(void)
140 trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
142 * Has to be in very low memory so we can execute
145 if (__pa(trampoline_base) >= 0x9F000)
148 * Make the SMP trampoline executable:
150 trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1);
154 * The bootstrap kernel entry code has set these up. Save them for
158 static void __devinit smp_store_cpu_info(int id)
160 struct cpuinfo_x86 *c = cpu_data + id;
166 * Mask B, Pentium, but not Pentium MMX
168 if (c->x86_vendor == X86_VENDOR_INTEL &&
170 c->x86_mask >= 1 && c->x86_mask <= 4 &&
173 * Remember we have B step Pentia with bugs
178 * Certain Athlons might work (for various values of 'work') in SMP
179 * but they are not certified as MP capable.
181 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
183 if (num_possible_cpus() == 1)
186 /* Athlon 660/661 is valid. */
187 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
190 /* Duron 670 is valid */
191 if ((c->x86_model==7) && (c->x86_mask==0))
195 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
196 * It's worth noting that the A5 stepping (662) of some Athlon XP's
197 * have the MP bit set.
198 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
200 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
201 ((c->x86_model==7) && (c->x86_mask>=1)) ||
206 /* If we get here, it's not a certified SMP capable AMD system. */
207 add_taint(TAINT_UNSAFE_SMP);
215 * TSC synchronization.
217 * We first check whether all CPUs have their TSC's synchronized,
218 * then we print a warning if not, and always resync.
223 atomic_t count_start;
225 unsigned long long values[NR_CPUS];
227 .start_flag = ATOMIC_INIT(0),
228 .count_start = ATOMIC_INIT(0),
229 .count_stop = ATOMIC_INIT(0),
234 static void __init synchronize_tsc_bp(void)
237 unsigned long long t0;
238 unsigned long long sum, avg;
240 unsigned int one_usec;
243 printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus());
245 /* convert from kcyc/sec to cyc/usec */
246 one_usec = cpu_khz / 1000;
248 atomic_set(&tsc.start_flag, 1);
252 * We loop a few times to get a primed instruction cache,
253 * then the last pass is more or less synchronized and
254 * the BP and APs set their cycle counters to zero all at
255 * once. This reduces the chance of having random offsets
256 * between the processors, and guarantees that the maximum
257 * delay between the cycle counters is never bigger than
258 * the latency of information-passing (cachelines) between
261 for (i = 0; i < NR_LOOPS; i++) {
263 * all APs synchronize but they loop on '== num_cpus'
265 while (atomic_read(&tsc.count_start) != num_booting_cpus()-1)
267 atomic_set(&tsc.count_stop, 0);
270 * this lets the APs save their current TSC:
272 atomic_inc(&tsc.count_start);
274 rdtscll(tsc.values[smp_processor_id()]);
276 * We clear the TSC in the last loop:
282 * Wait for all APs to leave the synchronization point:
284 while (atomic_read(&tsc.count_stop) != num_booting_cpus()-1)
286 atomic_set(&tsc.count_start, 0);
288 atomic_inc(&tsc.count_stop);
292 for (i = 0; i < NR_CPUS; i++) {
293 if (cpu_isset(i, cpu_callout_map)) {
299 do_div(avg, num_booting_cpus());
301 for (i = 0; i < NR_CPUS; i++) {
302 if (!cpu_isset(i, cpu_callout_map))
304 delta = tsc.values[i] - avg;
308 * We report bigger than 2 microseconds clock differences.
310 if (delta > 2*one_usec) {
318 do_div(realdelta, one_usec);
319 if (tsc.values[i] < avg)
320 realdelta = -realdelta;
323 printk(KERN_INFO "CPU#%d had %Ld usecs TSC "
324 "skew, fixed it up.\n", i, realdelta);
331 static void __init synchronize_tsc_ap(void)
336 * Not every cpu is online at the time
337 * this gets called, so we first wait for the BP to
338 * finish SMP initialization:
340 while (!atomic_read(&tsc.start_flag))
343 for (i = 0; i < NR_LOOPS; i++) {
344 atomic_inc(&tsc.count_start);
345 while (atomic_read(&tsc.count_start) != num_booting_cpus())
348 rdtscll(tsc.values[smp_processor_id()]);
352 atomic_inc(&tsc.count_stop);
353 while (atomic_read(&tsc.count_stop) != num_booting_cpus())
359 extern void calibrate_delay(void);
361 static atomic_t init_deasserted;
363 static void __devinit smp_callin(void)
366 unsigned long timeout;
369 * If waken up by an INIT in an 82489DX configuration
370 * we may get here before an INIT-deassert IPI reaches
371 * our local APIC. We have to wait for the IPI or we'll
372 * lock up on an APIC access.
374 wait_for_init_deassert(&init_deasserted);
377 * (This works even if the APIC is not enabled.)
379 phys_id = GET_APIC_ID(apic_read(APIC_ID));
380 cpuid = smp_processor_id();
381 if (cpu_isset(cpuid, cpu_callin_map)) {
382 printk("huh, phys CPU#%d, CPU#%d already present??\n",
386 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
389 * STARTUP IPIs are fragile beasts as they might sometimes
390 * trigger some glue motherboard logic. Complete APIC bus
391 * silence for 1 second, this overestimates the time the
392 * boot CPU is spending to send the up to 2 STARTUP IPIs
393 * by a factor of two. This should be enough.
397 * Waiting 2s total for startup (udelay is not yet working)
399 timeout = jiffies + 2*HZ;
400 while (time_before(jiffies, timeout)) {
402 * Has the boot CPU finished it's STARTUP sequence?
404 if (cpu_isset(cpuid, cpu_callout_map))
409 if (!time_before(jiffies, timeout)) {
410 printk("BUG: CPU%d started up but did not get a callout!\n",
416 * the boot CPU has finished the init stage and is spinning
417 * on callin_map until we finish. We are free to set up this
418 * CPU, first the APIC. (this is probably redundant on most
422 Dprintk("CALLIN, before setup_local_APIC().\n");
423 smp_callin_clear_local_apic();
425 map_cpu_to_logical_apicid();
431 Dprintk("Stack at about %p\n",&cpuid);
434 * Save our processor parameters
436 smp_store_cpu_info(cpuid);
438 disable_APIC_timer();
441 * Allow the master to continue.
443 cpu_set(cpuid, cpu_callin_map);
446 * Synchronize the TSC with the BP
448 if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled)
449 synchronize_tsc_ap();
454 /* maps the cpu to the sched domain representing multi-core */
455 cpumask_t cpu_coregroup_map(int cpu)
457 struct cpuinfo_x86 *c = cpu_data + cpu;
459 * For perf, we return last level cache shared map.
460 * And for power savings, we return cpu_core_map
462 if (sched_mc_power_savings || sched_smt_power_savings)
463 return cpu_core_map[cpu];
465 return c->llc_shared_map;
468 /* representing cpus for which sibling maps can be computed */
469 static cpumask_t cpu_sibling_setup_map;
472 set_cpu_sibling_map(int cpu)
475 struct cpuinfo_x86 *c = cpu_data;
477 cpu_set(cpu, cpu_sibling_setup_map);
479 if (smp_num_siblings > 1) {
480 for_each_cpu_mask(i, cpu_sibling_setup_map) {
481 if (c[cpu].phys_proc_id == c[i].phys_proc_id &&
482 c[cpu].cpu_core_id == c[i].cpu_core_id) {
483 cpu_set(i, cpu_sibling_map[cpu]);
484 cpu_set(cpu, cpu_sibling_map[i]);
485 cpu_set(i, cpu_core_map[cpu]);
486 cpu_set(cpu, cpu_core_map[i]);
487 cpu_set(i, c[cpu].llc_shared_map);
488 cpu_set(cpu, c[i].llc_shared_map);
492 cpu_set(cpu, cpu_sibling_map[cpu]);
495 cpu_set(cpu, c[cpu].llc_shared_map);
497 if (current_cpu_data.x86_max_cores == 1) {
498 cpu_core_map[cpu] = cpu_sibling_map[cpu];
499 c[cpu].booted_cores = 1;
503 for_each_cpu_mask(i, cpu_sibling_setup_map) {
504 if (cpu_llc_id[cpu] != BAD_APICID &&
505 cpu_llc_id[cpu] == cpu_llc_id[i]) {
506 cpu_set(i, c[cpu].llc_shared_map);
507 cpu_set(cpu, c[i].llc_shared_map);
509 if (c[cpu].phys_proc_id == c[i].phys_proc_id) {
510 cpu_set(i, cpu_core_map[cpu]);
511 cpu_set(cpu, cpu_core_map[i]);
513 * Does this new cpu bringup a new core?
515 if (cpus_weight(cpu_sibling_map[cpu]) == 1) {
517 * for each core in package, increment
518 * the booted_cores for this new cpu
520 if (first_cpu(cpu_sibling_map[i]) == i)
521 c[cpu].booted_cores++;
523 * increment the core count for all
524 * the other cpus in this package
528 } else if (i != cpu && !c[cpu].booted_cores)
529 c[cpu].booted_cores = c[i].booted_cores;
535 * Activate a secondary processor.
537 static void __devinit start_secondary(void *unused)
540 * Don't put *anything* before secondary_cpu_init(), SMP
541 * booting is too fragile that we want to limit the
542 * things done here to the most necessary things.
544 secondary_cpu_init();
547 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
549 setup_secondary_APIC_clock();
550 if (nmi_watchdog == NMI_IO_APIC) {
551 disable_8259A_irq(0);
552 enable_NMI_through_LVT0(NULL);
557 * low-memory mappings have been cleared, flush them from
558 * the local TLBs too.
562 /* This must be done before setting cpu_online_map */
563 set_cpu_sibling_map(raw_smp_processor_id());
567 * We need to hold call_lock, so there is no inconsistency
568 * between the time smp_call_function() determines number of
569 * IPI receipients, and the time when the determination is made
570 * for which cpus receive the IPI. Holding this
571 * lock helps us to not include this cpu in a currently in progress
572 * smp_call_function().
574 lock_ipi_call_lock();
575 cpu_set(smp_processor_id(), cpu_online_map);
576 unlock_ipi_call_lock();
577 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
579 /* We can take interrupts now: we're officially "up". */
587 * Everything has been set up for the secondary
588 * CPUs - they just need to reload everything
589 * from the task structure
590 * This function must not return.
592 void __devinit initialize_secondary(void)
595 * We don't actually need to load the full TSS,
596 * basically just the stack pointer and the eip.
603 :"m" (current->thread.esp),"m" (current->thread.eip));
606 /* Static state in head.S used to set up a CPU */
611 extern struct i386_pda *start_pda;
612 extern struct Xgt_desc_struct cpu_gdt_descr;
616 /* which logical CPUs are on which nodes */
617 cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly =
618 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
619 EXPORT_SYMBOL(node_2_cpu_mask);
620 /* which node each logical CPU is on */
621 int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
622 EXPORT_SYMBOL(cpu_2_node);
624 /* set up a mapping between cpu and node. */
625 static inline void map_cpu_to_node(int cpu, int node)
627 printk("Mapping cpu %d to node %d\n", cpu, node);
628 cpu_set(cpu, node_2_cpu_mask[node]);
629 cpu_2_node[cpu] = node;
632 /* undo a mapping between cpu and node. */
633 static inline void unmap_cpu_to_node(int cpu)
637 printk("Unmapping cpu %d from all nodes\n", cpu);
638 for (node = 0; node < MAX_NUMNODES; node ++)
639 cpu_clear(cpu, node_2_cpu_mask[node]);
642 #else /* !CONFIG_NUMA */
644 #define map_cpu_to_node(cpu, node) ({})
645 #define unmap_cpu_to_node(cpu) ({})
647 #endif /* CONFIG_NUMA */
649 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
651 static void map_cpu_to_logical_apicid(void)
653 int cpu = smp_processor_id();
654 int apicid = logical_smp_processor_id();
655 int node = apicid_to_node(apicid);
657 if (!node_online(node))
658 node = first_online_node;
660 cpu_2_logical_apicid[cpu] = apicid;
661 map_cpu_to_node(cpu, node);
664 static void unmap_cpu_to_logical_apicid(int cpu)
666 cpu_2_logical_apicid[cpu] = BAD_APICID;
667 unmap_cpu_to_node(cpu);
671 static inline void __inquire_remote_apic(int apicid)
673 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
674 char *names[] = { "ID", "VERSION", "SPIV" };
677 printk("Inquiring remote APIC #%d...\n", apicid);
679 for (i = 0; i < ARRAY_SIZE(regs); i++) {
680 printk("... APIC #%d %s: ", apicid, names[i]);
685 apic_wait_icr_idle();
687 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
688 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
693 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
694 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
697 case APIC_ICR_RR_VALID:
698 status = apic_read(APIC_RRR);
699 printk("%08x\n", status);
708 #ifdef WAKE_SECONDARY_VIA_NMI
710 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
711 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
712 * won't ... remember to clear down the APIC, etc later.
715 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
717 unsigned long send_status = 0, accept_status = 0;
721 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
723 /* Boot on the stack */
724 /* Kick the second */
725 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
727 Dprintk("Waiting for send to finish...\n");
732 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
733 } while (send_status && (timeout++ < 1000));
736 * Give the other CPU some time to accept the IPI.
740 * Due to the Pentium erratum 3AP.
742 maxlvt = get_maxlvt();
744 apic_read_around(APIC_SPIV);
745 apic_write(APIC_ESR, 0);
747 accept_status = (apic_read(APIC_ESR) & 0xEF);
748 Dprintk("NMI sent.\n");
751 printk("APIC never delivered???\n");
753 printk("APIC delivery error (%lx).\n", accept_status);
755 return (send_status | accept_status);
757 #endif /* WAKE_SECONDARY_VIA_NMI */
759 #ifdef WAKE_SECONDARY_VIA_INIT
761 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
763 unsigned long send_status = 0, accept_status = 0;
764 int maxlvt, timeout, num_starts, j;
767 * Be paranoid about clearing APIC errors.
769 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
770 apic_read_around(APIC_SPIV);
771 apic_write(APIC_ESR, 0);
775 Dprintk("Asserting INIT.\n");
778 * Turn INIT on target chip
780 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
785 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
788 Dprintk("Waiting for send to finish...\n");
793 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
794 } while (send_status && (timeout++ < 1000));
798 Dprintk("Deasserting INIT.\n");
801 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
804 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
806 Dprintk("Waiting for send to finish...\n");
811 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
812 } while (send_status && (timeout++ < 1000));
814 atomic_set(&init_deasserted, 1);
817 * Should we send STARTUP IPIs ?
819 * Determine this based on the APIC version.
820 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
822 if (APIC_INTEGRATED(apic_version[phys_apicid]))
828 * Run STARTUP IPI loop.
830 Dprintk("#startup loops: %d.\n", num_starts);
832 maxlvt = get_maxlvt();
834 for (j = 1; j <= num_starts; j++) {
835 Dprintk("Sending STARTUP #%d.\n",j);
836 apic_read_around(APIC_SPIV);
837 apic_write(APIC_ESR, 0);
839 Dprintk("After apic_write.\n");
846 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
848 /* Boot on the stack */
849 /* Kick the second */
850 apic_write_around(APIC_ICR, APIC_DM_STARTUP
851 | (start_eip >> 12));
854 * Give the other CPU some time to accept the IPI.
858 Dprintk("Startup point 1.\n");
860 Dprintk("Waiting for send to finish...\n");
865 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
866 } while (send_status && (timeout++ < 1000));
869 * Give the other CPU some time to accept the IPI.
873 * Due to the Pentium erratum 3AP.
876 apic_read_around(APIC_SPIV);
877 apic_write(APIC_ESR, 0);
879 accept_status = (apic_read(APIC_ESR) & 0xEF);
880 if (send_status || accept_status)
883 Dprintk("After Startup.\n");
886 printk("APIC never delivered???\n");
888 printk("APIC delivery error (%lx).\n", accept_status);
890 return (send_status | accept_status);
892 #endif /* WAKE_SECONDARY_VIA_INIT */
894 extern cpumask_t cpu_initialized;
895 static inline int alloc_cpu_id(void)
899 cpus_complement(tmp_map, cpu_present_map);
900 cpu = first_cpu(tmp_map);
906 #ifdef CONFIG_HOTPLUG_CPU
907 static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS];
908 static inline struct task_struct * alloc_idle_task(int cpu)
910 struct task_struct *idle;
912 if ((idle = cpu_idle_tasks[cpu]) != NULL) {
913 /* initialize thread_struct. we really want to avoid destroy
916 idle->thread.esp = (unsigned long)task_pt_regs(idle);
917 init_idle(idle, cpu);
920 idle = fork_idle(cpu);
923 cpu_idle_tasks[cpu] = idle;
927 #define alloc_idle_task(cpu) fork_idle(cpu)
930 static int __devinit do_boot_cpu(int apicid, int cpu)
932 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
933 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
934 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
937 struct task_struct *idle;
938 unsigned long boot_error;
940 unsigned long start_eip;
941 unsigned short nmi_high = 0, nmi_low = 0;
944 * We can't use kernel_thread since we must avoid to
945 * reschedule the child.
947 idle = alloc_idle_task(cpu);
949 panic("failed fork for CPU %d", cpu);
951 /* Pre-allocate and initialize the CPU's GDT and PDA so it
952 doesn't have to do any memory allocation during the
953 delicate CPU-bringup phase. */
954 if (!init_gdt(cpu, idle)) {
955 printk(KERN_INFO "Couldn't allocate GDT/PDA for CPU %d\n", cpu);
959 idle->thread.eip = (unsigned long) start_secondary;
960 /* start_eip had better be page-aligned! */
961 start_eip = setup_trampoline();
964 alternatives_smp_switch(1);
966 /* So we see what's up */
967 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
968 /* Stack for startup_32 can be just as for start_secondary onwards */
969 stack_start.esp = (void *) idle->thread.esp;
971 start_pda = cpu_pda(cpu);
972 cpu_gdt_descr = per_cpu(cpu_gdt_descr, cpu);
976 x86_cpu_to_apicid[cpu] = apicid;
978 * This grunge runs the startup process for
979 * the targeted processor.
982 atomic_set(&init_deasserted, 0);
984 Dprintk("Setting warm reset code and vector.\n");
986 store_NMI_vector(&nmi_high, &nmi_low);
988 smpboot_setup_warm_reset_vector(start_eip);
991 * Starting actual IPI sequence...
993 boot_error = wakeup_secondary_cpu(apicid, start_eip);
997 * allow APs to start initializing.
999 Dprintk("Before Callout %d.\n", cpu);
1000 cpu_set(cpu, cpu_callout_map);
1001 Dprintk("After Callout %d.\n", cpu);
1004 * Wait 5s total for a response
1006 for (timeout = 0; timeout < 50000; timeout++) {
1007 if (cpu_isset(cpu, cpu_callin_map))
1008 break; /* It has booted */
1012 if (cpu_isset(cpu, cpu_callin_map)) {
1013 /* number CPUs logically, starting from 1 (BSP is 0) */
1015 printk("CPU%d: ", cpu);
1016 print_cpu_info(&cpu_data[cpu]);
1017 Dprintk("CPU has booted.\n");
1020 if (*((volatile unsigned char *)trampoline_base)
1022 /* trampoline started but...? */
1023 printk("Stuck ??\n");
1025 /* trampoline code not run */
1026 printk("Not responding.\n");
1027 inquire_remote_apic(apicid);
1032 /* Try to put things back the way they were before ... */
1033 unmap_cpu_to_logical_apicid(cpu);
1034 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
1035 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
1038 x86_cpu_to_apicid[cpu] = apicid;
1039 cpu_set(cpu, cpu_present_map);
1042 /* mark "stuck" area as not stuck */
1043 *((volatile unsigned long *)trampoline_base) = 0;
1048 #ifdef CONFIG_HOTPLUG_CPU
1049 void cpu_exit_clear(void)
1051 int cpu = raw_smp_processor_id();
1059 cpu_clear(cpu, cpu_callout_map);
1060 cpu_clear(cpu, cpu_callin_map);
1062 cpu_clear(cpu, smp_commenced_mask);
1063 unmap_cpu_to_logical_apicid(cpu);
1066 struct warm_boot_cpu_info {
1067 struct completion *complete;
1072 static void __cpuinit do_warm_boot_cpu(void *p)
1074 struct warm_boot_cpu_info *info = p;
1075 do_boot_cpu(info->apicid, info->cpu);
1076 complete(info->complete);
1079 static int __cpuinit __smp_prepare_cpu(int cpu)
1081 DECLARE_COMPLETION_ONSTACK(done);
1082 struct warm_boot_cpu_info info;
1083 struct work_struct task;
1085 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
1087 apicid = x86_cpu_to_apicid[cpu];
1088 if (apicid == BAD_APICID) {
1094 * the CPU isn't initialized at boot time, allocate gdt table here.
1095 * cpu_init will initialize it
1097 if (!cpu_gdt_descr->address) {
1098 cpu_gdt_descr->address = get_zeroed_page(GFP_KERNEL);
1099 if (!cpu_gdt_descr->address)
1100 printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu);
1105 info.complete = &done;
1106 info.apicid = apicid;
1108 INIT_WORK(&task, do_warm_boot_cpu, &info);
1110 tsc_sync_disabled = 1;
1112 /* init low mem mapping */
1113 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
1116 schedule_work(&task);
1117 wait_for_completion(&done);
1119 tsc_sync_disabled = 0;
1127 static void smp_tune_scheduling (void)
1129 unsigned long cachesize; /* kB */
1130 unsigned long bandwidth = 350; /* MB/s */
1132 * Rough estimation for SMP scheduling, this is the number of
1133 * cycles it takes for a fully memory-limited process to flush
1134 * the SMP-local cache.
1136 * (For a P5 this pretty much means we will choose another idle
1137 * CPU almost always at wakeup time (this is due to the small
1138 * L1 cache), on PIIs it's around 50-100 usecs, depending on
1144 * this basically disables processor-affinity
1145 * scheduling on SMP without a TSC.
1149 cachesize = boot_cpu_data.x86_cache_size;
1150 if (cachesize == -1) {
1151 cachesize = 16; /* Pentiums, 2x8kB cache */
1154 max_cache_size = cachesize * 1024;
1159 * Cycle through the processors sending APIC IPIs to boot each.
1162 static int boot_cpu_logical_apicid;
1163 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1165 #ifdef CONFIG_X86_NUMAQ
1166 EXPORT_SYMBOL(xquad_portio);
1169 static void __init smp_boot_cpus(unsigned int max_cpus)
1171 int apicid, cpu, bit, kicked;
1172 unsigned long bogosum = 0;
1175 * Setup boot CPU information
1177 smp_store_cpu_info(0); /* Final full version of the data */
1178 printk("CPU%d: ", 0);
1179 print_cpu_info(&cpu_data[0]);
1181 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
1182 boot_cpu_logical_apicid = logical_smp_processor_id();
1183 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
1185 current_thread_info()->cpu = 0;
1186 smp_tune_scheduling();
1188 set_cpu_sibling_map(0);
1191 * If we couldn't find an SMP configuration at boot time,
1192 * get out of here now!
1194 if (!smp_found_config && !acpi_lapic) {
1195 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1196 smpboot_clear_io_apic_irqs();
1197 phys_cpu_present_map = physid_mask_of_physid(0);
1198 if (APIC_init_uniprocessor())
1199 printk(KERN_NOTICE "Local APIC not detected."
1200 " Using dummy APIC emulation.\n");
1201 map_cpu_to_logical_apicid();
1202 cpu_set(0, cpu_sibling_map[0]);
1203 cpu_set(0, cpu_core_map[0]);
1208 * Should not be necessary because the MP table should list the boot
1209 * CPU too, but we do it for the sake of robustness anyway.
1210 * Makes no sense to do this check in clustered apic mode, so skip it
1212 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1213 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1214 boot_cpu_physical_apicid);
1215 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1219 * If we couldn't find a local APIC, then get out of here now!
1221 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
1222 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1223 boot_cpu_physical_apicid);
1224 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1225 smpboot_clear_io_apic_irqs();
1226 phys_cpu_present_map = physid_mask_of_physid(0);
1227 cpu_set(0, cpu_sibling_map[0]);
1228 cpu_set(0, cpu_core_map[0]);
1232 verify_local_APIC();
1235 * If SMP should be disabled, then really disable it!
1238 smp_found_config = 0;
1239 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1240 smpboot_clear_io_apic_irqs();
1241 phys_cpu_present_map = physid_mask_of_physid(0);
1242 cpu_set(0, cpu_sibling_map[0]);
1243 cpu_set(0, cpu_core_map[0]);
1249 map_cpu_to_logical_apicid();
1252 setup_portio_remap();
1255 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1257 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1258 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1259 * clustered apic ID.
1261 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1264 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
1265 apicid = cpu_present_to_apicid(bit);
1267 * Don't even attempt to start the boot CPU!
1269 if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
1272 if (!check_apicid_present(bit))
1274 if (max_cpus <= cpucount+1)
1277 if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
1278 printk("CPU #%d not responding - cannot use it.\n",
1285 * Cleanup possible dangling ends...
1287 smpboot_restore_warm_reset_vector();
1290 * Allow the user to impress friends.
1292 Dprintk("Before bogomips.\n");
1293 for (cpu = 0; cpu < NR_CPUS; cpu++)
1294 if (cpu_isset(cpu, cpu_callout_map))
1295 bogosum += cpu_data[cpu].loops_per_jiffy;
1297 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1299 bogosum/(500000/HZ),
1300 (bogosum/(5000/HZ))%100);
1302 Dprintk("Before bogocount - setting activated=1.\n");
1305 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1308 * Don't taint if we are running SMP kernel on a single non-MP
1311 if (tainted & TAINT_UNSAFE_SMP) {
1313 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1315 tainted &= ~TAINT_UNSAFE_SMP;
1318 Dprintk("Boot done.\n");
1321 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1324 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1325 cpus_clear(cpu_sibling_map[cpu]);
1326 cpus_clear(cpu_core_map[cpu]);
1329 cpu_set(0, cpu_sibling_map[0]);
1330 cpu_set(0, cpu_core_map[0]);
1332 smpboot_setup_io_apic();
1334 setup_boot_APIC_clock();
1337 * Synchronize the TSC with the AP
1339 if (cpu_has_tsc && cpucount && cpu_khz)
1340 synchronize_tsc_bp();
1343 /* These are wrappers to interface to the new boot process. Someone
1344 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1345 void __init smp_prepare_cpus(unsigned int max_cpus)
1347 smp_commenced_mask = cpumask_of_cpu(0);
1348 cpu_callin_map = cpumask_of_cpu(0);
1350 smp_boot_cpus(max_cpus);
1353 void __devinit smp_prepare_boot_cpu(void)
1355 cpu_set(smp_processor_id(), cpu_online_map);
1356 cpu_set(smp_processor_id(), cpu_callout_map);
1357 cpu_set(smp_processor_id(), cpu_present_map);
1358 cpu_set(smp_processor_id(), cpu_possible_map);
1359 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
1362 #ifdef CONFIG_HOTPLUG_CPU
1364 remove_siblinginfo(int cpu)
1367 struct cpuinfo_x86 *c = cpu_data;
1369 for_each_cpu_mask(sibling, cpu_core_map[cpu]) {
1370 cpu_clear(cpu, cpu_core_map[sibling]);
1372 * last thread sibling in this cpu core going down
1374 if (cpus_weight(cpu_sibling_map[cpu]) == 1)
1375 c[sibling].booted_cores--;
1378 for_each_cpu_mask(sibling, cpu_sibling_map[cpu])
1379 cpu_clear(cpu, cpu_sibling_map[sibling]);
1380 cpus_clear(cpu_sibling_map[cpu]);
1381 cpus_clear(cpu_core_map[cpu]);
1382 c[cpu].phys_proc_id = 0;
1383 c[cpu].cpu_core_id = 0;
1384 cpu_clear(cpu, cpu_sibling_setup_map);
1387 int __cpu_disable(void)
1389 cpumask_t map = cpu_online_map;
1390 int cpu = smp_processor_id();
1393 * Perhaps use cpufreq to drop frequency, but that could go
1394 * into generic code.
1396 * We won't take down the boot processor on i386 due to some
1397 * interrupts only being able to be serviced by the BSP.
1398 * Especially so if we're not using an IOAPIC -zwane
1402 if (nmi_watchdog == NMI_LOCAL_APIC)
1403 stop_apic_nmi_watchdog(NULL);
1405 /* Allow any queued timer interrupts to get serviced */
1408 local_irq_disable();
1410 remove_siblinginfo(cpu);
1412 cpu_clear(cpu, map);
1414 /* It's now safe to remove this processor from the online map */
1415 cpu_clear(cpu, cpu_online_map);
1419 void __cpu_die(unsigned int cpu)
1421 /* We don't do anything here: idle task is faking death itself. */
1424 for (i = 0; i < 10; i++) {
1425 /* They ack this in play_dead by setting CPU_DEAD */
1426 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1427 printk ("CPU %d is now offline\n", cpu);
1428 if (1 == num_online_cpus())
1429 alternatives_smp_switch(0);
1434 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1436 #else /* ... !CONFIG_HOTPLUG_CPU */
1437 int __cpu_disable(void)
1442 void __cpu_die(unsigned int cpu)
1444 /* We said "no" in __cpu_disable */
1447 #endif /* CONFIG_HOTPLUG_CPU */
1449 int __devinit __cpu_up(unsigned int cpu)
1451 #ifdef CONFIG_HOTPLUG_CPU
1455 * We do warm boot only on cpus that had booted earlier
1456 * Otherwise cold boot is all handled from smp_boot_cpus().
1457 * cpu_callin_map is set during AP kickstart process. Its reset
1458 * when a cpu is taken offline from cpu_exit_clear().
1460 if (!cpu_isset(cpu, cpu_callin_map))
1461 ret = __smp_prepare_cpu(cpu);
1467 /* In case one didn't come up */
1468 if (!cpu_isset(cpu, cpu_callin_map)) {
1469 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1475 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1476 /* Unleash the CPU! */
1477 cpu_set(cpu, smp_commenced_mask);
1478 while (!cpu_isset(cpu, cpu_online_map))
1483 void __init smp_cpus_done(unsigned int max_cpus)
1485 #ifdef CONFIG_X86_IO_APIC
1486 setup_ioapic_dest();
1489 #ifndef CONFIG_HOTPLUG_CPU
1491 * Disable executability of the SMP trampoline:
1493 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1497 void __init smp_intr_init(void)
1500 * IRQ0 must be given a fixed assignment and initialized,
1501 * because it's used before the IO-APIC is set up.
1503 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
1506 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1507 * IPI, driven by wakeup.
1509 set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
1511 /* IPI for invalidation */
1512 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1514 /* IPI for generic function call */
1515 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
1519 * If the BIOS enumerates physical processors before logical,
1520 * maxcpus=N at enumeration-time can be used to disable HT.
1522 static int __init parse_maxcpus(char *arg)
1524 extern unsigned int maxcpus;
1526 maxcpus = simple_strtoul(arg, NULL, 0);
1529 early_param("maxcpus", parse_maxcpus);