2 * Blackfin bf609 power management
4 * Copyright 2011 Analog Devices Inc.
6 * Licensed under the GPL-2
9 #include <linux/suspend.h>
11 #include <linux/interrupt.h>
12 #include <linux/gpio.h>
13 #include <linux/irq.h>
15 #include <linux/delay.h>
20 #include <asm/blackfin.h>
22 /***********************************************************/
24 /* Wakeup Actions for DPM_RESTORE */
26 /***********************************************************/
27 #define BITP_ROM_WUA_CHKHDR 24
28 #define BITP_ROM_WUA_DDRLOCK 7
29 #define BITP_ROM_WUA_DDRDLLEN 6
30 #define BITP_ROM_WUA_DDR 5
31 #define BITP_ROM_WUA_CGU 4
32 #define BITP_ROM_WUA_MEMBOOT 2
33 #define BITP_ROM_WUA_EN 1
35 #define BITM_ROM_WUA_CHKHDR (0xFF000000)
36 #define ENUM_ROM_WUA_CHKHDR_AD 0xAD000000
38 #define BITM_ROM_WUA_DDRLOCK (0x00000080)
39 #define BITM_ROM_WUA_DDRDLLEN (0x00000040)
40 #define BITM_ROM_WUA_DDR (0x00000020)
41 #define BITM_ROM_WUA_CGU (0x00000010)
42 #define BITM_ROM_WUA_MEMBOOT (0x00000002)
43 #define BITM_ROM_WUA_EN (0x00000001)
45 /***********************************************************/
49 /***********************************************************/
50 #define BITP_ROM_SYSCTRL_CGU_LOCKINGEN 28 /* unlocks CGU_CTL register */
51 #define BITP_ROM_SYSCTRL_WUA_OVERRIDE 24
52 #define BITP_ROM_SYSCTRL_WUA_DDRDLLEN 20 /* Saves the DDR DLL and PADS registers to the DPM registers */
53 #define BITP_ROM_SYSCTRL_WUA_DDR 19 /* Saves the DDR registers to the DPM registers */
54 #define BITP_ROM_SYSCTRL_WUA_CGU 18 /* Saves the CGU registers into DPM registers */
55 #define BITP_ROM_SYSCTRL_WUA_DPMWRITE 17 /* Saves the Syscontrol structure structure contents into DPM registers */
56 #define BITP_ROM_SYSCTRL_WUA_EN 16 /* reads current PLL and DDR configuration into structure */
57 #define BITP_ROM_SYSCTRL_DDR_WRITE 13 /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */
58 #define BITP_ROM_SYSCTRL_DDR_READ 12 /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */
59 #define BITP_ROM_SYSCTRL_CGU_AUTODIS 11 /* Disables auto handling of UPDT and ALGN fields */
60 #define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL 7 /* access CGU_CLKOUTSEL register */
61 #define BITP_ROM_SYSCTRL_CGU_DIV 6 /* access CGU_DIV register */
62 #define BITP_ROM_SYSCTRL_CGU_STAT 5 /* access CGU_STAT register */
63 #define BITP_ROM_SYSCTRL_CGU_CTL 4 /* access CGU_CTL register */
64 #define BITP_ROM_SYSCTRL_CGU_RTNSTAT 2 /* Update structure STAT field upon error */
65 #define BITP_ROM_SYSCTRL_WRITE 1 /* write registers */
66 #define BITP_ROM_SYSCTRL_READ 0 /* read registers */
68 #define BITM_ROM_SYSCTRL_CGU_READ (0x00000001) /* Read CGU registers */
69 #define BITM_ROM_SYSCTRL_CGU_WRITE (0x00000002) /* Write registers */
70 #define BITM_ROM_SYSCTRL_CGU_RTNSTAT (0x00000004) /* Update structure STAT field upon error or after a write operation */
71 #define BITM_ROM_SYSCTRL_CGU_CTL (0x00000010) /* Access CGU_CTL register */
72 #define BITM_ROM_SYSCTRL_CGU_STAT (0x00000020) /* Access CGU_STAT register */
73 #define BITM_ROM_SYSCTRL_CGU_DIV (0x00000040) /* Access CGU_DIV register */
74 #define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL (0x00000080) /* Access CGU_CLKOUTSEL register */
75 #define BITM_ROM_SYSCTRL_CGU_AUTODIS (0x00000800) /* Disables auto handling of UPDT and ALGN fields */
76 #define BITM_ROM_SYSCTRL_DDR_READ (0x00001000) /* Reads the contents of the DDR registers and stores them into the structure */
77 #define BITM_ROM_SYSCTRL_DDR_WRITE (0x00002000) /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */
78 #define BITM_ROM_SYSCTRL_WUA_EN (0x00010000) /* Wakeup entry or exit opertation enable */
79 #define BITM_ROM_SYSCTRL_WUA_DPMWRITE (0x00020000) /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */
80 #define BITM_ROM_SYSCTRL_WUA_CGU (0x00040000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
81 #define BITM_ROM_SYSCTRL_WUA_DDR (0x00080000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
82 #define BITM_ROM_SYSCTRL_WUA_DDRDLLEN (0x00100000) /* Enables saving/restoring of the DDR DLLCTL register */
83 #define BITM_ROM_SYSCTRL_WUA_OVERRIDE (0x01000000)
84 #define BITM_ROM_SYSCTRL_CGU_LOCKINGEN (0x10000000) /* Unlocks the CGU_CTL register */
87 /* Structures for the syscontrol() function */
88 struct STRUCT_ROM_SYSCTRL {
92 uint32_t ulCGU_CLKOUTSEL;
94 uint32_t ulWUA_BootAddr;
104 uint32_t ulDDR_PADCTL;
105 uint32_t ulDDR_DLLCTL;
109 struct bfin_pm_data {
111 uint32_t resume_addr;
115 struct bfin_pm_data bf609_pm_data;
117 struct STRUCT_ROM_SYSCTRL configvalues;
118 uint32_t dactionflags;
120 #define FUNC_ROM_SYSCONTROL 0xC8000080
121 __attribute__((l1_data))
122 static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL;
124 __attribute__((l1_text))
125 void bfin_cpu_suspend(void)
127 __asm__ __volatile__( \
134 __attribute__((l1_text))
135 void bfin_deepsleep(unsigned long mask)
139 bfin_write32(DPM0_WAKE_EN, 0x10);
140 bfin_write32(DPM0_WAKE_POL, 0x10);
141 dpm0_ctl = 0x00000008;
142 bfin_write32(DPM0_CTL, dpm0_ctl);
144 __asm__ __volatile__( \
149 #ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
150 __asm__ __volatile__(
163 __attribute__((l1_text))
164 void bf609_ddr_sr(void)
168 reg = bfin_read_DMC0_CTL();
170 bfin_write_DMC0_CTL(reg);
172 while (!(bfin_read_DMC0_STAT() & 0x8))
176 __attribute__((l1_text))
177 void bf609_ddr_sr_exit(void)
180 while (!(bfin_read_DMC0_STAT() & 0x1))
183 reg = bfin_read_DMC0_CTL();
185 bfin_write_DMC0_CTL(reg);
187 while ((bfin_read_DMC0_STAT() & 0x8))
191 __attribute__((l1_text))
192 void bfin_hibernate_syscontrol(void)
194 configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN
195 | BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN);
197 dactionflags = (BITM_ROM_SYSCTRL_WUA_EN
198 | BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU
199 | BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN);
201 bfrom_SysControl(dactionflags, &configvalues, NULL);
203 bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
207 # define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
209 # define SIC_SYSIRQ(irq) ((irq) - IVG15)
211 void bfin_hibernate(unsigned long mask)
213 bfin_write32(DPM0_WAKE_EN, 0x10);
214 bfin_write32(DPM0_WAKE_POL, 0x10);
215 bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
216 bfin_write32(DPM0_HIB_DIS, 0xFFFF);
218 printk(KERN_DEBUG "hibernate: restore %x pgcnt %x\n", bfin_read32(DPM0_RESTORE0), bfin_read32(DPM0_PGCNTR));
223 void bf609_cpu_pm_enter(suspend_state_t state)
226 unsigned long wakeup = 0;
227 unsigned long wakeup_pol = 0;
229 #ifdef CONFIG_PM_BFIN_WAKE_PA15
231 # if CONFIG_PM_BFIN_WAKE_PA15_POL
232 wakeup_pol |= PA15WE;
236 #ifdef CONFIG_PM_BFIN_WAKE_PB15
238 # if CONFIG_PM_BFIN_WAKE_PA15_POL
239 wakeup_pol |= PB15WE;
243 #ifdef CONFIG_PM_BFIN_WAKE_PC15
245 # if CONFIG_PM_BFIN_WAKE_PC15_POL
246 wakeup_pol |= PC15WE;
250 #ifdef CONFIG_PM_BFIN_WAKE_PD06
252 # if CONFIG_PM_BFIN_WAKE_PD06_POL
253 wakeup_pol |= PD06WE;
257 #ifdef CONFIG_PM_BFIN_WAKE_PE12
259 # if CONFIG_PM_BFIN_WAKE_PE12_POL
260 wakeup_pol |= PE12WE;
264 #ifdef CONFIG_PM_BFIN_WAKE_PG04
266 # if CONFIG_PM_BFIN_WAKE_PG04_POL
267 wakeup_pol |= PG04WE;
271 #ifdef CONFIG_PM_BFIN_WAKE_PG13
273 # if CONFIG_PM_BFIN_WAKE_PG13_POL
274 wakeup_pol |= PG13WE;
278 #ifdef CONFIG_PM_BFIN_WAKE_USB
280 # if CONFIG_PM_BFIN_WAKE_USB_POL
285 error = irq_set_irq_wake(255, 1);
287 printk(KERN_DEBUG "Unable to get irq wake\n");
288 error = irq_set_irq_wake(231, 1);
290 printk(KERN_DEBUG "Unable to get irq wake\n");
292 if (state == PM_SUSPEND_STANDBY)
293 bfin_deepsleep(wakeup);
295 bfin_hibernate(wakeup);
299 int bf609_cpu_pm_prepare(void)
304 void bf609_cpu_pm_finish(void)
309 static struct bfin_cpu_pm_fns bf609_cpu_pm = {
310 .enter = bf609_cpu_pm_enter,
311 .prepare = bf609_cpu_pm_prepare,
312 .finish = bf609_cpu_pm_finish,
315 static irqreturn_t test_isr(int irq, void *dev_id)
317 printk(KERN_DEBUG "gpio irq %d\n", irq);
321 static irqreturn_t dpm0_isr(int irq, void *dev_id)
325 wake_stat = bfin_read32(DPM0_WAKE_STAT);
326 printk(KERN_DEBUG "enter %s wake stat %08x\n", __func__, wake_stat);
328 bfin_write32(DPM0_WAKE_STAT, wake_stat);
332 static int __init bf609_init_pm(void)
337 #if CONFIG_PM_BFIN_WAKE_PE12
338 irq = gpio_to_irq(GPIO_PE12);
341 printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n",
345 error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "gpiope12", NULL);
347 printk(KERN_DEBUG "Unable to get irq\n");
350 error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL);
352 printk(KERN_DEBUG "Unable to get irq\n");
354 error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL);
356 printk(KERN_DEBUG "Unable to get irq\n");
358 bfin_cpu_pm = &bf609_cpu_pm;
362 late_initcall(bf609_init_pm);