Pileus Git - ~andy/linux/blob - arch/blackfin/kernel/process.c

   1 /*
   2  * Blackfin architecture-dependent process handling
   3  *
   4  * Copyright 2004-2009 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/unistd.h>
  11 #include <linux/user.h>
  12 #include <linux/uaccess.h>
  13 #include <linux/slab.h>
  14 #include <linux/sched.h>
  15 #include <linux/tick.h>
  16 #include <linux/fs.h>
  17 #include <linux/err.h>
  18
  19 #include <asm/blackfin.h>
  20 #include <asm/fixed_code.h>
  21 #include <asm/mem_map.h>
  22 #include <asm/irq.h>
  23
  24 asmlinkage void ret_from_fork(void);
  25
  26 /* Points to the SDRAM backup memory for the stack that is currently in
  27  * L1 scratchpad memory.
  28  */
  29 void *current_l1_stack_save;
  30
  31 /* The number of tasks currently using a L1 stack area.  The SRAM is
  32  * allocated/deallocated whenever this changes from/to zero.
  33  */
  34 int nr_l1stack_tasks;
  35
  36 /* Start and length of the area in L1 scratchpad memory which we've allocated
  37  * for process stacks.
  38  */
  39 void *l1_stack_base;
  40 unsigned long l1_stack_len;
  41
  42 /*
  43  * Powermanagement idle function, if any..
  44  */
  45 void (*pm_idle)(void) = NULL;
  46 EXPORT_SYMBOL(pm_idle);
  47
  48 void (*pm_power_off)(void) = NULL;
  49 EXPORT_SYMBOL(pm_power_off);
  50
  51 /*
  52  * The idle loop on BFIN
  53  */
  54 #ifdef CONFIG_IDLE_L1
  55 static void default_idle(void)__attribute__((l1_text));
  56 void cpu_idle(void)__attribute__((l1_text));
  57 #endif
  58
  59 /*
  60  * This is our default idle handler.  We need to disable
  61  * interrupts here to ensure we don't miss a wakeup call.
  62  */
  63 static void default_idle(void)
  64 {
  65 #ifdef CONFIG_IPIPE
  66         ipipe_suspend_domain();
  67 #endif
  68         hard_local_irq_disable();
  69         if (!need_resched())
  70                 idle_with_irq_disabled();
  71
  72         hard_local_irq_enable();
  73 }
  74
  75 /*
  76  * The idle thread.  We try to conserve power, while trying to keep
  77  * overall latency low.  The architecture specific idle is passed
  78  * a value to indicate the level of "idleness" of the system.
  79  */
  80 void cpu_idle(void)
  81 {
  82         /* endless idle loop with no priority at all */
  83         while (1) {
  84                 void (*idle)(void) = pm_idle;
  85
  86 #ifdef CONFIG_HOTPLUG_CPU
  87                 if (cpu_is_offline(smp_processor_id()))
  88                         cpu_die();
  89 #endif
  90                 if (!idle)
  91                         idle = default_idle;
  92                 tick_nohz_idle_enter();
  93                 rcu_idle_enter();
  94                 while (!need_resched())
  95                         idle();
  96                 rcu_idle_exit();
  97                 tick_nohz_idle_exit();
  98                 preempt_enable_no_resched();
  99                 schedule();
 100                 preempt_disable();
 101         }
 102 }
 103
 104 /*
 105  * Do necessary setup to start up a newly executed thread.
 106  *
 107  * pass the data segment into user programs if it exists,
 108  * it can't hurt anything as far as I can tell
 109  */
 110 void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
 111 {
 112         regs->pc = new_ip;
 113         if (current->mm)
 114                 regs->p5 = current->mm->start_data;
 115 #ifndef CONFIG_SMP
 116         task_thread_info(current)->l1_task_info.stack_start =
 117                 (void *)current->mm->context.stack_start;
 118         task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
 119         memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
 120                sizeof(*L1_SCRATCH_TASK_INFO));
 121 #endif
 122         wrusp(new_sp);
 123 }
 124 EXPORT_SYMBOL_GPL(start_thread);
 125
 126 void flush_thread(void)
 127 {
 128 }
 129
 130 asmlinkage int bfin_clone(unsigned long clone_flags, unsigned long newsp)
 131 {
 132 #ifdef __ARCH_SYNC_CORE_DCACHE
 133         if (current->nr_cpus_allowed == num_possible_cpus())
 134                 set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
 135 #endif
 136         if (newsp)
 137                 newsp -= 12;
 138         return do_fork(clone_flags, newsp, 0, NULL, NULL);
 139 }
 140
 141 int
 142 copy_thread(unsigned long clone_flags,
 143             unsigned long usp, unsigned long topstk,
 144             struct task_struct *p)
 145 {
 146         struct pt_regs *childregs;
 147         unsigned long *v;
 148
 149         childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
 150         v = ((unsigned long *)childregs) - 2;
 151         if (unlikely(p->flags & PF_KTHREAD)) {
 152                 memset(childregs, 0, sizeof(struct pt_regs));
 153                 v[0] = usp;
 154                 v[1] = topstk;
 155                 childregs->orig_p0 = -1;
 156                 childregs->ipend = 0x8000;
 157                 __asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
 158                 p->thread.usp = 0;
 159         } else {
 160                 *childregs = *current_pt_regs();
 161                 childregs->r0 = 0;
 162                 p->thread.usp = usp ? : rdusp();
 163                 v[0] = v[1] = 0;
 164         }
 165
 166         p->thread.ksp = (unsigned long)v;
 167         p->thread.pc = (unsigned long)ret_from_fork;
 168
 169         return 0;
 170 }
 171
 172 unsigned long get_wchan(struct task_struct *p)
 173 {
 174         unsigned long fp, pc;
 175         unsigned long stack_page;
 176         int count = 0;
 177         if (!p || p == current || p->state == TASK_RUNNING)
 178                 return 0;
 179
 180         stack_page = (unsigned long)p;
 181         fp = p->thread.usp;
 182         do {
 183                 if (fp < stack_page + sizeof(struct thread_info) ||
 184                     fp >= 8184 + stack_page)
 185                         return 0;
 186                 pc = ((unsigned long *)fp)[1];
 187                 if (!in_sched_functions(pc))
 188                         return pc;
 189                 fp = *(unsigned long *)fp;
 190         }
 191         while (count++ < 16);
 192         return 0;
 193 }
 194
 195 void finish_atomic_sections (struct pt_regs *regs)
 196 {
 197         int __user *up0 = (int __user *)regs->p0;
 198
 199         switch (regs->pc) {
 200         default:
 201                 /* not in middle of an atomic step, so resume like normal */
 202                 return;
 203
 204         case ATOMIC_XCHG32 + 2:
 205                 put_user(regs->r1, up0);
 206                 break;
 207
 208         case ATOMIC_CAS32 + 2:
 209         case ATOMIC_CAS32 + 4:
 210                 if (regs->r0 == regs->r1)
 211         case ATOMIC_CAS32 + 6:
 212                         put_user(regs->r2, up0);
 213                 break;
 214
 215         case ATOMIC_ADD32 + 2:
 216                 regs->r0 = regs->r1 + regs->r0;
 217                 /* fall through */
 218         case ATOMIC_ADD32 + 4:
 219                 put_user(regs->r0, up0);
 220                 break;
 221
 222         case ATOMIC_SUB32 + 2:
 223                 regs->r0 = regs->r1 - regs->r0;
 224                 /* fall through */
 225         case ATOMIC_SUB32 + 4:
 226                 put_user(regs->r0, up0);
 227                 break;
 228
 229         case ATOMIC_IOR32 + 2:
 230                 regs->r0 = regs->r1 | regs->r0;
 231                 /* fall through */
 232         case ATOMIC_IOR32 + 4:
 233                 put_user(regs->r0, up0);
 234                 break;
 235
 236         case ATOMIC_AND32 + 2:
 237                 regs->r0 = regs->r1 & regs->r0;
 238                 /* fall through */
 239         case ATOMIC_AND32 + 4:
 240                 put_user(regs->r0, up0);
 241                 break;
 242
 243         case ATOMIC_XOR32 + 2:
 244                 regs->r0 = regs->r1 ^ regs->r0;
 245                 /* fall through */
 246         case ATOMIC_XOR32 + 4:
 247                 put_user(regs->r0, up0);
 248                 break;
 249         }
 250
 251         /*
 252          * We've finished the atomic section, and the only thing left for
 253          * userspace is to do a RTS, so we might as well handle that too
 254          * since we need to update the PC anyways.
 255          */
 256         regs->pc = regs->rets;
 257 }
 258
 259 static inline
 260 int in_mem(unsigned long addr, unsigned long size,
 261            unsigned long start, unsigned long end)
 262 {
 263         return addr >= start && addr + size <= end;
 264 }
 265 static inline
 266 int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
 267                      unsigned long const_addr, unsigned long const_size)
 268 {
 269         return const_size &&
 270                in_mem(addr, size, const_addr + off, const_addr + const_size);
 271 }
 272 static inline
 273 int in_mem_const(unsigned long addr, unsigned long size,
 274                  unsigned long const_addr, unsigned long const_size)
 275 {
 276         return in_mem_const_off(addr, size, 0, const_addr, const_size);
 277 }
 278 #ifdef CONFIG_BF60x
 279 #define ASYNC_ENABLED(bnum, bctlnum)    1
 280 #else
 281 #define ASYNC_ENABLED(bnum, bctlnum) \
 282 ({ \
 283         (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
 284         bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
 285         1; \
 286 })
 287 #endif
 288 /*
 289  * We can't read EBIU banks that aren't enabled or we end up hanging
 290  * on the access to the async space.  Make sure we validate accesses
 291  * that cross async banks too.
 292  *      0 - found, but unusable
 293  *      1 - found & usable
 294  *      2 - not found
 295  */
 296 static
 297 int in_async(unsigned long addr, unsigned long size)
 298 {
 299         if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
 300                 if (!ASYNC_ENABLED(0, 0))
 301                         return 0;
 302                 if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
 303                         return 1;
 304                 size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
 305                 addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
 306         }
 307         if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
 308                 if (!ASYNC_ENABLED(1, 0))
 309                         return 0;
 310                 if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
 311                         return 1;
 312                 size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
 313                 addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
 314         }
 315         if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
 316                 if (!ASYNC_ENABLED(2, 1))
 317                         return 0;
 318                 if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
 319                         return 1;
 320                 size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
 321                 addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
 322         }
 323         if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
 324                 if (ASYNC_ENABLED(3, 1))
 325                         return 0;
 326                 if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
 327                         return 1;
 328                 return 0;
 329         }
 330
 331         /* not within async bounds */
 332         return 2;
 333 }
 334
 335 int bfin_mem_access_type(unsigned long addr, unsigned long size)
 336 {
 337         int cpu = raw_smp_processor_id();
 338
 339         /* Check that things do not wrap around */
 340         if (addr > ULONG_MAX - size)
 341                 return -EFAULT;
 342
 343         if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
 344                 return BFIN_MEM_ACCESS_CORE;
 345
 346         if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
 347                 return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
 348         if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
 349                 return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
 350         if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
 351                 return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
 352         if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
 353                 return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
 354 #ifdef COREB_L1_CODE_START
 355         if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
 356                 return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
 357         if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
 358                 return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
 359         if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
 360                 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
 361         if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
 362                 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
 363 #endif
 364         if (in_mem_const(addr, size, L2_START, L2_LENGTH))
 365                 return BFIN_MEM_ACCESS_CORE;
 366
 367         if (addr >= SYSMMR_BASE)
 368                 return BFIN_MEM_ACCESS_CORE_ONLY;
 369
 370         switch (in_async(addr, size)) {
 371         case 0: return -EFAULT;
 372         case 1: return BFIN_MEM_ACCESS_CORE;
 373         case 2: /* fall through */;
 374         }
 375
 376         if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
 377                 return BFIN_MEM_ACCESS_CORE;
 378         if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
 379                 return BFIN_MEM_ACCESS_DMA;
 380
 381         return -EFAULT;
 382 }
 383
 384 #if defined(CONFIG_ACCESS_CHECK)
 385 #ifdef CONFIG_ACCESS_OK_L1
 386 __attribute__((l1_text))
 387 #endif
 388 /* Return 1 if access to memory range is OK, 0 otherwise */
 389 int _access_ok(unsigned long addr, unsigned long size)
 390 {
 391         int aret;
 392
 393         if (size == 0)
 394                 return 1;
 395         /* Check that things do not wrap around */
 396         if (addr > ULONG_MAX - size)
 397                 return 0;
 398         if (segment_eq(get_fs(), KERNEL_DS))
 399                 return 1;
 400 #ifdef CONFIG_MTD_UCLINUX
 401         if (1)
 402 #else
 403         if (0)
 404 #endif
 405         {
 406                 if (in_mem(addr, size, memory_start, memory_end))
 407                         return 1;
 408                 if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
 409                         return 1;
 410 # ifndef CONFIG_ROMFS_ON_MTD
 411                 if (0)
 412 # endif
 413                         /* For XIP, allow user space to use pointers within the ROMFS.  */
 414                         if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
 415                                 return 1;
 416         } else {
 417                 if (in_mem(addr, size, memory_start, physical_mem_end))
 418                         return 1;
 419         }
 420
 421         if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
 422                 return 1;
 423
 424         if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
 425                 return 1;
 426         if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
 427                 return 1;
 428         if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
 429                 return 1;
 430         if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
 431                 return 1;
 432 #ifdef COREB_L1_CODE_START
 433         if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
 434                 return 1;
 435         if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
 436                 return 1;
 437         if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
 438                 return 1;
 439         if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
 440                 return 1;
 441 #endif
 442
 443 #ifndef CONFIG_EXCEPTION_L1_SCRATCH
 444         if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
 445                 return 1;
 446 #endif
 447
 448         aret = in_async(addr, size);
 449         if (aret < 2)
 450                 return aret;
 451
 452         if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
 453                 return 1;
 454
 455         if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
 456                 return 1;
 457         if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
 458                 return 1;
 459
 460         return 0;
 461 }
 462 EXPORT_SYMBOL(_access_ok);
 463 #endif /* CONFIG_ACCESS_CHECK */