Pileus Git - ~andy/linux/blob - arch/avr32/mach-at32ap/at32ap700x.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/dw_dmac.h>
  11 #include <linux/fb.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/slab.h>
  16 #include <linux/gpio.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/usb/atmel_usba_udc.h>
  19
  20 #include <mach/atmel-mci.h>
  21 #include <linux/atmel-mci.h>
  22
  23 #include <asm/io.h>
  24 #include <asm/irq.h>
  25
  26 #include <mach/at32ap700x.h>
  27 #include <mach/board.h>
  28 #include <mach/hmatrix.h>
  29 #include <mach/portmux.h>
  30 #include <mach/sram.h>
  31
  32 #include <sound/atmel-abdac.h>
  33 #include <sound/atmel-ac97c.h>
  34
  35 #include <video/atmel_lcdc.h>
  36
  37 #include "clock.h"
  38 #include "pio.h"
  39 #include "pm.h"
  40
  41
  42 #define PBMEM(base)                                     \
  43         {                                               \
  44                 .start          = base,                 \
  45                 .end            = base + 0x3ff,         \
  46                 .flags          = IORESOURCE_MEM,       \
  47         }
  48 #define IRQ(num)                                        \
  49         {                                               \
  50                 .start          = num,                  \
  51                 .end            = num,                  \
  52                 .flags          = IORESOURCE_IRQ,       \
  53         }
  54 #define NAMED_IRQ(num, _name)                           \
  55         {                                               \
  56                 .start          = num,                  \
  57                 .end            = num,                  \
  58                 .name           = _name,                \
  59                 .flags          = IORESOURCE_IRQ,       \
  60         }
  61
  62 /* REVISIT these assume *every* device supports DMA, but several
  63  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  64  */
  65 #define DEFINE_DEV(_name, _id)                                  \
  66 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32);            \
  67 static struct platform_device _name##_id##_device = {           \
  68         .name           = #_name,                               \
  69         .id             = _id,                                  \
  70         .dev            = {                                     \
  71                 .dma_mask = &_name##_id##_dma_mask,             \
  72                 .coherent_dma_mask = DMA_BIT_MASK(32),          \
  73         },                                                      \
  74         .resource       = _name##_id##_resource,                \
  75         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  76 }
  77 #define DEFINE_DEV_DATA(_name, _id)                             \
  78 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32);            \
  79 static struct platform_device _name##_id##_device = {           \
  80         .name           = #_name,                               \
  81         .id             = _id,                                  \
  82         .dev            = {                                     \
  83                 .dma_mask = &_name##_id##_dma_mask,             \
  84                 .platform_data  = &_name##_id##_data,           \
  85                 .coherent_dma_mask = DMA_BIT_MASK(32),          \
  86         },                                                      \
  87         .resource       = _name##_id##_resource,                \
  88         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  89 }
  90
  91 #define select_peripheral(port, pin_mask, periph, flags)        \
  92         at32_select_periph(GPIO_##port##_BASE, pin_mask,        \
  93                            GPIO_##periph, flags)
  94
  95 #define DEV_CLK(_name, devname, bus, _index)                    \
  96 static struct clk devname##_##_name = {                         \
  97         .name           = #_name,                               \
  98         .dev            = &devname##_device.dev,                \
  99         .parent         = &bus##_clk,                           \
 100         .mode           = bus##_clk_mode,                       \
 101         .get_rate       = bus##_clk_get_rate,                   \
 102         .index          = _index,                               \
 103 }
 104
 105 static DEFINE_SPINLOCK(pm_lock);
 106
 107 static struct clk osc0;
 108 static struct clk osc1;
 109
 110 static unsigned long osc_get_rate(struct clk *clk)
 111 {
 112         return at32_board_osc_rates[clk->index];
 113 }
 114
 115 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 116 {
 117         unsigned long div, mul, rate;
 118
 119         div = PM_BFEXT(PLLDIV, control) + 1;
 120         mul = PM_BFEXT(PLLMUL, control) + 1;
 121
 122         rate = clk->parent->get_rate(clk->parent);
 123         rate = (rate + div / 2) / div;
 124         rate *= mul;
 125
 126         return rate;
 127 }
 128
 129 static long pll_set_rate(struct clk *clk, unsigned long rate,
 130                          u32 *pll_ctrl)
 131 {
 132         unsigned long mul;
 133         unsigned long mul_best_fit = 0;
 134         unsigned long div;
 135         unsigned long div_min;
 136         unsigned long div_max;
 137         unsigned long div_best_fit = 0;
 138         unsigned long base;
 139         unsigned long pll_in;
 140         unsigned long actual = 0;
 141         unsigned long rate_error;
 142         unsigned long rate_error_prev = ~0UL;
 143         u32 ctrl;
 144
 145         /* Rate must be between 80 MHz and 200 Mhz. */
 146         if (rate < 80000000UL || rate > 200000000UL)
 147                 return -EINVAL;
 148
 149         ctrl = PM_BF(PLLOPT, 4);
 150         base = clk->parent->get_rate(clk->parent);
 151
 152         /* PLL input frequency must be between 6 MHz and 32 MHz. */
 153         div_min = DIV_ROUND_UP(base, 32000000UL);
 154         div_max = base / 6000000UL;
 155
 156         if (div_max < div_min)
 157                 return -EINVAL;
 158
 159         for (div = div_min; div <= div_max; div++) {
 160                 pll_in = (base + div / 2) / div;
 161                 mul = (rate + pll_in / 2) / pll_in;
 162
 163                 if (mul == 0)
 164                         continue;
 165
 166                 actual = pll_in * mul;
 167                 rate_error = abs(actual - rate);
 168
 169                 if (rate_error < rate_error_prev) {
 170                         mul_best_fit = mul;
 171                         div_best_fit = div;
 172                         rate_error_prev = rate_error;
 173                 }
 174
 175                 if (rate_error == 0)
 176                         break;
 177         }
 178
 179         if (div_best_fit == 0)
 180                 return -EINVAL;
 181
 182         ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
 183         ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
 184         ctrl |= PM_BF(PLLCOUNT, 16);
 185
 186         if (clk->parent == &osc1)
 187                 ctrl |= PM_BIT(PLLOSC);
 188
 189         *pll_ctrl = ctrl;
 190
 191         return actual;
 192 }
 193
 194 static unsigned long pll0_get_rate(struct clk *clk)
 195 {
 196         u32 control;
 197
 198         control = pm_readl(PLL0);
 199
 200         return pll_get_rate(clk, control);
 201 }
 202
 203 static void pll1_mode(struct clk *clk, int enabled)
 204 {
 205         unsigned long timeout;
 206         u32 status;
 207         u32 ctrl;
 208
 209         ctrl = pm_readl(PLL1);
 210
 211         if (enabled) {
 212                 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
 213                         pr_debug("clk %s: failed to enable, rate not set\n",
 214                                         clk->name);
 215                         return;
 216                 }
 217
 218                 ctrl |= PM_BIT(PLLEN);
 219                 pm_writel(PLL1, ctrl);
 220
 221                 /* Wait for PLL lock. */
 222                 for (timeout = 10000; timeout; timeout--) {
 223                         status = pm_readl(ISR);
 224                         if (status & PM_BIT(LOCK1))
 225                                 break;
 226                         udelay(10);
 227                 }
 228
 229                 if (!(status & PM_BIT(LOCK1)))
 230                         printk(KERN_ERR "clk %s: timeout waiting for lock\n",
 231                                         clk->name);
 232         } else {
 233                 ctrl &= ~PM_BIT(PLLEN);
 234                 pm_writel(PLL1, ctrl);
 235         }
 236 }
 237
 238 static unsigned long pll1_get_rate(struct clk *clk)
 239 {
 240         u32 control;
 241
 242         control = pm_readl(PLL1);
 243
 244         return pll_get_rate(clk, control);
 245 }
 246
 247 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
 248 {
 249         u32 ctrl = 0;
 250         unsigned long actual_rate;
 251
 252         actual_rate = pll_set_rate(clk, rate, &ctrl);
 253
 254         if (apply) {
 255                 if (actual_rate != rate)
 256                         return -EINVAL;
 257                 if (clk->users > 0)
 258                         return -EBUSY;
 259                 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
 260                                 clk->name, rate, actual_rate);
 261                 pm_writel(PLL1, ctrl);
 262         }
 263
 264         return actual_rate;
 265 }
 266
 267 static int pll1_set_parent(struct clk *clk, struct clk *parent)
 268 {
 269         u32 ctrl;
 270
 271         if (clk->users > 0)
 272                 return -EBUSY;
 273
 274         ctrl = pm_readl(PLL1);
 275         WARN_ON(ctrl & PM_BIT(PLLEN));
 276
 277         if (parent == &osc0)
 278                 ctrl &= ~PM_BIT(PLLOSC);
 279         else if (parent == &osc1)
 280                 ctrl |= PM_BIT(PLLOSC);
 281         else
 282                 return -EINVAL;
 283
 284         pm_writel(PLL1, ctrl);
 285         clk->parent = parent;
 286
 287         return 0;
 288 }
 289
 290 /*
 291  * The AT32AP7000 has five primary clock sources: One 32kHz
 292  * oscillator, two crystal oscillators and two PLLs.
 293  */
 294 static struct clk osc32k = {
 295         .name           = "osc32k",
 296         .get_rate       = osc_get_rate,
 297         .users          = 1,
 298         .index          = 0,
 299 };
 300 static struct clk osc0 = {
 301         .name           = "osc0",
 302         .get_rate       = osc_get_rate,
 303         .users          = 1,
 304         .index          = 1,
 305 };
 306 static struct clk osc1 = {
 307         .name           = "osc1",
 308         .get_rate       = osc_get_rate,
 309         .index          = 2,
 310 };
 311 static struct clk pll0 = {
 312         .name           = "pll0",
 313         .get_rate       = pll0_get_rate,
 314         .parent         = &osc0,
 315 };
 316 static struct clk pll1 = {
 317         .name           = "pll1",
 318         .mode           = pll1_mode,
 319         .get_rate       = pll1_get_rate,
 320         .set_rate       = pll1_set_rate,
 321         .set_parent     = pll1_set_parent,
 322         .parent         = &osc0,
 323 };
 324
 325 /*
 326  * The main clock can be either osc0 or pll0.  The boot loader may
 327  * have chosen one for us, so we don't really know which one until we
 328  * have a look at the SM.
 329  */
 330 static struct clk *main_clock;
 331
 332 /*
 333  * Synchronous clocks are generated from the main clock. The clocks
 334  * must satisfy the constraint
 335  *   fCPU >= fHSB >= fPB
 336  * i.e. each clock must not be faster than its parent.
 337  */
 338 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 339 {
 340         return main_clock->get_rate(main_clock) >> shift;
 341 };
 342
 343 static void cpu_clk_mode(struct clk *clk, int enabled)
 344 {
 345         unsigned long flags;
 346         u32 mask;
 347
 348         spin_lock_irqsave(&pm_lock, flags);
 349         mask = pm_readl(CPU_MASK);
 350         if (enabled)
 351                 mask |= 1 << clk->index;
 352         else
 353                 mask &= ~(1 << clk->index);
 354         pm_writel(CPU_MASK, mask);
 355         spin_unlock_irqrestore(&pm_lock, flags);
 356 }
 357
 358 static unsigned long cpu_clk_get_rate(struct clk *clk)
 359 {
 360         unsigned long cksel, shift = 0;
 361
 362         cksel = pm_readl(CKSEL);
 363         if (cksel & PM_BIT(CPUDIV))
 364                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 365
 366         return bus_clk_get_rate(clk, shift);
 367 }
 368
 369 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 370 {
 371         u32 control;
 372         unsigned long parent_rate, child_div, actual_rate, div;
 373
 374         parent_rate = clk->parent->get_rate(clk->parent);
 375         control = pm_readl(CKSEL);
 376
 377         if (control & PM_BIT(HSBDIV))
 378                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 379         else
 380                 child_div = 1;
 381
 382         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 383                 actual_rate = parent_rate;
 384                 control &= ~PM_BIT(CPUDIV);
 385         } else {
 386                 unsigned int cpusel;
 387                 div = (parent_rate + rate / 2) / rate;
 388                 if (div > child_div)
 389                         div = child_div;
 390                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
 391                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 392                 actual_rate = parent_rate / (1 << (cpusel + 1));
 393         }
 394
 395         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 396                         clk->name, rate, actual_rate);
 397
 398         if (apply)
 399                 pm_writel(CKSEL, control);
 400
 401         return actual_rate;
 402 }
 403
 404 static void hsb_clk_mode(struct clk *clk, int enabled)
 405 {
 406         unsigned long flags;
 407         u32 mask;
 408
 409         spin_lock_irqsave(&pm_lock, flags);
 410         mask = pm_readl(HSB_MASK);
 411         if (enabled)
 412                 mask |= 1 << clk->index;
 413         else
 414                 mask &= ~(1 << clk->index);
 415         pm_writel(HSB_MASK, mask);
 416         spin_unlock_irqrestore(&pm_lock, flags);
 417 }
 418
 419 static unsigned long hsb_clk_get_rate(struct clk *clk)
 420 {
 421         unsigned long cksel, shift = 0;
 422
 423         cksel = pm_readl(CKSEL);
 424         if (cksel & PM_BIT(HSBDIV))
 425                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 426
 427         return bus_clk_get_rate(clk, shift);
 428 }
 429
 430 void pba_clk_mode(struct clk *clk, int enabled)
 431 {
 432         unsigned long flags;
 433         u32 mask;
 434
 435         spin_lock_irqsave(&pm_lock, flags);
 436         mask = pm_readl(PBA_MASK);
 437         if (enabled)
 438                 mask |= 1 << clk->index;
 439         else
 440                 mask &= ~(1 << clk->index);
 441         pm_writel(PBA_MASK, mask);
 442         spin_unlock_irqrestore(&pm_lock, flags);
 443 }
 444
 445 unsigned long pba_clk_get_rate(struct clk *clk)
 446 {
 447         unsigned long cksel, shift = 0;
 448
 449         cksel = pm_readl(CKSEL);
 450         if (cksel & PM_BIT(PBADIV))
 451                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 452
 453         return bus_clk_get_rate(clk, shift);
 454 }
 455
 456 static void pbb_clk_mode(struct clk *clk, int enabled)
 457 {
 458         unsigned long flags;
 459         u32 mask;
 460
 461         spin_lock_irqsave(&pm_lock, flags);
 462         mask = pm_readl(PBB_MASK);
 463         if (enabled)
 464                 mask |= 1 << clk->index;
 465         else
 466                 mask &= ~(1 << clk->index);
 467         pm_writel(PBB_MASK, mask);
 468         spin_unlock_irqrestore(&pm_lock, flags);
 469 }
 470
 471 static unsigned long pbb_clk_get_rate(struct clk *clk)
 472 {
 473         unsigned long cksel, shift = 0;
 474
 475         cksel = pm_readl(CKSEL);
 476         if (cksel & PM_BIT(PBBDIV))
 477                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 478
 479         return bus_clk_get_rate(clk, shift);
 480 }
 481
 482 static struct clk cpu_clk = {
 483         .name           = "cpu",
 484         .get_rate       = cpu_clk_get_rate,
 485         .set_rate       = cpu_clk_set_rate,
 486         .users          = 1,
 487 };
 488 static struct clk hsb_clk = {
 489         .name           = "hsb",
 490         .parent         = &cpu_clk,
 491         .get_rate       = hsb_clk_get_rate,
 492 };
 493 static struct clk pba_clk = {
 494         .name           = "pba",
 495         .parent         = &hsb_clk,
 496         .mode           = hsb_clk_mode,
 497         .get_rate       = pba_clk_get_rate,
 498         .index          = 1,
 499 };
 500 static struct clk pbb_clk = {
 501         .name           = "pbb",
 502         .parent         = &hsb_clk,
 503         .mode           = hsb_clk_mode,
 504         .get_rate       = pbb_clk_get_rate,
 505         .users          = 1,
 506         .index          = 2,
 507 };
 508
 509 /* --------------------------------------------------------------------
 510  *  Generic Clock operations
 511  * -------------------------------------------------------------------- */
 512
 513 static void genclk_mode(struct clk *clk, int enabled)
 514 {
 515         u32 control;
 516
 517         control = pm_readl(GCCTRL(clk->index));
 518         if (enabled)
 519                 control |= PM_BIT(CEN);
 520         else
 521                 control &= ~PM_BIT(CEN);
 522         pm_writel(GCCTRL(clk->index), control);
 523 }
 524
 525 static unsigned long genclk_get_rate(struct clk *clk)
 526 {
 527         u32 control;
 528         unsigned long div = 1;
 529
 530         control = pm_readl(GCCTRL(clk->index));
 531         if (control & PM_BIT(DIVEN))
 532                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 533
 534         return clk->parent->get_rate(clk->parent) / div;
 535 }
 536
 537 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 538 {
 539         u32 control;
 540         unsigned long parent_rate, actual_rate, div;
 541
 542         parent_rate = clk->parent->get_rate(clk->parent);
 543         control = pm_readl(GCCTRL(clk->index));
 544
 545         if (rate > 3 * parent_rate / 4) {
 546                 actual_rate = parent_rate;
 547                 control &= ~PM_BIT(DIVEN);
 548         } else {
 549                 div = (parent_rate + rate) / (2 * rate) - 1;
 550                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 551                 actual_rate = parent_rate / (2 * (div + 1));
 552         }
 553
 554         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 555                 clk->name, rate, actual_rate);
 556
 557         if (apply)
 558                 pm_writel(GCCTRL(clk->index), control);
 559
 560         return actual_rate;
 561 }
 562
 563 int genclk_set_parent(struct clk *clk, struct clk *parent)
 564 {
 565         u32 control;
 566
 567         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 568                 clk->name, parent->name, clk->parent->name);
 569
 570         control = pm_readl(GCCTRL(clk->index));
 571
 572         if (parent == &osc1 || parent == &pll1)
 573                 control |= PM_BIT(OSCSEL);
 574         else if (parent == &osc0 || parent == &pll0)
 575                 control &= ~PM_BIT(OSCSEL);
 576         else
 577                 return -EINVAL;
 578
 579         if (parent == &pll0 || parent == &pll1)
 580                 control |= PM_BIT(PLLSEL);
 581         else
 582                 control &= ~PM_BIT(PLLSEL);
 583
 584         pm_writel(GCCTRL(clk->index), control);
 585         clk->parent = parent;
 586
 587         return 0;
 588 }
 589
 590 static void __init genclk_init_parent(struct clk *clk)
 591 {
 592         u32 control;
 593         struct clk *parent;
 594
 595         BUG_ON(clk->index > 7);
 596
 597         control = pm_readl(GCCTRL(clk->index));
 598         if (control & PM_BIT(OSCSEL))
 599                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 600         else
 601                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 602
 603         clk->parent = parent;
 604 }
 605
 606 static struct dw_dma_platform_data dw_dmac0_data = {
 607         .nr_channels    = 3,
 608 };
 609
 610 static struct resource dw_dmac0_resource[] = {
 611         PBMEM(0xff200000),
 612         IRQ(2),
 613 };
 614 DEFINE_DEV_DATA(dw_dmac, 0);
 615 DEV_CLK(hclk, dw_dmac0, hsb, 10);
 616
 617 /* --------------------------------------------------------------------
 618  *  System peripherals
 619  * -------------------------------------------------------------------- */
 620 static struct resource at32_pm0_resource[] = {
 621         {
 622                 .start  = 0xfff00000,
 623                 .end    = 0xfff0007f,
 624                 .flags  = IORESOURCE_MEM,
 625         },
 626         IRQ(20),
 627 };
 628
 629 static struct resource at32ap700x_rtc0_resource[] = {
 630         {
 631                 .start  = 0xfff00080,
 632                 .end    = 0xfff000af,
 633                 .flags  = IORESOURCE_MEM,
 634         },
 635         IRQ(21),
 636 };
 637
 638 static struct resource at32_wdt0_resource[] = {
 639         {
 640                 .start  = 0xfff000b0,
 641                 .end    = 0xfff000cf,
 642                 .flags  = IORESOURCE_MEM,
 643         },
 644 };
 645
 646 static struct resource at32_eic0_resource[] = {
 647         {
 648                 .start  = 0xfff00100,
 649                 .end    = 0xfff0013f,
 650                 .flags  = IORESOURCE_MEM,
 651         },
 652         IRQ(19),
 653 };
 654
 655 DEFINE_DEV(at32_pm, 0);
 656 DEFINE_DEV(at32ap700x_rtc, 0);
 657 DEFINE_DEV(at32_wdt, 0);
 658 DEFINE_DEV(at32_eic, 0);
 659
 660 /*
 661  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 662  * is always running.
 663  */
 664 static struct clk at32_pm_pclk = {
 665         .name           = "pclk",
 666         .dev            = &at32_pm0_device.dev,
 667         .parent         = &pbb_clk,
 668         .mode           = pbb_clk_mode,
 669         .get_rate       = pbb_clk_get_rate,
 670         .users          = 1,
 671         .index          = 0,
 672 };
 673
 674 static struct resource intc0_resource[] = {
 675         PBMEM(0xfff00400),
 676 };
 677 struct platform_device at32_intc0_device = {
 678         .name           = "intc",
 679         .id             = 0,
 680         .resource       = intc0_resource,
 681         .num_resources  = ARRAY_SIZE(intc0_resource),
 682 };
 683 DEV_CLK(pclk, at32_intc0, pbb, 1);
 684
 685 static struct clk ebi_clk = {
 686         .name           = "ebi",
 687         .parent         = &hsb_clk,
 688         .mode           = hsb_clk_mode,
 689         .get_rate       = hsb_clk_get_rate,
 690         .users          = 1,
 691 };
 692 static struct clk hramc_clk = {
 693         .name           = "hramc",
 694         .parent         = &hsb_clk,
 695         .mode           = hsb_clk_mode,
 696         .get_rate       = hsb_clk_get_rate,
 697         .users          = 1,
 698         .index          = 3,
 699 };
 700 static struct clk sdramc_clk = {
 701         .name           = "sdramc_clk",
 702         .parent         = &pbb_clk,
 703         .mode           = pbb_clk_mode,
 704         .get_rate       = pbb_clk_get_rate,
 705         .users          = 1,
 706         .index          = 14,
 707 };
 708
 709 static struct resource smc0_resource[] = {
 710         PBMEM(0xfff03400),
 711 };
 712 DEFINE_DEV(smc, 0);
 713 DEV_CLK(pclk, smc0, pbb, 13);
 714 DEV_CLK(mck, smc0, hsb, 0);
 715
 716 static struct platform_device pdc_device = {
 717         .name           = "pdc",
 718         .id             = 0,
 719 };
 720 DEV_CLK(hclk, pdc, hsb, 4);
 721 DEV_CLK(pclk, pdc, pba, 16);
 722
 723 static struct clk pico_clk = {
 724         .name           = "pico",
 725         .parent         = &cpu_clk,
 726         .mode           = cpu_clk_mode,
 727         .get_rate       = cpu_clk_get_rate,
 728         .users          = 1,
 729 };
 730
 731 /* --------------------------------------------------------------------
 732  * HMATRIX
 733  * -------------------------------------------------------------------- */
 734
 735 struct clk at32_hmatrix_clk = {
 736         .name           = "hmatrix_clk",
 737         .parent         = &pbb_clk,
 738         .mode           = pbb_clk_mode,
 739         .get_rate       = pbb_clk_get_rate,
 740         .index          = 2,
 741         .users          = 1,
 742 };
 743
 744 /*
 745  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 746  * External Bus Interface (EBI). This can be used to enable special
 747  * features like CompactFlash support, NAND Flash support, etc. on
 748  * certain chipselects.
 749  */
 750 static inline void set_ebi_sfr_bits(u32 mask)
 751 {
 752         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
 753 }
 754
 755 /* --------------------------------------------------------------------
 756  *  Timer/Counter (TC)
 757  * -------------------------------------------------------------------- */
 758
 759 static struct resource at32_tcb0_resource[] = {
 760         PBMEM(0xfff00c00),
 761         IRQ(22),
 762 };
 763 static struct platform_device at32_tcb0_device = {
 764         .name           = "atmel_tcb",
 765         .id             = 0,
 766         .resource       = at32_tcb0_resource,
 767         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
 768 };
 769 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
 770
 771 static struct resource at32_tcb1_resource[] = {
 772         PBMEM(0xfff01000),
 773         IRQ(23),
 774 };
 775 static struct platform_device at32_tcb1_device = {
 776         .name           = "atmel_tcb",
 777         .id             = 1,
 778         .resource       = at32_tcb1_resource,
 779         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
 780 };
 781 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
 782
 783 /* --------------------------------------------------------------------
 784  *  PIO
 785  * -------------------------------------------------------------------- */
 786
 787 static struct resource pio0_resource[] = {
 788         PBMEM(0xffe02800),
 789         IRQ(13),
 790 };
 791 DEFINE_DEV(pio, 0);
 792 DEV_CLK(mck, pio0, pba, 10);
 793
 794 static struct resource pio1_resource[] = {
 795         PBMEM(0xffe02c00),
 796         IRQ(14),
 797 };
 798 DEFINE_DEV(pio, 1);
 799 DEV_CLK(mck, pio1, pba, 11);
 800
 801 static struct resource pio2_resource[] = {
 802         PBMEM(0xffe03000),
 803         IRQ(15),
 804 };
 805 DEFINE_DEV(pio, 2);
 806 DEV_CLK(mck, pio2, pba, 12);
 807
 808 static struct resource pio3_resource[] = {
 809         PBMEM(0xffe03400),
 810         IRQ(16),
 811 };
 812 DEFINE_DEV(pio, 3);
 813 DEV_CLK(mck, pio3, pba, 13);
 814
 815 static struct resource pio4_resource[] = {
 816         PBMEM(0xffe03800),
 817         IRQ(17),
 818 };
 819 DEFINE_DEV(pio, 4);
 820 DEV_CLK(mck, pio4, pba, 14);
 821
 822 static int __init system_device_init(void)
 823 {
 824         platform_device_register(&at32_pm0_device);
 825         platform_device_register(&at32_intc0_device);
 826         platform_device_register(&at32ap700x_rtc0_device);
 827         platform_device_register(&at32_wdt0_device);
 828         platform_device_register(&at32_eic0_device);
 829         platform_device_register(&smc0_device);
 830         platform_device_register(&pdc_device);
 831         platform_device_register(&dw_dmac0_device);
 832
 833         platform_device_register(&at32_tcb0_device);
 834         platform_device_register(&at32_tcb1_device);
 835
 836         platform_device_register(&pio0_device);
 837         platform_device_register(&pio1_device);
 838         platform_device_register(&pio2_device);
 839         platform_device_register(&pio3_device);
 840         platform_device_register(&pio4_device);
 841
 842         return 0;
 843 }
 844 core_initcall(system_device_init);
 845
 846 /* --------------------------------------------------------------------
 847  *  PSIF
 848  * -------------------------------------------------------------------- */
 849 static struct resource atmel_psif0_resource[] __initdata = {
 850         {
 851                 .start  = 0xffe03c00,
 852                 .end    = 0xffe03cff,
 853                 .flags  = IORESOURCE_MEM,
 854         },
 855         IRQ(18),
 856 };
 857 static struct clk atmel_psif0_pclk = {
 858         .name           = "pclk",
 859         .parent         = &pba_clk,
 860         .mode           = pba_clk_mode,
 861         .get_rate       = pba_clk_get_rate,
 862         .index          = 15,
 863 };
 864
 865 static struct resource atmel_psif1_resource[] __initdata = {
 866         {
 867                 .start  = 0xffe03d00,
 868                 .end    = 0xffe03dff,
 869                 .flags  = IORESOURCE_MEM,
 870         },
 871         IRQ(18),
 872 };
 873 static struct clk atmel_psif1_pclk = {
 874         .name           = "pclk",
 875         .parent         = &pba_clk,
 876         .mode           = pba_clk_mode,
 877         .get_rate       = pba_clk_get_rate,
 878         .index          = 15,
 879 };
 880
 881 struct platform_device *__init at32_add_device_psif(unsigned int id)
 882 {
 883         struct platform_device *pdev;
 884         u32 pin_mask;
 885
 886         if (!(id == 0 || id == 1))
 887                 return NULL;
 888
 889         pdev = platform_device_alloc("atmel_psif", id);
 890         if (!pdev)
 891                 return NULL;
 892
 893         switch (id) {
 894         case 0:
 895                 pin_mask  = (1 << 8) | (1 << 9); /* CLOCK & DATA */
 896
 897                 if (platform_device_add_resources(pdev, atmel_psif0_resource,
 898                                         ARRAY_SIZE(atmel_psif0_resource)))
 899                         goto err_add_resources;
 900                 atmel_psif0_pclk.dev = &pdev->dev;
 901                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
 902                 break;
 903         case 1:
 904                 pin_mask  = (1 << 11) | (1 << 12); /* CLOCK & DATA */
 905
 906                 if (platform_device_add_resources(pdev, atmel_psif1_resource,
 907                                         ARRAY_SIZE(atmel_psif1_resource)))
 908                         goto err_add_resources;
 909                 atmel_psif1_pclk.dev = &pdev->dev;
 910                 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
 911                 break;
 912         default:
 913                 return NULL;
 914         }
 915
 916         platform_device_add(pdev);
 917         return pdev;
 918
 919 err_add_resources:
 920         platform_device_put(pdev);
 921         return NULL;
 922 }
 923
 924 /* --------------------------------------------------------------------
 925  *  USART
 926  * -------------------------------------------------------------------- */
 927
 928 static struct atmel_uart_data atmel_usart0_data = {
 929         .use_dma_tx     = 1,
 930         .use_dma_rx     = 1,
 931 };
 932 static struct resource atmel_usart0_resource[] = {
 933         PBMEM(0xffe00c00),
 934         IRQ(6),
 935 };
 936 DEFINE_DEV_DATA(atmel_usart, 0);
 937 DEV_CLK(usart, atmel_usart0, pba, 3);
 938
 939 static struct atmel_uart_data atmel_usart1_data = {
 940         .use_dma_tx     = 1,
 941         .use_dma_rx     = 1,
 942 };
 943 static struct resource atmel_usart1_resource[] = {
 944         PBMEM(0xffe01000),
 945         IRQ(7),
 946 };
 947 DEFINE_DEV_DATA(atmel_usart, 1);
 948 DEV_CLK(usart, atmel_usart1, pba, 4);
 949
 950 static struct atmel_uart_data atmel_usart2_data = {
 951         .use_dma_tx     = 1,
 952         .use_dma_rx     = 1,
 953 };
 954 static struct resource atmel_usart2_resource[] = {
 955         PBMEM(0xffe01400),
 956         IRQ(8),
 957 };
 958 DEFINE_DEV_DATA(atmel_usart, 2);
 959 DEV_CLK(usart, atmel_usart2, pba, 5);
 960
 961 static struct atmel_uart_data atmel_usart3_data = {
 962         .use_dma_tx     = 1,
 963         .use_dma_rx     = 1,
 964 };
 965 static struct resource atmel_usart3_resource[] = {
 966         PBMEM(0xffe01800),
 967         IRQ(9),
 968 };
 969 DEFINE_DEV_DATA(atmel_usart, 3);
 970 DEV_CLK(usart, atmel_usart3, pba, 6);
 971
 972 static inline void configure_usart0_pins(int flags)
 973 {
 974         u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
 975         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 6);
 976         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 7);
 977         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 10);
 978
 979         select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
 980 }
 981
 982 static inline void configure_usart1_pins(int flags)
 983 {
 984         u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
 985         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 19);
 986         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 20);
 987         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 16);
 988
 989         select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
 990 }
 991
 992 static inline void configure_usart2_pins(int flags)
 993 {
 994         u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
 995         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 30);
 996         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 29);
 997         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 28);
 998
 999         select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1000 }
1001
1002 static inline void configure_usart3_pins(int flags)
1003 {
1004         u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
1005         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 16);
1006         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 15);
1007         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 19);
1008
1009         select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1010 }
1011
1012 static struct platform_device *__initdata at32_usarts[4];
1013
1014 void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
1015 {
1016         struct platform_device *pdev;
1017         struct atmel_uart_data *pdata;
1018
1019         switch (hw_id) {
1020         case 0:
1021                 pdev = &atmel_usart0_device;
1022                 configure_usart0_pins(flags);
1023                 break;
1024         case 1:
1025                 pdev = &atmel_usart1_device;
1026                 configure_usart1_pins(flags);
1027                 break;
1028         case 2:
1029                 pdev = &atmel_usart2_device;
1030                 configure_usart2_pins(flags);
1031                 break;
1032         case 3:
1033                 pdev = &atmel_usart3_device;
1034                 configure_usart3_pins(flags);
1035                 break;
1036         default:
1037                 return;
1038         }
1039
1040         if (PXSEG(pdev->resource[0].start) == P4SEG) {
1041                 /* Addresses in the P4 segment are permanently mapped 1:1 */
1042                 struct atmel_uart_data *data = pdev->dev.platform_data;
1043                 data->regs = (void __iomem *)pdev->resource[0].start;
1044         }
1045
1046         pdev->id = line;
1047         pdata = pdev->dev.platform_data;
1048         pdata->num = line;
1049         at32_usarts[line] = pdev;
1050 }
1051
1052 struct platform_device *__init at32_add_device_usart(unsigned int id)
1053 {
1054         platform_device_register(at32_usarts[id]);
1055         return at32_usarts[id];
1056 }
1057
1058 void __init at32_setup_serial_console(unsigned int usart_id)
1059 {
1060         atmel_default_console_device = at32_usarts[usart_id];
1061 }
1062
1063 /* --------------------------------------------------------------------
1064  *  Ethernet
1065  * -------------------------------------------------------------------- */
1066
1067 #ifdef CONFIG_CPU_AT32AP7000
1068 static struct macb_platform_data macb0_data;
1069 static struct resource macb0_resource[] = {
1070         PBMEM(0xfff01800),
1071         IRQ(25),
1072 };
1073 DEFINE_DEV_DATA(macb, 0);
1074 DEV_CLK(hclk, macb0, hsb, 8);
1075 DEV_CLK(pclk, macb0, pbb, 6);
1076
1077 static struct macb_platform_data macb1_data;
1078 static struct resource macb1_resource[] = {
1079         PBMEM(0xfff01c00),
1080         IRQ(26),
1081 };
1082 DEFINE_DEV_DATA(macb, 1);
1083 DEV_CLK(hclk, macb1, hsb, 9);
1084 DEV_CLK(pclk, macb1, pbb, 7);
1085
1086 struct platform_device *__init
1087 at32_add_device_eth(unsigned int id, struct macb_platform_data *data)
1088 {
1089         struct platform_device *pdev;
1090         u32 pin_mask;
1091
1092         switch (id) {
1093         case 0:
1094                 pdev = &macb0_device;
1095
1096                 pin_mask  = (1 << 3);   /* TXD0 */
1097                 pin_mask |= (1 << 4);   /* TXD1 */
1098                 pin_mask |= (1 << 7);   /* TXEN */
1099                 pin_mask |= (1 << 8);   /* TXCK */
1100                 pin_mask |= (1 << 9);   /* RXD0 */
1101                 pin_mask |= (1 << 10);  /* RXD1 */
1102                 pin_mask |= (1 << 13);  /* RXER */
1103                 pin_mask |= (1 << 15);  /* RXDV */
1104                 pin_mask |= (1 << 16);  /* MDC  */
1105                 pin_mask |= (1 << 17);  /* MDIO */
1106
1107                 if (!data->is_rmii) {
1108                         pin_mask |= (1 << 0);   /* COL  */
1109                         pin_mask |= (1 << 1);   /* CRS  */
1110                         pin_mask |= (1 << 2);   /* TXER */
1111                         pin_mask |= (1 << 5);   /* TXD2 */
1112                         pin_mask |= (1 << 6);   /* TXD3 */
1113                         pin_mask |= (1 << 11);  /* RXD2 */
1114                         pin_mask |= (1 << 12);  /* RXD3 */
1115                         pin_mask |= (1 << 14);  /* RXCK */
1116 #ifndef CONFIG_BOARD_MIMC200
1117                         pin_mask |= (1 << 18);  /* SPD  */
1118 #endif
1119                 }
1120
1121                 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1122
1123                 break;
1124
1125         case 1:
1126                 pdev = &macb1_device;
1127
1128                 pin_mask  = (1 << 13);  /* TXD0 */
1129                 pin_mask |= (1 << 14);  /* TXD1 */
1130                 pin_mask |= (1 << 11);  /* TXEN */
1131                 pin_mask |= (1 << 12);  /* TXCK */
1132                 pin_mask |= (1 << 10);  /* RXD0 */
1133                 pin_mask |= (1 << 6);   /* RXD1 */
1134                 pin_mask |= (1 << 5);   /* RXER */
1135                 pin_mask |= (1 << 4);   /* RXDV */
1136                 pin_mask |= (1 << 3);   /* MDC  */
1137                 pin_mask |= (1 << 2);   /* MDIO */
1138
1139 #ifndef CONFIG_BOARD_MIMC200
1140                 if (!data->is_rmii)
1141                         pin_mask |= (1 << 15);  /* SPD  */
1142 #endif
1143
1144                 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1145
1146                 if (!data->is_rmii) {
1147                         pin_mask  = (1 << 19);  /* COL  */
1148                         pin_mask |= (1 << 23);  /* CRS  */
1149                         pin_mask |= (1 << 26);  /* TXER */
1150                         pin_mask |= (1 << 27);  /* TXD2 */
1151                         pin_mask |= (1 << 28);  /* TXD3 */
1152                         pin_mask |= (1 << 29);  /* RXD2 */
1153                         pin_mask |= (1 << 30);  /* RXD3 */
1154                         pin_mask |= (1 << 24);  /* RXCK */
1155
1156                         select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1157                 }
1158                 break;
1159
1160         default:
1161                 return NULL;
1162         }
1163
1164         memcpy(pdev->dev.platform_data, data, sizeof(struct macb_platform_data));
1165         platform_device_register(pdev);
1166
1167         return pdev;
1168 }
1169 #endif
1170
1171 /* --------------------------------------------------------------------
1172  *  SPI
1173  * -------------------------------------------------------------------- */
1174 static struct resource atmel_spi0_resource[] = {
1175         PBMEM(0xffe00000),
1176         IRQ(3),
1177 };
1178 DEFINE_DEV(atmel_spi, 0);
1179 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1180
1181 static struct resource atmel_spi1_resource[] = {
1182         PBMEM(0xffe00400),
1183         IRQ(4),
1184 };
1185 DEFINE_DEV(atmel_spi, 1);
1186 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1187
1188 void __init
1189 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
1190 {
1191         /*
1192          * Manage the chipselects as GPIOs, normally using the same pins
1193          * the SPI controller expects; but boards can use other pins.
1194          */
1195         static u8 __initdata spi_pins[][4] = {
1196                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1197                   GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
1198                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1199                   GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
1200         };
1201         unsigned int pin, mode;
1202
1203         /* There are only 2 SPI controllers */
1204         if (bus_num > 1)
1205                 return;
1206
1207         for (; n; n--, b++) {
1208                 b->bus_num = bus_num;
1209                 if (b->chip_select >= 4)
1210                         continue;
1211                 pin = (unsigned)b->controller_data;
1212                 if (!pin) {
1213                         pin = spi_pins[bus_num][b->chip_select];
1214                         b->controller_data = (void *)pin;
1215                 }
1216                 mode = AT32_GPIOF_OUTPUT;
1217                 if (!(b->mode & SPI_CS_HIGH))
1218                         mode |= AT32_GPIOF_HIGH;
1219                 at32_select_gpio(pin, mode);
1220         }
1221 }
1222
1223 struct platform_device *__init
1224 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1225 {
1226         struct platform_device *pdev;
1227         u32 pin_mask;
1228
1229         switch (id) {
1230         case 0:
1231                 pdev = &atmel_spi0_device;
1232                 pin_mask  = (1 << 1) | (1 << 2);        /* MOSI & SCK */
1233
1234                 /* pullup MISO so a level is always defined */
1235                 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1236                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1237
1238                 at32_spi_setup_slaves(0, b, n);
1239                 break;
1240
1241         case 1:
1242                 pdev = &atmel_spi1_device;
1243                 pin_mask  = (1 << 1) | (1 << 5);        /* MOSI */
1244
1245                 /* pullup MISO so a level is always defined */
1246                 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1247                 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1248
1249                 at32_spi_setup_slaves(1, b, n);
1250                 break;
1251
1252         default:
1253                 return NULL;
1254         }
1255
1256         spi_register_board_info(b, n);
1257         platform_device_register(pdev);
1258         return pdev;
1259 }
1260
1261 /* --------------------------------------------------------------------
1262  *  TWI
1263  * -------------------------------------------------------------------- */
1264 static struct resource atmel_twi0_resource[] __initdata = {
1265         PBMEM(0xffe00800),
1266         IRQ(5),
1267 };
1268 static struct clk atmel_twi0_pclk = {
1269         .name           = "twi_pclk",
1270         .parent         = &pba_clk,
1271         .mode           = pba_clk_mode,
1272         .get_rate       = pba_clk_get_rate,
1273         .index          = 2,
1274 };
1275
1276 struct platform_device *__init at32_add_device_twi(unsigned int id,
1277                                                     struct i2c_board_info *b,
1278                                                     unsigned int n)
1279 {
1280         struct platform_device *pdev;
1281         u32 pin_mask;
1282
1283         if (id != 0)
1284                 return NULL;
1285
1286         pdev = platform_device_alloc("atmel_twi", id);
1287         if (!pdev)
1288                 return NULL;
1289
1290         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1291                                 ARRAY_SIZE(atmel_twi0_resource)))
1292                 goto err_add_resources;
1293
1294         pin_mask  = (1 << 6) | (1 << 7);        /* SDA & SDL */
1295
1296         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1297
1298         atmel_twi0_pclk.dev = &pdev->dev;
1299
1300         if (b)
1301                 i2c_register_board_info(id, b, n);
1302
1303         platform_device_add(pdev);
1304         return pdev;
1305
1306 err_add_resources:
1307         platform_device_put(pdev);
1308         return NULL;
1309 }
1310
1311 /* --------------------------------------------------------------------
1312  * MMC
1313  * -------------------------------------------------------------------- */
1314 static struct resource atmel_mci0_resource[] __initdata = {
1315         PBMEM(0xfff02400),
1316         IRQ(28),
1317 };
1318 static struct clk atmel_mci0_pclk = {
1319         .name           = "mci_clk",
1320         .parent         = &pbb_clk,
1321         .mode           = pbb_clk_mode,
1322         .get_rate       = pbb_clk_get_rate,
1323         .index          = 9,
1324 };
1325
1326 struct platform_device *__init
1327 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1328 {
1329         struct platform_device          *pdev;
1330         struct mci_dma_data             *slave;
1331         u32                             pioa_mask;
1332         u32                             piob_mask;
1333
1334         if (id != 0 || !data)
1335                 return NULL;
1336
1337         /* Must have at least one usable slot */
1338         if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1339                 return NULL;
1340
1341         pdev = platform_device_alloc("atmel_mci", id);
1342         if (!pdev)
1343                 goto fail;
1344
1345         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1346                                 ARRAY_SIZE(atmel_mci0_resource)))
1347                 goto fail;
1348
1349         slave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
1350         if (!slave)
1351                 goto fail;
1352
1353         slave->sdata.dma_dev = &dw_dmac0_device.dev;
1354         slave->sdata.reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
1355         slave->sdata.cfg_hi = (DWC_CFGH_SRC_PER(0)
1356                                 | DWC_CFGH_DST_PER(1));
1357         slave->sdata.cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1358                                 | DWC_CFGL_HS_SRC_POL);
1359
1360         data->dma_slave = slave;
1361
1362         if (platform_device_add_data(pdev, data,
1363                                 sizeof(struct mci_platform_data)))
1364                 goto fail_free;
1365
1366         /* CLK line is common to both slots */
1367         pioa_mask = 1 << 10;
1368
1369         switch (data->slot[0].bus_width) {
1370         case 4:
1371                 pioa_mask |= 1 << 13;           /* DATA1 */
1372                 pioa_mask |= 1 << 14;           /* DATA2 */
1373                 pioa_mask |= 1 << 15;           /* DATA3 */
1374                 /* fall through */
1375         case 1:
1376                 pioa_mask |= 1 << 11;           /* CMD   */
1377                 pioa_mask |= 1 << 12;           /* DATA0 */
1378
1379                 if (gpio_is_valid(data->slot[0].detect_pin))
1380                         at32_select_gpio(data->slot[0].detect_pin, 0);
1381                 if (gpio_is_valid(data->slot[0].wp_pin))
1382                         at32_select_gpio(data->slot[0].wp_pin, 0);
1383                 break;
1384         case 0:
1385                 /* Slot is unused */
1386                 break;
1387         default:
1388                 goto fail_free;
1389         }
1390
1391         select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1392         piob_mask = 0;
1393
1394         switch (data->slot[1].bus_width) {
1395         case 4:
1396                 piob_mask |= 1 <<  8;           /* DATA1 */
1397                 piob_mask |= 1 <<  9;           /* DATA2 */
1398                 piob_mask |= 1 << 10;           /* DATA3 */
1399                 /* fall through */
1400         case 1:
1401                 piob_mask |= 1 <<  6;           /* CMD   */
1402                 piob_mask |= 1 <<  7;           /* DATA0 */
1403                 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1404
1405                 if (gpio_is_valid(data->slot[1].detect_pin))
1406                         at32_select_gpio(data->slot[1].detect_pin, 0);
1407                 if (gpio_is_valid(data->slot[1].wp_pin))
1408                         at32_select_gpio(data->slot[1].wp_pin, 0);
1409                 break;
1410         case 0:
1411                 /* Slot is unused */
1412                 break;
1413         default:
1414                 if (!data->slot[0].bus_width)
1415                         goto fail_free;
1416
1417                 data->slot[1].bus_width = 0;
1418                 break;
1419         }
1420
1421         atmel_mci0_pclk.dev = &pdev->dev;
1422
1423         platform_device_add(pdev);
1424         return pdev;
1425
1426 fail_free:
1427         kfree(slave);
1428 fail:
1429         data->dma_slave = NULL;
1430         platform_device_put(pdev);
1431         return NULL;
1432 }
1433
1434 /* --------------------------------------------------------------------
1435  *  LCDC
1436  * -------------------------------------------------------------------- */
1437 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1438 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1439 static struct resource atmel_lcdfb0_resource[] = {
1440         {
1441                 .start          = 0xff000000,
1442                 .end            = 0xff000fff,
1443                 .flags          = IORESOURCE_MEM,
1444         },
1445         IRQ(1),
1446         {
1447                 /* Placeholder for pre-allocated fb memory */
1448                 .start          = 0x00000000,
1449                 .end            = 0x00000000,
1450                 .flags          = 0,
1451         },
1452 };
1453 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1454 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1455 static struct clk atmel_lcdfb0_pixclk = {
1456         .name           = "lcdc_clk",
1457         .dev            = &atmel_lcdfb0_device.dev,
1458         .mode           = genclk_mode,
1459         .get_rate       = genclk_get_rate,
1460         .set_rate       = genclk_set_rate,
1461         .set_parent     = genclk_set_parent,
1462         .index          = 7,
1463 };
1464
1465 struct platform_device *__init
1466 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1467                      unsigned long fbmem_start, unsigned long fbmem_len,
1468                      u64 pin_mask)
1469 {
1470         struct platform_device *pdev;
1471         struct atmel_lcdfb_info *info;
1472         struct fb_monspecs *monspecs;
1473         struct fb_videomode *modedb;
1474         unsigned int modedb_size;
1475         u32 portc_mask, portd_mask, porte_mask;
1476
1477         /*
1478          * Do a deep copy of the fb data, monspecs and modedb. Make
1479          * sure all allocations are done before setting up the
1480          * portmux.
1481          */
1482         monspecs = kmemdup(data->default_monspecs,
1483                            sizeof(struct fb_monspecs), GFP_KERNEL);
1484         if (!monspecs)
1485                 return NULL;
1486
1487         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1488         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1489         if (!modedb)
1490                 goto err_dup_modedb;
1491         monspecs->modedb = modedb;
1492
1493         switch (id) {
1494         case 0:
1495                 pdev = &atmel_lcdfb0_device;
1496
1497                 if (pin_mask == 0ULL)
1498                         /* Default to "full" lcdc control signals and 24bit */
1499                         pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1500
1501                 /* LCDC on port C */
1502                 portc_mask = pin_mask & 0xfff80000;
1503                 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1504
1505                 /* LCDC on port D */
1506                 portd_mask = pin_mask & 0x0003ffff;
1507                 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1508
1509                 /* LCDC on port E */
1510                 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1511                 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1512
1513                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1514                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1515                 break;
1516
1517         default:
1518                 goto err_invalid_id;
1519         }
1520
1521         if (fbmem_len) {
1522                 pdev->resource[2].start = fbmem_start;
1523                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1524                 pdev->resource[2].flags = IORESOURCE_MEM;
1525         }
1526
1527         info = pdev->dev.platform_data;
1528         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1529         info->default_monspecs = monspecs;
1530
1531         platform_device_register(pdev);
1532         return pdev;
1533
1534 err_invalid_id:
1535         kfree(modedb);
1536 err_dup_modedb:
1537         kfree(monspecs);
1538         return NULL;
1539 }
1540 #endif
1541
1542 /* --------------------------------------------------------------------
1543  *  PWM
1544  * -------------------------------------------------------------------- */
1545 static struct resource atmel_pwm0_resource[] __initdata = {
1546         PBMEM(0xfff01400),
1547         IRQ(24),
1548 };
1549 static struct clk atmel_pwm0_mck = {
1550         .name           = "pwm_clk",
1551         .parent         = &pbb_clk,
1552         .mode           = pbb_clk_mode,
1553         .get_rate       = pbb_clk_get_rate,
1554         .index          = 5,
1555 };
1556
1557 struct platform_device *__init at32_add_device_pwm(u32 mask)
1558 {
1559         struct platform_device *pdev;
1560         u32 pin_mask;
1561
1562         if (!mask)
1563                 return NULL;
1564
1565         pdev = platform_device_alloc("atmel_pwm", 0);
1566         if (!pdev)
1567                 return NULL;
1568
1569         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1570                                 ARRAY_SIZE(atmel_pwm0_resource)))
1571                 goto out_free_pdev;
1572
1573         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1574                 goto out_free_pdev;
1575
1576         pin_mask = 0;
1577         if (mask & (1 << 0))
1578                 pin_mask |= (1 << 28);
1579         if (mask & (1 << 1))
1580                 pin_mask |= (1 << 29);
1581         if (pin_mask > 0)
1582                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1583
1584         pin_mask = 0;
1585         if (mask & (1 << 2))
1586                 pin_mask |= (1 << 21);
1587         if (mask & (1 << 3))
1588                 pin_mask |= (1 << 22);
1589         if (pin_mask > 0)
1590                 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1591
1592         atmel_pwm0_mck.dev = &pdev->dev;
1593
1594         platform_device_add(pdev);
1595
1596         return pdev;
1597
1598 out_free_pdev:
1599         platform_device_put(pdev);
1600         return NULL;
1601 }
1602
1603 /* --------------------------------------------------------------------
1604  *  SSC
1605  * -------------------------------------------------------------------- */
1606 static struct resource ssc0_resource[] = {
1607         PBMEM(0xffe01c00),
1608         IRQ(10),
1609 };
1610 DEFINE_DEV(ssc, 0);
1611 DEV_CLK(pclk, ssc0, pba, 7);
1612
1613 static struct resource ssc1_resource[] = {
1614         PBMEM(0xffe02000),
1615         IRQ(11),
1616 };
1617 DEFINE_DEV(ssc, 1);
1618 DEV_CLK(pclk, ssc1, pba, 8);
1619
1620 static struct resource ssc2_resource[] = {
1621         PBMEM(0xffe02400),
1622         IRQ(12),
1623 };
1624 DEFINE_DEV(ssc, 2);
1625 DEV_CLK(pclk, ssc2, pba, 9);
1626
1627 struct platform_device *__init
1628 at32_add_device_ssc(unsigned int id, unsigned int flags)
1629 {
1630         struct platform_device *pdev;
1631         u32 pin_mask = 0;
1632
1633         switch (id) {
1634         case 0:
1635                 pdev = &ssc0_device;
1636                 if (flags & ATMEL_SSC_RF)
1637                         pin_mask |= (1 << 21);  /* RF */
1638                 if (flags & ATMEL_SSC_RK)
1639                         pin_mask |= (1 << 22);  /* RK */
1640                 if (flags & ATMEL_SSC_TK)
1641                         pin_mask |= (1 << 23);  /* TK */
1642                 if (flags & ATMEL_SSC_TF)
1643                         pin_mask |= (1 << 24);  /* TF */
1644                 if (flags & ATMEL_SSC_TD)
1645                         pin_mask |= (1 << 25);  /* TD */
1646                 if (flags & ATMEL_SSC_RD)
1647                         pin_mask |= (1 << 26);  /* RD */
1648
1649                 if (pin_mask > 0)
1650                         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1651
1652                 break;
1653         case 1:
1654                 pdev = &ssc1_device;
1655                 if (flags & ATMEL_SSC_RF)
1656                         pin_mask |= (1 << 0);   /* RF */
1657                 if (flags & ATMEL_SSC_RK)
1658                         pin_mask |= (1 << 1);   /* RK */
1659                 if (flags & ATMEL_SSC_TK)
1660                         pin_mask |= (1 << 2);   /* TK */
1661                 if (flags & ATMEL_SSC_TF)
1662                         pin_mask |= (1 << 3);   /* TF */
1663                 if (flags & ATMEL_SSC_TD)
1664                         pin_mask |= (1 << 4);   /* TD */
1665                 if (flags & ATMEL_SSC_RD)
1666                         pin_mask |= (1 << 5);   /* RD */
1667
1668                 if (pin_mask > 0)
1669                         select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1670
1671                 break;
1672         case 2:
1673                 pdev = &ssc2_device;
1674                 if (flags & ATMEL_SSC_TD)
1675                         pin_mask |= (1 << 13);  /* TD */
1676                 if (flags & ATMEL_SSC_RD)
1677                         pin_mask |= (1 << 14);  /* RD */
1678                 if (flags & ATMEL_SSC_TK)
1679                         pin_mask |= (1 << 15);  /* TK */
1680                 if (flags & ATMEL_SSC_TF)
1681                         pin_mask |= (1 << 16);  /* TF */
1682                 if (flags & ATMEL_SSC_RF)
1683                         pin_mask |= (1 << 17);  /* RF */
1684                 if (flags & ATMEL_SSC_RK)
1685                         pin_mask |= (1 << 18);  /* RK */
1686
1687                 if (pin_mask > 0)
1688                         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1689
1690                 break;
1691         default:
1692                 return NULL;
1693         }
1694
1695         platform_device_register(pdev);
1696         return pdev;
1697 }
1698
1699 /* --------------------------------------------------------------------
1700  *  USB Device Controller
1701  * -------------------------------------------------------------------- */
1702 static struct resource usba0_resource[] __initdata = {
1703         {
1704                 .start          = 0xff300000,
1705                 .end            = 0xff3fffff,
1706                 .flags          = IORESOURCE_MEM,
1707         }, {
1708                 .start          = 0xfff03000,
1709                 .end            = 0xfff033ff,
1710                 .flags          = IORESOURCE_MEM,
1711         },
1712         IRQ(31),
1713 };
1714 static struct clk usba0_pclk = {
1715         .name           = "pclk",
1716         .parent         = &pbb_clk,
1717         .mode           = pbb_clk_mode,
1718         .get_rate       = pbb_clk_get_rate,
1719         .index          = 12,
1720 };
1721 static struct clk usba0_hclk = {
1722         .name           = "hclk",
1723         .parent         = &hsb_clk,
1724         .mode           = hsb_clk_mode,
1725         .get_rate       = hsb_clk_get_rate,
1726         .index          = 6,
1727 };
1728
1729 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1730         [idx] = {                                               \
1731                 .name           = nam,                          \
1732                 .index          = idx,                          \
1733                 .fifo_size      = maxpkt,                       \
1734                 .nr_banks       = maxbk,                        \
1735                 .can_dma        = dma,                          \
1736                 .can_isoc       = isoc,                         \
1737         }
1738
1739 static struct usba_ep_data at32_usba_ep[] __initdata = {
1740         EP("ep0",     0,   64, 1, 0, 0),
1741         EP("ep1",     1,  512, 2, 1, 1),
1742         EP("ep2",     2,  512, 2, 1, 1),
1743         EP("ep3-int", 3,   64, 3, 1, 0),
1744         EP("ep4-int", 4,   64, 3, 1, 0),
1745         EP("ep5",     5, 1024, 3, 1, 1),
1746         EP("ep6",     6, 1024, 3, 1, 1),
1747 };
1748
1749 #undef EP
1750
1751 struct platform_device *__init
1752 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1753 {
1754         /*
1755          * pdata doesn't have room for any endpoints, so we need to
1756          * append room for the ones we need right after it.
1757          */
1758         struct {
1759                 struct usba_platform_data pdata;
1760                 struct usba_ep_data ep[7];
1761         } usba_data;
1762         struct platform_device *pdev;
1763
1764         if (id != 0)
1765                 return NULL;
1766
1767         pdev = platform_device_alloc("atmel_usba_udc", 0);
1768         if (!pdev)
1769                 return NULL;
1770
1771         if (platform_device_add_resources(pdev, usba0_resource,
1772                                           ARRAY_SIZE(usba0_resource)))
1773                 goto out_free_pdev;
1774
1775         if (data) {
1776                 usba_data.pdata.vbus_pin = data->vbus_pin;
1777                 usba_data.pdata.vbus_pin_inverted = data->vbus_pin_inverted;
1778         } else {
1779                 usba_data.pdata.vbus_pin = -EINVAL;
1780                 usba_data.pdata.vbus_pin_inverted = -EINVAL;
1781         }
1782
1783         data = &usba_data.pdata;
1784         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1785         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1786
1787         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1788                 goto out_free_pdev;
1789
1790         if (gpio_is_valid(data->vbus_pin))
1791                 at32_select_gpio(data->vbus_pin, 0);
1792
1793         usba0_pclk.dev = &pdev->dev;
1794         usba0_hclk.dev = &pdev->dev;
1795
1796         platform_device_add(pdev);
1797
1798         return pdev;
1799
1800 out_free_pdev:
1801         platform_device_put(pdev);
1802         return NULL;
1803 }
1804
1805 /* --------------------------------------------------------------------
1806  * IDE / CompactFlash
1807  * -------------------------------------------------------------------- */
1808 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1809 static struct resource at32_smc_cs4_resource[] __initdata = {
1810         {
1811                 .start  = 0x04000000,
1812                 .end    = 0x07ffffff,
1813                 .flags  = IORESOURCE_MEM,
1814         },
1815         IRQ(~0UL), /* Magic IRQ will be overridden */
1816 };
1817 static struct resource at32_smc_cs5_resource[] __initdata = {
1818         {
1819                 .start  = 0x20000000,
1820                 .end    = 0x23ffffff,
1821                 .flags  = IORESOURCE_MEM,
1822         },
1823         IRQ(~0UL), /* Magic IRQ will be overridden */
1824 };
1825
1826 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1827                 unsigned int cs, unsigned int extint)
1828 {
1829         static unsigned int extint_pin_map[4] __initdata = {
1830                 (1 << 25),
1831                 (1 << 26),
1832                 (1 << 27),
1833                 (1 << 28),
1834         };
1835         static bool common_pins_initialized __initdata = false;
1836         unsigned int extint_pin;
1837         int ret;
1838         u32 pin_mask;
1839
1840         if (extint >= ARRAY_SIZE(extint_pin_map))
1841                 return -EINVAL;
1842         extint_pin = extint_pin_map[extint];
1843
1844         switch (cs) {
1845         case 4:
1846                 ret = platform_device_add_resources(pdev,
1847                                 at32_smc_cs4_resource,
1848                                 ARRAY_SIZE(at32_smc_cs4_resource));
1849                 if (ret)
1850                         return ret;
1851
1852                 /* NCS4   -> OE_N  */
1853                 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1854                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1855                 break;
1856         case 5:
1857                 ret = platform_device_add_resources(pdev,
1858                                 at32_smc_cs5_resource,
1859                                 ARRAY_SIZE(at32_smc_cs5_resource));
1860                 if (ret)
1861                         return ret;
1862
1863                 /* NCS5   -> OE_N  */
1864                 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1865                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1866                 break;
1867         default:
1868                 return -EINVAL;
1869         }
1870
1871         if (!common_pins_initialized) {
1872                 pin_mask  = (1 << 19);  /* CFCE1  -> CS0_N */
1873                 pin_mask |= (1 << 20);  /* CFCE2  -> CS1_N */
1874                 pin_mask |= (1 << 23);  /* CFRNW  -> DIR   */
1875                 pin_mask |= (1 << 24);  /* NWAIT  <- IORDY */
1876
1877                 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1878
1879                 common_pins_initialized = true;
1880         }
1881
1882         select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1883
1884         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1885         pdev->resource[1].end = pdev->resource[1].start;
1886
1887         return 0;
1888 }
1889
1890 struct platform_device *__init
1891 at32_add_device_ide(unsigned int id, unsigned int extint,
1892                     struct ide_platform_data *data)
1893 {
1894         struct platform_device *pdev;
1895
1896         pdev = platform_device_alloc("at32_ide", id);
1897         if (!pdev)
1898                 goto fail;
1899
1900         if (platform_device_add_data(pdev, data,
1901                                 sizeof(struct ide_platform_data)))
1902                 goto fail;
1903
1904         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1905                 goto fail;
1906
1907         platform_device_add(pdev);
1908         return pdev;
1909
1910 fail:
1911         platform_device_put(pdev);
1912         return NULL;
1913 }
1914
1915 struct platform_device *__init
1916 at32_add_device_cf(unsigned int id, unsigned int extint,
1917                     struct cf_platform_data *data)
1918 {
1919         struct platform_device *pdev;
1920
1921         pdev = platform_device_alloc("at32_cf", id);
1922         if (!pdev)
1923                 goto fail;
1924
1925         if (platform_device_add_data(pdev, data,
1926                                 sizeof(struct cf_platform_data)))
1927                 goto fail;
1928
1929         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1930                 goto fail;
1931
1932         if (gpio_is_valid(data->detect_pin))
1933                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1934         if (gpio_is_valid(data->reset_pin))
1935                 at32_select_gpio(data->reset_pin, 0);
1936         if (gpio_is_valid(data->vcc_pin))
1937                 at32_select_gpio(data->vcc_pin, 0);
1938         /* READY is used as extint, so we can't select it as gpio */
1939
1940         platform_device_add(pdev);
1941         return pdev;
1942
1943 fail:
1944         platform_device_put(pdev);
1945         return NULL;
1946 }
1947 #endif
1948
1949 /* --------------------------------------------------------------------
1950  * NAND Flash / SmartMedia
1951  * -------------------------------------------------------------------- */
1952 static struct resource smc_cs3_resource[] __initdata = {
1953         {
1954                 .start  = 0x0c000000,
1955                 .end    = 0x0fffffff,
1956                 .flags  = IORESOURCE_MEM,
1957         }, {
1958                 .start  = 0xfff03c00,
1959                 .end    = 0xfff03fff,
1960                 .flags  = IORESOURCE_MEM,
1961         },
1962 };
1963
1964 struct platform_device *__init
1965 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1966 {
1967         struct platform_device *pdev;
1968
1969         if (id != 0 || !data)
1970                 return NULL;
1971
1972         pdev = platform_device_alloc("atmel_nand", id);
1973         if (!pdev)
1974                 goto fail;
1975
1976         if (platform_device_add_resources(pdev, smc_cs3_resource,
1977                                 ARRAY_SIZE(smc_cs3_resource)))
1978                 goto fail;
1979
1980         if (platform_device_add_data(pdev, data,
1981                                 sizeof(struct atmel_nand_data)))
1982                 goto fail;
1983
1984         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1985         if (data->enable_pin)
1986                 at32_select_gpio(data->enable_pin,
1987                                 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1988         if (data->rdy_pin)
1989                 at32_select_gpio(data->rdy_pin, 0);
1990         if (data->det_pin)
1991                 at32_select_gpio(data->det_pin, 0);
1992
1993         platform_device_add(pdev);
1994         return pdev;
1995
1996 fail:
1997         platform_device_put(pdev);
1998         return NULL;
1999 }
2000
2001 /* --------------------------------------------------------------------
2002  * AC97C
2003  * -------------------------------------------------------------------- */
2004 static struct resource atmel_ac97c0_resource[] __initdata = {
2005         PBMEM(0xfff02800),
2006         IRQ(29),
2007 };
2008 static struct clk atmel_ac97c0_pclk = {
2009         .name           = "pclk",
2010         .parent         = &pbb_clk,
2011         .mode           = pbb_clk_mode,
2012         .get_rate       = pbb_clk_get_rate,
2013         .index          = 10,
2014 };
2015
2016 struct platform_device *__init
2017 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2018                       unsigned int flags)
2019 {
2020         struct platform_device          *pdev;
2021         struct dw_dma_slave             *rx_dws;
2022         struct dw_dma_slave             *tx_dws;
2023         struct ac97c_platform_data      _data;
2024         u32                             pin_mask;
2025
2026         if (id != 0)
2027                 return NULL;
2028
2029         pdev = platform_device_alloc("atmel_ac97c", id);
2030         if (!pdev)
2031                 return NULL;
2032
2033         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
2034                                 ARRAY_SIZE(atmel_ac97c0_resource)))
2035                 goto out_free_resources;
2036
2037         if (!data) {
2038                 data = &_data;
2039                 memset(data, 0, sizeof(struct ac97c_platform_data));
2040                 data->reset_pin = -ENODEV;
2041         }
2042
2043         rx_dws = &data->rx_dws;
2044         tx_dws = &data->tx_dws;
2045
2046         /* Check if DMA slave interface for capture should be configured. */
2047         if (flags & AC97C_CAPTURE) {
2048                 rx_dws->dma_dev = &dw_dmac0_device.dev;
2049                 rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2050                 rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
2051                 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2052                 rx_dws->src_master = 0;
2053                 rx_dws->dst_master = 1;
2054                 rx_dws->src_msize = DW_DMA_MSIZE_1;
2055                 rx_dws->dst_msize = DW_DMA_MSIZE_1;
2056                 rx_dws->fc = DW_DMA_FC_D_P2M;
2057         }
2058
2059         /* Check if DMA slave interface for playback should be configured. */
2060         if (flags & AC97C_PLAYBACK) {
2061                 tx_dws->dma_dev = &dw_dmac0_device.dev;
2062                 tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2063                 tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
2064                 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2065                 tx_dws->src_master = 0;
2066                 tx_dws->dst_master = 1;
2067                 tx_dws->src_msize = DW_DMA_MSIZE_1;
2068                 tx_dws->dst_msize = DW_DMA_MSIZE_1;
2069                 tx_dws->fc = DW_DMA_FC_D_M2P;
2070         }
2071
2072         if (platform_device_add_data(pdev, data,
2073                                 sizeof(struct ac97c_platform_data)))
2074                 goto out_free_resources;
2075
2076         /* SDO | SYNC | SCLK | SDI */
2077         pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
2078
2079         select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2080
2081         if (gpio_is_valid(data->reset_pin))
2082                 at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
2083                                 | AT32_GPIOF_HIGH);
2084
2085         atmel_ac97c0_pclk.dev = &pdev->dev;
2086
2087         platform_device_add(pdev);
2088         return pdev;
2089
2090 out_free_resources:
2091         platform_device_put(pdev);
2092         return NULL;
2093 }
2094
2095 /* --------------------------------------------------------------------
2096  * ABDAC
2097  * -------------------------------------------------------------------- */
2098 static struct resource abdac0_resource[] __initdata = {
2099         PBMEM(0xfff02000),
2100         IRQ(27),
2101 };
2102 static struct clk abdac0_pclk = {
2103         .name           = "pclk",
2104         .parent         = &pbb_clk,
2105         .mode           = pbb_clk_mode,
2106         .get_rate       = pbb_clk_get_rate,
2107         .index          = 8,
2108 };
2109 static struct clk abdac0_sample_clk = {
2110         .name           = "sample_clk",
2111         .mode           = genclk_mode,
2112         .get_rate       = genclk_get_rate,
2113         .set_rate       = genclk_set_rate,
2114         .set_parent     = genclk_set_parent,
2115         .index          = 6,
2116 };
2117
2118 struct platform_device *__init
2119 at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2120 {
2121         struct platform_device  *pdev;
2122         struct dw_dma_slave     *dws;
2123         u32                     pin_mask;
2124
2125         if (id != 0 || !data)
2126                 return NULL;
2127
2128         pdev = platform_device_alloc("atmel_abdac", id);
2129         if (!pdev)
2130                 return NULL;
2131
2132         if (platform_device_add_resources(pdev, abdac0_resource,
2133                                 ARRAY_SIZE(abdac0_resource)))
2134                 goto out_free_resources;
2135
2136         dws = &data->dws;
2137
2138         dws->dma_dev = &dw_dmac0_device.dev;
2139         dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
2140         dws->cfg_hi = DWC_CFGH_DST_PER(2);
2141         dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2142         dws->src_master = 0;
2143         dws->dst_master = 1;
2144         dws->src_msize = DW_DMA_MSIZE_1;
2145         dws->dst_msize = DW_DMA_MSIZE_1;
2146         dws->fc = DW_DMA_FC_D_M2P;
2147
2148         if (platform_device_add_data(pdev, data,
2149                                 sizeof(struct atmel_abdac_pdata)))
2150                 goto out_free_resources;
2151
2152         pin_mask  = (1 << 20) | (1 << 22);      /* DATA1 & DATAN1 */
2153         pin_mask |= (1 << 21) | (1 << 23);      /* DATA0 & DATAN0 */
2154
2155         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2156
2157         abdac0_pclk.dev = &pdev->dev;
2158         abdac0_sample_clk.dev = &pdev->dev;
2159
2160         platform_device_add(pdev);
2161         return pdev;
2162
2163 out_free_resources:
2164         platform_device_put(pdev);
2165         return NULL;
2166 }
2167
2168 /* --------------------------------------------------------------------
2169  *  GCLK
2170  * -------------------------------------------------------------------- */
2171 static struct clk gclk0 = {
2172         .name           = "gclk0",
2173         .mode           = genclk_mode,
2174         .get_rate       = genclk_get_rate,
2175         .set_rate       = genclk_set_rate,
2176         .set_parent     = genclk_set_parent,
2177         .index          = 0,
2178 };
2179 static struct clk gclk1 = {
2180         .name           = "gclk1",
2181         .mode           = genclk_mode,
2182         .get_rate       = genclk_get_rate,
2183         .set_rate       = genclk_set_rate,
2184         .set_parent     = genclk_set_parent,
2185         .index          = 1,
2186 };
2187 static struct clk gclk2 = {
2188         .name           = "gclk2",
2189         .mode           = genclk_mode,
2190         .get_rate       = genclk_get_rate,
2191         .set_rate       = genclk_set_rate,
2192         .set_parent     = genclk_set_parent,
2193         .index          = 2,
2194 };
2195 static struct clk gclk3 = {
2196         .name           = "gclk3",
2197         .mode           = genclk_mode,
2198         .get_rate       = genclk_get_rate,
2199         .set_rate       = genclk_set_rate,
2200         .set_parent     = genclk_set_parent,
2201         .index          = 3,
2202 };
2203 static struct clk gclk4 = {
2204         .name           = "gclk4",
2205         .mode           = genclk_mode,
2206         .get_rate       = genclk_get_rate,
2207         .set_rate       = genclk_set_rate,
2208         .set_parent     = genclk_set_parent,
2209         .index          = 4,
2210 };
2211
2212 static __initdata struct clk *init_clocks[] = {
2213         &osc32k,
2214         &osc0,
2215         &osc1,
2216         &pll0,
2217         &pll1,
2218         &cpu_clk,
2219         &hsb_clk,
2220         &pba_clk,
2221         &pbb_clk,
2222         &at32_pm_pclk,
2223         &at32_intc0_pclk,
2224         &at32_hmatrix_clk,
2225         &ebi_clk,
2226         &hramc_clk,
2227         &sdramc_clk,
2228         &smc0_pclk,
2229         &smc0_mck,
2230         &pdc_hclk,
2231         &pdc_pclk,
2232         &dw_dmac0_hclk,
2233         &pico_clk,
2234         &pio0_mck,
2235         &pio1_mck,
2236         &pio2_mck,
2237         &pio3_mck,
2238         &pio4_mck,
2239         &at32_tcb0_t0_clk,
2240         &at32_tcb1_t0_clk,
2241         &atmel_psif0_pclk,
2242         &atmel_psif1_pclk,
2243         &atmel_usart0_usart,
2244         &atmel_usart1_usart,
2245         &atmel_usart2_usart,
2246         &atmel_usart3_usart,
2247         &atmel_pwm0_mck,
2248 #if defined(CONFIG_CPU_AT32AP7000)
2249         &macb0_hclk,
2250         &macb0_pclk,
2251         &macb1_hclk,
2252         &macb1_pclk,
2253 #endif
2254         &atmel_spi0_spi_clk,
2255         &atmel_spi1_spi_clk,
2256         &atmel_twi0_pclk,
2257         &atmel_mci0_pclk,
2258 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2259         &atmel_lcdfb0_hck1,
2260         &atmel_lcdfb0_pixclk,
2261 #endif
2262         &ssc0_pclk,
2263         &ssc1_pclk,
2264         &ssc2_pclk,
2265         &usba0_hclk,
2266         &usba0_pclk,
2267         &atmel_ac97c0_pclk,
2268         &abdac0_pclk,
2269         &abdac0_sample_clk,
2270         &gclk0,
2271         &gclk1,
2272         &gclk2,
2273         &gclk3,
2274         &gclk4,
2275 };
2276
2277 void __init setup_platform(void)
2278 {
2279         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2280         int i;
2281
2282         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2283                 main_clock = &pll0;
2284                 cpu_clk.parent = &pll0;
2285         } else {
2286                 main_clock = &osc0;
2287                 cpu_clk.parent = &osc0;
2288         }
2289
2290         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2291                 pll0.parent = &osc1;
2292         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2293                 pll1.parent = &osc1;
2294
2295         genclk_init_parent(&gclk0);
2296         genclk_init_parent(&gclk1);
2297         genclk_init_parent(&gclk2);
2298         genclk_init_parent(&gclk3);
2299         genclk_init_parent(&gclk4);
2300 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2301         genclk_init_parent(&atmel_lcdfb0_pixclk);
2302 #endif
2303         genclk_init_parent(&abdac0_sample_clk);
2304
2305         /*
2306          * Build initial dynamic clock list by registering all clocks
2307          * from the array.
2308          * At the same time, turn on all clocks that have at least one
2309          * user already, and turn off everything else. We only do this
2310          * for module clocks, and even though it isn't particularly
2311          * pretty to  check the address of the mode function, it should
2312          * do the trick...
2313          */
2314         for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2315                 struct clk *clk = init_clocks[i];
2316
2317                 /* first, register clock */
2318                 at32_clk_register(clk);
2319
2320                 if (clk->users == 0)
2321                         continue;
2322
2323                 if (clk->mode == &cpu_clk_mode)
2324                         cpu_mask |= 1 << clk->index;
2325                 else if (clk->mode == &hsb_clk_mode)
2326                         hsb_mask |= 1 << clk->index;
2327                 else if (clk->mode == &pba_clk_mode)
2328                         pba_mask |= 1 << clk->index;
2329                 else if (clk->mode == &pbb_clk_mode)
2330                         pbb_mask |= 1 << clk->index;
2331         }
2332
2333         pm_writel(CPU_MASK, cpu_mask);
2334         pm_writel(HSB_MASK, hsb_mask);
2335         pm_writel(PBA_MASK, pba_mask);
2336         pm_writel(PBB_MASK, pbb_mask);
2337
2338         /* Initialize the port muxes */
2339         at32_init_pio(&pio0_device);
2340         at32_init_pio(&pio1_device);
2341         at32_init_pio(&pio2_device);
2342         at32_init_pio(&pio3_device);
2343         at32_init_pio(&pio4_device);
2344 }
2345
2346 struct gen_pool *sram_pool;
2347
2348 static int __init sram_init(void)
2349 {
2350         struct gen_pool *pool;
2351
2352         /* 1KiB granularity */
2353         pool = gen_pool_create(10, -1);
2354         if (!pool)
2355                 goto fail;
2356
2357         if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2358                 goto err_pool_add;
2359
2360         sram_pool = pool;
2361         return 0;
2362
2363 err_pool_add:
2364         gen_pool_destroy(pool);
2365 fail:
2366         pr_err("Failed to create SRAM pool\n");
2367         return -ENOMEM;
2368 }
2369 core_initcall(sram_init);