2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __ASM_SPINLOCK_H
17 #define __ASM_SPINLOCK_H
19 #include <asm/spinlock_types.h>
20 #include <asm/processor.h>
23 * Spinlock implementation.
25 * The old value is read exclusively and the new one, if unlocked, is written
26 * exclusively. In case of failure, the loop is restarted.
28 * The memory barriers are implicit with the load-acquire and store-release
35 #define arch_spin_is_locked(x) ((x)->lock != 0)
36 #define arch_spin_unlock_wait(lock) \
37 do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
39 #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
41 static inline void arch_spin_lock(arch_spinlock_t *lock)
50 " stxr %w0, %w2, %1\n"
52 : "=&r" (tmp), "+Q" (lock->lock)
57 static inline int arch_spin_trylock(arch_spinlock_t *lock)
64 " stxr %w0, %w2, %1\n"
67 : "=&r" (tmp), "+Q" (lock->lock)
74 static inline void arch_spin_unlock(arch_spinlock_t *lock)
78 : "=Q" (lock->lock) : "r" (0) : "memory");
82 * Write lock implementation.
84 * Write locks set bit 31. Unlocking, is done by writing 0 since the lock is
87 * The memory barriers are implicit with the load-acquire and store-release
91 static inline void arch_write_lock(arch_rwlock_t *rw)
100 " stxr %w0, %w2, %1\n"
102 : "=&r" (tmp), "+Q" (rw->lock)
107 static inline int arch_write_trylock(arch_rwlock_t *rw)
114 " stxr %w0, %w2, %1\n"
116 : "=&r" (tmp), "+Q" (rw->lock)
123 static inline void arch_write_unlock(arch_rwlock_t *rw)
127 : "=Q" (rw->lock) : "r" (0) : "memory");
130 /* write_can_lock - would write_trylock() succeed? */
131 #define arch_write_can_lock(x) ((x)->lock == 0)
134 * Read lock implementation.
136 * It exclusively loads the lock value, increments it and stores the new value
137 * back if positive and the CPU still exclusively owns the location. If the
138 * value is negative, the lock is already held.
140 * During unlocking there may be multiple active read locks but no write lock.
142 * The memory barriers are implicit with the load-acquire and store-release
145 static inline void arch_read_lock(arch_rwlock_t *rw)
147 unsigned int tmp, tmp2;
153 " add %w0, %w0, #1\n"
154 " tbnz %w0, #31, 1b\n"
155 " stxr %w1, %w0, %2\n"
157 : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
162 static inline void arch_read_unlock(arch_rwlock_t *rw)
164 unsigned int tmp, tmp2;
168 " sub %w0, %w0, #1\n"
169 " stlxr %w1, %w0, %2\n"
171 : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
176 static inline int arch_read_trylock(arch_rwlock_t *rw)
178 unsigned int tmp, tmp2 = 1;
182 " add %w0, %w0, #1\n"
183 " tbnz %w0, #31, 1f\n"
184 " stxr %w1, %w0, %2\n"
186 : "=&r" (tmp), "+r" (tmp2), "+Q" (rw->lock)
193 /* read_can_lock - would read_trylock() succeed? */
194 #define arch_read_can_lock(x) ((x)->lock < 0x80000000)
196 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
197 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
199 #define arch_spin_relax(lock) cpu_relax()
200 #define arch_read_relax(lock) cpu_relax()
201 #define arch_write_relax(lock) cpu_relax()
203 #endif /* __ASM_SPINLOCK_H */