1 /* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
3 * Copyright (c) 2007, 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2443 Clock control suport - common code
9 #include <linux/init.h>
10 #include <linux/clk.h>
13 #include <mach/regs-s3c2443-clock.h>
15 #include <plat/s3c2443.h>
16 #include <plat/clock.h>
17 #include <plat/clock-clksrc.h>
20 #include <plat/cpu-freq.h>
23 static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
25 u32 ctrlbit = clk->ctrlbit;
26 u32 con = __raw_readl(reg);
33 __raw_writel(con, reg);
37 int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
39 return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
42 int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
44 return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
47 int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
49 return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
52 /* mpllref is a direct descendant of clk_xtal by default, but it is not
53 * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
54 * such directly equating the two source clocks is impossible.
56 struct clk clk_mpllref = {
61 static struct clk *clk_epllref_sources[] = {
68 struct clksrc_clk clk_epllref = {
72 .sources = &(struct clksrc_sources) {
73 .sources = clk_epllref_sources,
74 .nr_sources = ARRAY_SIZE(clk_epllref_sources),
76 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
81 * this is sourced from either the EPLL or the EPLLref clock
84 static struct clk *clk_sysclk_sources[] = {
85 [0] = &clk_epllref.clk,
89 struct clksrc_clk clk_esysclk = {
94 .sources = &(struct clksrc_sources) {
95 .sources = clk_sysclk_sources,
96 .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
98 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
101 static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
103 unsigned long parent_rate = clk_get_rate(clk->parent);
104 unsigned long div = __raw_readl(S3C2443_CLKDIV0);
106 div &= S3C2443_CLKDIV0_EXTDIV_MASK;
107 div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
109 return parent_rate / (div + 1);
112 static struct clk clk_mdivclk = {
114 .parent = &clk_mpllref,
115 .ops = &(struct clk_ops) {
116 .get_rate = s3c2443_getrate_mdivclk,
120 static struct clk *clk_msysclk_sources[] = {
127 struct clksrc_clk clk_msysclk = {
132 .sources = &(struct clksrc_sources) {
133 .sources = clk_msysclk_sources,
134 .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
136 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
141 * this divides the msysclk down to pass to h/p/etc.
144 static unsigned long s3c2443_prediv_getrate(struct clk *clk)
146 unsigned long rate = clk_get_rate(clk->parent);
147 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
149 clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
150 clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
152 return rate / (clkdiv0 + 1);
155 static struct clk clk_prediv = {
157 .parent = &clk_msysclk.clk,
158 .ops = &(struct clk_ops) {
159 .get_rate = s3c2443_prediv_getrate,
165 * usb host bus-clock, usually 48MHz to provide USB bus clock timing
168 static struct clksrc_clk clk_usb_bus_host = {
170 .name = "usb-bus-host-parent",
171 .parent = &clk_esysclk.clk,
172 .ctrlbit = S3C2443_SCLKCON_USBHOST,
173 .enable = s3c2443_clkcon_enable_s,
175 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
178 /* common clksrc clocks */
180 static struct clksrc_clk clksrc_clks[] = {
182 /* ART baud-rate clock sourced from esysclk via a divisor */
185 .parent = &clk_esysclk.clk,
187 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
189 /* camera interface bus-clock, divided down from esysclk */
191 .name = "camif-upll", /* same as 2440 name */
192 .parent = &clk_esysclk.clk,
193 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
194 .enable = s3c2443_clkcon_enable_s,
196 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
199 .name = "display-if",
200 .parent = &clk_esysclk.clk,
201 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
202 .enable = s3c2443_clkcon_enable_s,
204 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
209 static struct clk init_clocks_off[] = {
213 .enable = s3c2443_clkcon_enable_p,
214 .ctrlbit = S3C2443_PCLKCON_ADC,
218 .enable = s3c2443_clkcon_enable_p,
219 .ctrlbit = S3C2443_PCLKCON_IIC,
223 static struct clk init_clocks[] = {
227 .enable = s3c2443_clkcon_enable_h,
228 .ctrlbit = S3C2443_HCLKCON_DMA0,
232 .enable = s3c2443_clkcon_enable_h,
233 .ctrlbit = S3C2443_HCLKCON_DMA1,
237 .enable = s3c2443_clkcon_enable_h,
238 .ctrlbit = S3C2443_HCLKCON_DMA2,
242 .enable = s3c2443_clkcon_enable_h,
243 .ctrlbit = S3C2443_HCLKCON_DMA3,
247 .enable = s3c2443_clkcon_enable_h,
248 .ctrlbit = S3C2443_HCLKCON_DMA4,
252 .enable = s3c2443_clkcon_enable_h,
253 .ctrlbit = S3C2443_HCLKCON_DMA5,
257 .enable = s3c2443_clkcon_enable_h,
258 .ctrlbit = S3C2443_HCLKCON_HSMMC,
262 .enable = s3c2443_clkcon_enable_p,
263 .ctrlbit = S3C2443_PCLKCON_GPIO,
267 .enable = s3c2443_clkcon_enable_h,
268 .ctrlbit = S3C2443_HCLKCON_USBH,
270 .name = "usb-device",
272 .enable = s3c2443_clkcon_enable_h,
273 .ctrlbit = S3C2443_HCLKCON_USBD,
277 .enable = s3c2443_clkcon_enable_h,
278 .ctrlbit = S3C2443_HCLKCON_LCDC,
283 .enable = s3c2443_clkcon_enable_p,
284 .ctrlbit = S3C2443_PCLKCON_PWMT,
288 .enable = s3c2443_clkcon_enable_h,
289 .ctrlbit = S3C2443_HCLKCON_CFC,
293 .enable = s3c2443_clkcon_enable_h,
294 .ctrlbit = S3C2443_HCLKCON_SSMC,
297 .devname = "s3c2440-uart.0",
299 .enable = s3c2443_clkcon_enable_p,
300 .ctrlbit = S3C2443_PCLKCON_UART0,
303 .devname = "s3c2440-uart.1",
305 .enable = s3c2443_clkcon_enable_p,
306 .ctrlbit = S3C2443_PCLKCON_UART1,
309 .devname = "s3c2440-uart.2",
311 .enable = s3c2443_clkcon_enable_p,
312 .ctrlbit = S3C2443_PCLKCON_UART2,
315 .devname = "s3c2440-uart.3",
317 .enable = s3c2443_clkcon_enable_p,
318 .ctrlbit = S3C2443_PCLKCON_UART3,
322 .enable = s3c2443_clkcon_enable_p,
323 .ctrlbit = S3C2443_PCLKCON_RTC,
327 .ctrlbit = S3C2443_PCLKCON_WDT,
331 .ctrlbit = S3C2443_PCLKCON_AC97,
336 .name = "usb-bus-host",
337 .parent = &clk_usb_bus_host.clk,
341 static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
343 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
348 /* EPLLCON compatible enough to get on/off information */
350 void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
353 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
354 unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
355 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
356 struct clk *xtal_clk;
364 xtal_clk = clk_get(NULL, "xtal");
365 xtal = clk_get_rate(xtal_clk);
368 pll = get_mpll(mpllcon, xtal);
369 clk_msysclk.clk.rate = pll;
371 fclk = pll / get_fdiv(clkdiv0);
372 hclk = s3c2443_prediv_getrate(&clk_prediv);
373 hclk /= s3c2443_get_hdiv(clkdiv0);
374 pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
376 s3c24xx_setup_clocks(fclk, hclk, pclk);
378 printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
379 (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
380 print_mhz(pll), print_mhz(fclk),
381 print_mhz(hclk), print_mhz(pclk));
383 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
384 s3c_set_clksrc(&clksrc_clks[ptr], true);
386 /* ensure usb bus clock is within correct rate of 48MHz */
388 if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
389 printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
390 clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
393 printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
394 (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
395 print_mhz(clk_get_rate(&clk_epll)),
396 print_mhz(clk_get_rate(&clk_usb_bus)));
399 static struct clk *clks[] __initdata = {
408 static struct clksrc_clk *clksrcs[] __initdata = {
415 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
420 /* s3c2443 parents h and p clocks from prediv */
421 clk_h.parent = &clk_prediv;
422 clk_p.parent = &clk_prediv;
424 clk_usb_bus.parent = &clk_usb_bus_host.clk;
425 clk_epll.parent = &clk_epllref.clk;
427 s3c24xx_register_baseclocks(xtal);
428 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
430 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
431 s3c_register_clksrc(clksrcs[ptr], 1);
433 s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
434 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
436 /* See s3c2443/etc notes on disabling clocks at init time */
437 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
438 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
440 s3c2443_common_setup_clocks(get_mpll, get_fdiv);