4 #define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
5 #define MX31_IRAM_SIZE SZ_16K
7 #define MX31_L2CC_BASE_ADDR 0x30000000
8 #define MX31_L2CC_SIZE SZ_1M
10 #define MX31_AIPS1_BASE_ADDR 0x43f00000
11 #define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000
12 #define MX31_AIPS1_SIZE SZ_1M
13 #define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
14 #define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
15 #define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
16 #define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
17 #define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
18 #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
19 #define MX31_I2C_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
20 #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
21 #define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
22 #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
23 #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
24 #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
25 #define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
26 #define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
27 #define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
28 #define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
29 #define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
30 #define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
31 #define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
32 #define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
33 #define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
34 #define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
36 #define MX31_SPBA0_BASE_ADDR 0x50000000
37 #define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000
38 #define MX31_SPBA0_SIZE SZ_1M
39 #define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
40 #define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
41 #define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
42 #define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
43 #define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
44 #define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
45 #define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
46 #define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
47 #define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
48 #define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
50 #define MX31_AIPS2_BASE_ADDR 0x53f00000
51 #define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000
52 #define MX31_AIPS2_SIZE SZ_1M
53 #define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
54 #define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
55 #define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
56 #define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
57 #define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
58 #define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
59 #define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
60 #define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
61 #define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
62 #define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
63 #define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
64 #define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
65 #define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
66 #define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
67 #define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
68 #define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
69 #define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
70 #define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
71 #define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
72 #define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
73 #define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
75 #define MX31_ROMP_BASE_ADDR 0x60000000
76 #define MX31_ROMP_BASE_ADDR_VIRT 0xfc500000
77 #define MX31_ROMP_SIZE SZ_1M
79 #define MX31_AVIC_BASE_ADDR 0x68000000
80 #define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000
81 #define MX31_AVIC_SIZE SZ_1M
83 #define MX31_IPU_MEM_BASE_ADDR 0x70000000
84 #define MX31_CSD0_BASE_ADDR 0x80000000
85 #define MX31_CSD1_BASE_ADDR 0x90000000
87 #define MX31_CS0_BASE_ADDR 0xa0000000
88 #define MX31_CS1_BASE_ADDR 0xa8000000
89 #define MX31_CS2_BASE_ADDR 0xb0000000
90 #define MX31_CS3_BASE_ADDR 0xb2000000
92 #define MX31_CS4_BASE_ADDR 0xb4000000
93 #define MX31_CS4_BASE_ADDR_VIRT 0xf4000000
94 #define MX31_CS4_SIZE SZ_32M
96 #define MX31_CS5_BASE_ADDR 0xb6000000
97 #define MX31_CS5_BASE_ADDR_VIRT 0xf6000000
98 #define MX31_CS5_SIZE SZ_32M
100 #define MX31_X_MEMC_BASE_ADDR 0xb8000000
101 #define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000
102 #define MX31_X_MEMC_SIZE SZ_64K
103 #define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
104 #define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
105 #define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
106 #define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
107 #define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
108 #define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
110 #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
112 #define MX31_IO_ADDRESS(x) ( \
113 IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \
114 IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \
115 IMX_IO_ADDRESS(x, MX31_AVIC) ?: \
116 IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \
117 IMX_IO_ADDRESS(x, MX31_SPBA0))
119 #define MX31_INT_I2C3 3
120 #define MX31_INT_I2C2 4
121 #define MX31_INT_MPEG4_ENCODER 5
122 #define MX31_INT_RTIC 6
123 #define MX31_INT_FIRI 7
124 #define MX31_INT_MMC_SDHC2 8
125 #define MX31_INT_MMC_SDHC1 9
126 #define MX31_INT_I2C 10
127 #define MX31_INT_SSI2 11
128 #define MX31_INT_SSI1 12
129 #define MX31_INT_CSPI2 13
130 #define MX31_INT_CSPI1 14
131 #define MX31_INT_ATA 15
132 #define MX31_INT_MBX 16
133 #define MX31_INT_CSPI3 17
134 #define MX31_INT_UART3 18
135 #define MX31_INT_IIM 19
136 #define MX31_INT_SIM2 20
137 #define MX31_INT_SIM1 21
138 #define MX31_INT_RNGA 22
139 #define MX31_INT_EVTMON 23
140 #define MX31_INT_KPP 24
141 #define MX31_INT_RTC 25
142 #define MX31_INT_PWM 26
143 #define MX31_INT_EPIT2 27
144 #define MX31_INT_EPIT1 28
145 #define MX31_INT_GPT 29
146 #define MX31_INT_POWER_FAIL 30
147 #define MX31_INT_CCM_DVFS 31
148 #define MX31_INT_UART2 32
149 #define MX31_INT_NANDFC 33
150 #define MX31_INT_SDMA 34
151 #define MX31_INT_USB1 35
152 #define MX31_INT_USB2 36
153 #define MX31_INT_USB3 37
154 #define MX31_INT_USB4 38
155 #define MX31_INT_MSHC1 39
156 #define MX31_INT_MSHC2 40
157 #define MX31_INT_IPU_ERR 41
158 #define MX31_INT_IPU_SYN 42
159 #define MX31_INT_UART1 45
160 #define MX31_INT_UART4 46
161 #define MX31_INT_UART5 47
162 #define MX31_INT_ECT 48
163 #define MX31_INT_SCC_SCM 49
164 #define MX31_INT_SCC_SMN 50
165 #define MX31_INT_GPIO2 51
166 #define MX31_INT_GPIO1 52
167 #define MX31_INT_CCM 53
168 #define MX31_INT_PCMCIA 54
169 #define MX31_INT_WDOG 55
170 #define MX31_INT_GPIO3 56
171 #define MX31_INT_EXT_POWER 58
172 #define MX31_INT_EXT_TEMPER 59
173 #define MX31_INT_EXT_SENSOR60 60
174 #define MX31_INT_EXT_SENSOR61 61
175 #define MX31_INT_EXT_WDOG 62
176 #define MX31_INT_EXT_TV 63
178 #define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
180 /* silicon revisions specific to i.MX31 */
181 #define MX31_CHIP_REV_1_0 0x10
182 #define MX31_CHIP_REV_1_1 0x11
183 #define MX31_CHIP_REV_1_2 0x12
184 #define MX31_CHIP_REV_1_3 0x13
185 #define MX31_CHIP_REV_2_0 0x20
186 #define MX31_CHIP_REV_2_1 0x21
187 #define MX31_CHIP_REV_2_2 0x22
188 #define MX31_CHIP_REV_2_3 0x23
189 #define MX31_CHIP_REV_3_0 0x30
190 #define MX31_CHIP_REV_3_1 0x31
191 #define MX31_CHIP_REV_3_2 0x32
193 #define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
194 #define MX31_SYSTEM_REV_NUM 3
196 #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
197 /* these should go away */
198 #define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
199 #define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
200 #define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
201 #define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
202 #define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
203 #define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
204 #define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
205 #define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
206 #define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
207 #define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
208 #define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
209 #define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
210 #define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
211 #define MXC_INT_FIRI MX31_INT_FIRI
212 #define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1
213 #define MXC_INT_MBX MX31_INT_MBX
214 #define MXC_INT_CSPI3 MX31_INT_CSPI3
215 #define MXC_INT_SIM2 MX31_INT_SIM2
216 #define MXC_INT_SIM1 MX31_INT_SIM1
217 #define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
218 #define MXC_INT_USB1 MX31_INT_USB1
219 #define MXC_INT_USB2 MX31_INT_USB2
220 #define MXC_INT_USB3 MX31_INT_USB3
221 #define MXC_INT_USB4 MX31_INT_USB4
222 #define MXC_INT_MSHC2 MX31_INT_MSHC2
223 #define MXC_INT_UART4 MX31_INT_UART4
224 #define MXC_INT_UART5 MX31_INT_UART5
225 #define MXC_INT_CCM MX31_INT_CCM
226 #define MXC_INT_PCMCIA MX31_INT_PCMCIA