2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sizes.h>
22 #include <asm/cputype.h>
23 #include <asm/sections.h>
24 #include <asm/cachetype.h>
25 #include <asm/setup.h>
26 #include <asm/smp_plat.h>
28 #include <asm/highmem.h>
29 #include <asm/system_info.h>
30 #include <asm/traps.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/pci.h>
40 * empty_zero_page is a special page that is used for
41 * zero-initialized data and COW.
43 struct page *empty_zero_page;
44 EXPORT_SYMBOL(empty_zero_page);
47 * The pmd table for the upper-most set of pages.
51 #define CPOLICY_UNCACHED 0
52 #define CPOLICY_BUFFERED 1
53 #define CPOLICY_WRITETHROUGH 2
54 #define CPOLICY_WRITEBACK 3
55 #define CPOLICY_WRITEALLOC 4
57 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
58 static unsigned int ecc_mask __initdata = 0;
60 pgprot_t pgprot_kernel;
61 pgprot_t pgprot_hyp_device;
63 pgprot_t pgprot_s2_device;
65 EXPORT_SYMBOL(pgprot_user);
66 EXPORT_SYMBOL(pgprot_kernel);
69 const char policy[16];
76 #ifdef CONFIG_ARM_LPAE
77 #define s2_policy(policy) policy
79 #define s2_policy(policy) 0
82 static struct cachepolicy cache_policies[] __initdata = {
86 .pmd = PMD_SECT_UNCACHED,
87 .pte = L_PTE_MT_UNCACHED,
88 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
92 .pmd = PMD_SECT_BUFFERED,
93 .pte = L_PTE_MT_BUFFERABLE,
94 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
96 .policy = "writethrough",
99 .pte = L_PTE_MT_WRITETHROUGH,
100 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
102 .policy = "writeback",
105 .pte = L_PTE_MT_WRITEBACK,
106 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
108 .policy = "writealloc",
110 .pmd = PMD_SECT_WBWA,
111 .pte = L_PTE_MT_WRITEALLOC,
112 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
116 #ifdef CONFIG_CPU_CP15
118 * These are useful for identifying cache coherency
119 * problems by allowing the cache or the cache and
120 * writebuffer to be turned off. (Note: the write
121 * buffer should not be on and the cache off).
123 static int __init early_cachepolicy(char *p)
127 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
128 int len = strlen(cache_policies[i].policy);
130 if (memcmp(p, cache_policies[i].policy, len) == 0) {
132 cr_alignment &= ~cache_policies[i].cr_mask;
133 cr_no_alignment &= ~cache_policies[i].cr_mask;
137 if (i == ARRAY_SIZE(cache_policies))
138 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
140 * This restriction is partly to do with the way we boot; it is
141 * unpredictable to have memory mapped using two different sets of
142 * memory attributes (shared, type, and cache attribs). We can not
143 * change these attributes once the initial assembly has setup the
146 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
147 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
148 cachepolicy = CPOLICY_WRITEBACK;
151 set_cr(cr_alignment);
154 early_param("cachepolicy", early_cachepolicy);
156 static int __init early_nocache(char *__unused)
158 char *p = "buffered";
159 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
160 early_cachepolicy(p);
163 early_param("nocache", early_nocache);
165 static int __init early_nowrite(char *__unused)
167 char *p = "uncached";
168 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
169 early_cachepolicy(p);
172 early_param("nowb", early_nowrite);
174 #ifndef CONFIG_ARM_LPAE
175 static int __init early_ecc(char *p)
177 if (memcmp(p, "on", 2) == 0)
178 ecc_mask = PMD_PROTECTION;
179 else if (memcmp(p, "off", 3) == 0)
183 early_param("ecc", early_ecc);
186 static int __init noalign_setup(char *__unused)
188 cr_alignment &= ~CR_A;
189 cr_no_alignment &= ~CR_A;
190 set_cr(cr_alignment);
193 __setup("noalign", noalign_setup);
196 void adjust_cr(unsigned long mask, unsigned long set)
204 local_irq_save(flags);
206 cr_no_alignment = (cr_no_alignment & ~mask) | set;
207 cr_alignment = (cr_alignment & ~mask) | set;
209 set_cr((get_cr() & ~mask) | set);
211 local_irq_restore(flags);
215 #else /* ifdef CONFIG_CPU_CP15 */
217 static int __init early_cachepolicy(char *p)
219 pr_warning("cachepolicy kernel parameter not supported without cp15\n");
221 early_param("cachepolicy", early_cachepolicy);
223 static int __init noalign_setup(char *__unused)
225 pr_warning("noalign kernel parameter not supported without cp15\n");
227 __setup("noalign", noalign_setup);
229 #endif /* ifdef CONFIG_CPU_CP15 / else */
231 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
232 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
234 static struct mem_type mem_types[] = {
235 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
236 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
238 .prot_l1 = PMD_TYPE_TABLE,
239 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
242 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
243 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
244 .prot_l1 = PMD_TYPE_TABLE,
245 .prot_sect = PROT_SECT_DEVICE,
248 [MT_DEVICE_CACHED] = { /* ioremap_cached */
249 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
250 .prot_l1 = PMD_TYPE_TABLE,
251 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
254 [MT_DEVICE_WC] = { /* ioremap_wc */
255 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
256 .prot_l1 = PMD_TYPE_TABLE,
257 .prot_sect = PROT_SECT_DEVICE,
261 .prot_pte = PROT_PTE_DEVICE,
262 .prot_l1 = PMD_TYPE_TABLE,
263 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
267 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
268 .domain = DOMAIN_KERNEL,
270 #ifndef CONFIG_ARM_LPAE
272 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
273 .domain = DOMAIN_KERNEL,
277 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
279 .prot_l1 = PMD_TYPE_TABLE,
280 .domain = DOMAIN_USER,
282 [MT_HIGH_VECTORS] = {
283 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
284 L_PTE_USER | L_PTE_RDONLY,
285 .prot_l1 = PMD_TYPE_TABLE,
286 .domain = DOMAIN_USER,
289 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
290 .prot_l1 = PMD_TYPE_TABLE,
291 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
292 .domain = DOMAIN_KERNEL,
295 .prot_sect = PMD_TYPE_SECT,
296 .domain = DOMAIN_KERNEL,
298 [MT_MEMORY_NONCACHED] = {
299 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
301 .prot_l1 = PMD_TYPE_TABLE,
302 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
303 .domain = DOMAIN_KERNEL,
306 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
308 .prot_l1 = PMD_TYPE_TABLE,
309 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
310 .domain = DOMAIN_KERNEL,
313 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
314 .prot_l1 = PMD_TYPE_TABLE,
315 .domain = DOMAIN_KERNEL,
318 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
319 L_PTE_MT_UNCACHED | L_PTE_XN,
320 .prot_l1 = PMD_TYPE_TABLE,
321 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
322 PMD_SECT_UNCACHED | PMD_SECT_XN,
323 .domain = DOMAIN_KERNEL,
325 [MT_MEMORY_DMA_READY] = {
326 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
327 .prot_l1 = PMD_TYPE_TABLE,
328 .domain = DOMAIN_KERNEL,
332 const struct mem_type *get_mem_type(unsigned int type)
334 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
336 EXPORT_SYMBOL(get_mem_type);
339 * Adjust the PMD section entries according to the CPU in use.
341 static void __init build_mem_type_table(void)
343 struct cachepolicy *cp;
344 unsigned int cr = get_cr();
345 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
346 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
347 int cpu_arch = cpu_architecture();
350 if (cpu_arch < CPU_ARCH_ARMv6) {
351 #if defined(CONFIG_CPU_DCACHE_DISABLE)
352 if (cachepolicy > CPOLICY_BUFFERED)
353 cachepolicy = CPOLICY_BUFFERED;
354 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
355 if (cachepolicy > CPOLICY_WRITETHROUGH)
356 cachepolicy = CPOLICY_WRITETHROUGH;
359 if (cpu_arch < CPU_ARCH_ARMv5) {
360 if (cachepolicy >= CPOLICY_WRITEALLOC)
361 cachepolicy = CPOLICY_WRITEBACK;
365 cachepolicy = CPOLICY_WRITEALLOC;
368 * Strip out features not present on earlier architectures.
369 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
370 * without extended page tables don't have the 'Shared' bit.
372 if (cpu_arch < CPU_ARCH_ARMv5)
373 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
374 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
375 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
376 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
377 mem_types[i].prot_sect &= ~PMD_SECT_S;
380 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
381 * "update-able on write" bit on ARM610). However, Xscale and
382 * Xscale3 require this bit to be cleared.
384 if (cpu_is_xscale() || cpu_is_xsc3()) {
385 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
386 mem_types[i].prot_sect &= ~PMD_BIT4;
387 mem_types[i].prot_l1 &= ~PMD_BIT4;
389 } else if (cpu_arch < CPU_ARCH_ARMv6) {
390 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
391 if (mem_types[i].prot_l1)
392 mem_types[i].prot_l1 |= PMD_BIT4;
393 if (mem_types[i].prot_sect)
394 mem_types[i].prot_sect |= PMD_BIT4;
399 * Mark the device areas according to the CPU/architecture.
401 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
402 if (!cpu_is_xsc3()) {
404 * Mark device regions on ARMv6+ as execute-never
405 * to prevent speculative instruction fetches.
407 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
408 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
409 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
410 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
412 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
414 * For ARMv7 with TEX remapping,
415 * - shared device is SXCB=1100
416 * - nonshared device is SXCB=0100
417 * - write combine device mem is SXCB=0001
418 * (Uncached Normal memory)
420 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
421 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
422 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
423 } else if (cpu_is_xsc3()) {
426 * - shared device is TEXCB=00101
427 * - nonshared device is TEXCB=01000
428 * - write combine device mem is TEXCB=00100
429 * (Inner/Outer Uncacheable in xsc3 parlance)
431 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
432 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
433 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
436 * For ARMv6 and ARMv7 without TEX remapping,
437 * - shared device is TEXCB=00001
438 * - nonshared device is TEXCB=01000
439 * - write combine device mem is TEXCB=00100
440 * (Uncached Normal in ARMv6 parlance).
442 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
443 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
444 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
448 * On others, write combining is "Uncached/Buffered"
450 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
454 * Now deal with the memory-type mappings
456 cp = &cache_policies[cachepolicy];
457 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
458 s2_pgprot = cp->pte_s2;
459 hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
462 * ARMv6 and above have extended page tables.
464 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
465 #ifndef CONFIG_ARM_LPAE
467 * Mark cache clean areas and XIP ROM read only
468 * from SVC mode and no access from userspace.
470 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
471 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
472 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
477 * Mark memory with the "shared" attribute
480 user_pgprot |= L_PTE_SHARED;
481 kern_pgprot |= L_PTE_SHARED;
482 vecs_pgprot |= L_PTE_SHARED;
483 s2_pgprot |= L_PTE_SHARED;
484 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
485 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
486 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
487 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
488 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
489 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
490 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
491 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
492 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
497 * Non-cacheable Normal - intended for memory areas that must
498 * not cause dirty cache line writebacks when used
500 if (cpu_arch >= CPU_ARCH_ARMv6) {
501 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
502 /* Non-cacheable Normal is XCB = 001 */
503 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
506 /* For both ARMv6 and non-TEX-remapping ARMv7 */
507 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
511 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
514 #ifdef CONFIG_ARM_LPAE
516 * Do not generate access flag faults for the kernel mappings.
518 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
519 mem_types[i].prot_pte |= PTE_EXT_AF;
520 if (mem_types[i].prot_sect)
521 mem_types[i].prot_sect |= PMD_SECT_AF;
523 kern_pgprot |= PTE_EXT_AF;
524 vecs_pgprot |= PTE_EXT_AF;
527 for (i = 0; i < 16; i++) {
528 pteval_t v = pgprot_val(protection_map[i]);
529 protection_map[i] = __pgprot(v | user_pgprot);
532 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
533 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
535 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
536 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
537 L_PTE_DIRTY | kern_pgprot);
538 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
539 pgprot_s2_device = __pgprot(s2_device_pgprot);
540 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
542 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
543 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
544 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
545 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
546 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
547 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
548 mem_types[MT_ROM].prot_sect |= cp->pmd;
552 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
556 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
559 printk("Memory policy: ECC %sabled, Data cache %s\n",
560 ecc_mask ? "en" : "dis", cp->policy);
562 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
563 struct mem_type *t = &mem_types[i];
565 t->prot_l1 |= PMD_DOMAIN(t->domain);
567 t->prot_sect |= PMD_DOMAIN(t->domain);
571 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
572 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
573 unsigned long size, pgprot_t vma_prot)
576 return pgprot_noncached(vma_prot);
577 else if (file->f_flags & O_SYNC)
578 return pgprot_writecombine(vma_prot);
581 EXPORT_SYMBOL(phys_mem_access_prot);
584 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
586 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
588 void *ptr = __va(memblock_alloc(sz, align));
593 static void __init *early_alloc(unsigned long sz)
595 return early_alloc_aligned(sz, sz);
598 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
600 if (pmd_none(*pmd)) {
601 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
602 __pmd_populate(pmd, __pa(pte), prot);
604 BUG_ON(pmd_bad(*pmd));
605 return pte_offset_kernel(pmd, addr);
608 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
609 unsigned long end, unsigned long pfn,
610 const struct mem_type *type)
612 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
614 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
616 } while (pte++, addr += PAGE_SIZE, addr != end);
619 static void __init map_init_section(pmd_t *pmd, unsigned long addr,
620 unsigned long end, phys_addr_t phys,
621 const struct mem_type *type)
623 #ifndef CONFIG_ARM_LPAE
625 * In classic MMU format, puds and pmds are folded in to
626 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
627 * group of L1 entries making up one logical pointer to
628 * an L2 table (2MB), where as PMDs refer to the individual
629 * L1 entries (1MB). Hence increment to get the correct
630 * offset for odd 1MB sections.
631 * (See arch/arm/include/asm/pgtable-2level.h)
633 if (addr & SECTION_SIZE)
637 *pmd = __pmd(phys | type->prot_sect);
638 phys += SECTION_SIZE;
639 } while (pmd++, addr += SECTION_SIZE, addr != end);
641 flush_pmd_entry(pmd);
644 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
645 unsigned long end, phys_addr_t phys,
646 const struct mem_type *type)
648 pmd_t *pmd = pmd_offset(pud, addr);
653 * With LPAE, we must loop over to map
654 * all the pmds for the given range.
656 next = pmd_addr_end(addr, end);
659 * Try a section mapping - addr, next and phys must all be
660 * aligned to a section boundary.
662 if (type->prot_sect &&
663 ((addr | next | phys) & ~SECTION_MASK) == 0) {
664 map_init_section(pmd, addr, next, phys, type);
666 alloc_init_pte(pmd, addr, next,
667 __phys_to_pfn(phys), type);
672 } while (pmd++, addr = next, addr != end);
675 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
676 unsigned long end, phys_addr_t phys,
677 const struct mem_type *type)
679 pud_t *pud = pud_offset(pgd, addr);
683 next = pud_addr_end(addr, end);
684 alloc_init_pmd(pud, addr, next, phys, type);
686 } while (pud++, addr = next, addr != end);
689 #ifndef CONFIG_ARM_LPAE
690 static void __init create_36bit_mapping(struct map_desc *md,
691 const struct mem_type *type)
693 unsigned long addr, length, end;
698 phys = __pfn_to_phys(md->pfn);
699 length = PAGE_ALIGN(md->length);
701 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
702 printk(KERN_ERR "MM: CPU does not support supersection "
703 "mapping for 0x%08llx at 0x%08lx\n",
704 (long long)__pfn_to_phys((u64)md->pfn), addr);
708 /* N.B. ARMv6 supersections are only defined to work with domain 0.
709 * Since domain assignments can in fact be arbitrary, the
710 * 'domain == 0' check below is required to insure that ARMv6
711 * supersections are only allocated for domain 0 regardless
712 * of the actual domain assignments in use.
715 printk(KERN_ERR "MM: invalid domain in supersection "
716 "mapping for 0x%08llx at 0x%08lx\n",
717 (long long)__pfn_to_phys((u64)md->pfn), addr);
721 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
722 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
723 " at 0x%08lx invalid alignment\n",
724 (long long)__pfn_to_phys((u64)md->pfn), addr);
729 * Shift bits [35:32] of address into bits [23:20] of PMD
732 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
734 pgd = pgd_offset_k(addr);
737 pud_t *pud = pud_offset(pgd, addr);
738 pmd_t *pmd = pmd_offset(pud, addr);
741 for (i = 0; i < 16; i++)
742 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
744 addr += SUPERSECTION_SIZE;
745 phys += SUPERSECTION_SIZE;
746 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
747 } while (addr != end);
749 #endif /* !CONFIG_ARM_LPAE */
752 * Create the page directory entries and any necessary
753 * page tables for the mapping specified by `md'. We
754 * are able to cope here with varying sizes and address
755 * offsets, and we take full advantage of sections and
758 static void __init create_mapping(struct map_desc *md)
760 unsigned long addr, length, end;
762 const struct mem_type *type;
765 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
766 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
767 " at 0x%08lx in user region\n",
768 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
772 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
773 md->virtual >= PAGE_OFFSET &&
774 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
775 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
776 " at 0x%08lx out of vmalloc space\n",
777 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
780 type = &mem_types[md->type];
782 #ifndef CONFIG_ARM_LPAE
784 * Catch 36-bit addresses
786 if (md->pfn >= 0x100000) {
787 create_36bit_mapping(md, type);
792 addr = md->virtual & PAGE_MASK;
793 phys = __pfn_to_phys(md->pfn);
794 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
796 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
797 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
798 "be mapped using pages, ignoring.\n",
799 (long long)__pfn_to_phys(md->pfn), addr);
803 pgd = pgd_offset_k(addr);
806 unsigned long next = pgd_addr_end(addr, end);
808 alloc_init_pud(pgd, addr, next, phys, type);
812 } while (pgd++, addr != end);
816 * Create the architecture specific mappings
818 void __init iotable_init(struct map_desc *io_desc, int nr)
821 struct vm_struct *vm;
822 struct static_vm *svm;
827 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
829 for (md = io_desc; nr; md++, nr--) {
833 vm->addr = (void *)(md->virtual & PAGE_MASK);
834 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
835 vm->phys_addr = __pfn_to_phys(md->pfn);
836 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
837 vm->flags |= VM_ARM_MTYPE(md->type);
838 vm->caller = iotable_init;
839 add_static_vm_early(svm++);
843 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
846 struct vm_struct *vm;
847 struct static_vm *svm;
849 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
852 vm->addr = (void *)addr;
854 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
856 add_static_vm_early(svm);
859 #ifndef CONFIG_ARM_LPAE
862 * The Linux PMD is made of two consecutive section entries covering 2MB
863 * (see definition in include/asm/pgtable-2level.h). However a call to
864 * create_mapping() may optimize static mappings by using individual
865 * 1MB section mappings. This leaves the actual PMD potentially half
866 * initialized if the top or bottom section entry isn't used, leaving it
867 * open to problems if a subsequent ioremap() or vmalloc() tries to use
868 * the virtual space left free by that unused section entry.
870 * Let's avoid the issue by inserting dummy vm entries covering the unused
871 * PMD halves once the static mappings are in place.
874 static void __init pmd_empty_section_gap(unsigned long addr)
876 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
879 static void __init fill_pmd_gaps(void)
881 struct static_vm *svm;
882 struct vm_struct *vm;
883 unsigned long addr, next = 0;
886 list_for_each_entry(svm, &static_vmlist, list) {
888 addr = (unsigned long)vm->addr;
893 * Check if this vm starts on an odd section boundary.
894 * If so and the first section entry for this PMD is free
895 * then we block the corresponding virtual address.
897 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
898 pmd = pmd_off_k(addr);
900 pmd_empty_section_gap(addr & PMD_MASK);
904 * Then check if this vm ends on an odd section boundary.
905 * If so and the second section entry for this PMD is empty
906 * then we block the corresponding virtual address.
909 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
910 pmd = pmd_off_k(addr) + 1;
912 pmd_empty_section_gap(addr);
915 /* no need to look at any vm entry until we hit the next PMD */
916 next = (addr + PMD_SIZE - 1) & PMD_MASK;
921 #define fill_pmd_gaps() do { } while (0)
924 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
925 static void __init pci_reserve_io(void)
927 struct static_vm *svm;
929 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
933 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
936 #define pci_reserve_io() do { } while (0)
939 #ifdef CONFIG_DEBUG_LL
940 void __init debug_ll_io_init(void)
944 debug_ll_addr(&map.pfn, &map.virtual);
945 if (!map.pfn || !map.virtual)
947 map.pfn = __phys_to_pfn(map.pfn);
948 map.virtual &= PAGE_MASK;
949 map.length = PAGE_SIZE;
950 map.type = MT_DEVICE;
951 create_mapping(&map);
955 static void * __initdata vmalloc_min =
956 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
959 * vmalloc=size forces the vmalloc area to be exactly 'size'
960 * bytes. This can be used to increase (or decrease) the vmalloc
961 * area - the default is 240m.
963 static int __init early_vmalloc(char *arg)
965 unsigned long vmalloc_reserve = memparse(arg, NULL);
967 if (vmalloc_reserve < SZ_16M) {
968 vmalloc_reserve = SZ_16M;
970 "vmalloc area too small, limiting to %luMB\n",
971 vmalloc_reserve >> 20);
974 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
975 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
977 "vmalloc area is too big, limiting to %luMB\n",
978 vmalloc_reserve >> 20);
981 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
984 early_param("vmalloc", early_vmalloc);
986 phys_addr_t arm_lowmem_limit __initdata = 0;
988 void __init sanity_check_meminfo(void)
990 int i, j, highmem = 0;
991 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
993 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
994 struct membank *bank = &meminfo.bank[j];
995 *bank = meminfo.bank[i];
997 if (bank->start >= vmalloc_limit)
1000 bank->highmem = highmem;
1002 #ifdef CONFIG_HIGHMEM
1004 * Split those memory banks which are partially overlapping
1005 * the vmalloc area greatly simplifying things later.
1007 if (!highmem && bank->start < vmalloc_limit &&
1008 bank->size > vmalloc_limit - bank->start) {
1009 if (meminfo.nr_banks >= NR_BANKS) {
1010 printk(KERN_CRIT "NR_BANKS too low, "
1011 "ignoring high memory\n");
1013 memmove(bank + 1, bank,
1014 (meminfo.nr_banks - i) * sizeof(*bank));
1017 bank[1].size -= vmalloc_limit - bank->start;
1018 bank[1].start = vmalloc_limit;
1019 bank[1].highmem = highmem = 1;
1022 bank->size = vmalloc_limit - bank->start;
1026 * Highmem banks not allowed with !CONFIG_HIGHMEM.
1029 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1030 "(!CONFIG_HIGHMEM).\n",
1031 (unsigned long long)bank->start,
1032 (unsigned long long)bank->start + bank->size - 1);
1037 * Check whether this memory bank would partially overlap
1040 if (bank->start + bank->size > vmalloc_limit)
1041 unsigned long newsize = vmalloc_limit - bank->start;
1042 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1043 "to -%.8llx (vmalloc region overlap).\n",
1044 (unsigned long long)bank->start,
1045 (unsigned long long)bank->start + bank->size - 1,
1046 (unsigned long long)bank->start + newsize - 1);
1047 bank->size = newsize;
1050 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
1051 arm_lowmem_limit = bank->start + bank->size;
1055 #ifdef CONFIG_HIGHMEM
1057 const char *reason = NULL;
1059 if (cache_is_vipt_aliasing()) {
1061 * Interactions between kmap and other mappings
1062 * make highmem support with aliasing VIPT caches
1065 reason = "with VIPT aliasing cache";
1068 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1070 while (j > 0 && meminfo.bank[j - 1].highmem)
1075 meminfo.nr_banks = j;
1076 high_memory = __va(arm_lowmem_limit - 1) + 1;
1077 memblock_set_current_limit(arm_lowmem_limit);
1080 static inline void prepare_page_table(void)
1086 * Clear out all the mappings below the kernel image.
1088 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1089 pmd_clear(pmd_off_k(addr));
1091 #ifdef CONFIG_XIP_KERNEL
1092 /* The XIP kernel is mapped in the module area -- skip over it */
1093 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1095 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1096 pmd_clear(pmd_off_k(addr));
1099 * Find the end of the first block of lowmem.
1101 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1102 if (end >= arm_lowmem_limit)
1103 end = arm_lowmem_limit;
1106 * Clear out all the kernel space mappings, except for the first
1107 * memory bank, up to the vmalloc region.
1109 for (addr = __phys_to_virt(end);
1110 addr < VMALLOC_START; addr += PMD_SIZE)
1111 pmd_clear(pmd_off_k(addr));
1114 #ifdef CONFIG_ARM_LPAE
1115 /* the first page is reserved for pgd */
1116 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1117 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1119 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1123 * Reserve the special regions of memory
1125 void __init arm_mm_memblock_reserve(void)
1128 * Reserve the page tables. These are already in use,
1129 * and can only be in node 0.
1131 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1133 #ifdef CONFIG_SA1111
1135 * Because of the SA1111 DMA bug, we want to preserve our
1136 * precious DMA-able memory...
1138 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1143 * Set up the device mappings. Since we clear out the page tables for all
1144 * mappings above VMALLOC_START, we will remove any debug device mappings.
1145 * This means you have to be careful how you debug this function, or any
1146 * called function. This means you can't use any function or debugging
1147 * method which may touch any device, otherwise the kernel _will_ crash.
1149 static void __init devicemaps_init(struct machine_desc *mdesc)
1151 struct map_desc map;
1156 * Allocate the vector page early.
1158 vectors = early_alloc(PAGE_SIZE);
1160 early_trap_init(vectors);
1162 for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1163 pmd_clear(pmd_off_k(addr));
1166 * Map the kernel if it is XIP.
1167 * It is always first in the modulearea.
1169 #ifdef CONFIG_XIP_KERNEL
1170 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1171 map.virtual = MODULES_VADDR;
1172 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1174 create_mapping(&map);
1178 * Map the cache flushing regions.
1181 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1182 map.virtual = FLUSH_BASE;
1184 map.type = MT_CACHECLEAN;
1185 create_mapping(&map);
1187 #ifdef FLUSH_BASE_MINICACHE
1188 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1189 map.virtual = FLUSH_BASE_MINICACHE;
1191 map.type = MT_MINICLEAN;
1192 create_mapping(&map);
1196 * Create a mapping for the machine vectors at the high-vectors
1197 * location (0xffff0000). If we aren't using high-vectors, also
1198 * create a mapping at the low-vectors virtual address.
1200 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1201 map.virtual = 0xffff0000;
1202 map.length = PAGE_SIZE;
1203 map.type = MT_HIGH_VECTORS;
1204 create_mapping(&map);
1206 if (!vectors_high()) {
1208 map.type = MT_LOW_VECTORS;
1209 create_mapping(&map);
1213 * Ask the machine support to map in the statically mapped devices.
1219 /* Reserve fixed i/o space in VMALLOC region */
1223 * Finally flush the caches and tlb to ensure that we're in a
1224 * consistent state wrt the writebuffer. This also ensures that
1225 * any write-allocated cache lines in the vector page are written
1226 * back. After this point, we can start to touch devices again.
1228 local_flush_tlb_all();
1232 static void __init kmap_init(void)
1234 #ifdef CONFIG_HIGHMEM
1235 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1236 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1240 static void __init map_lowmem(void)
1242 struct memblock_region *reg;
1244 /* Map all the lowmem memory banks. */
1245 for_each_memblock(memory, reg) {
1246 phys_addr_t start = reg->base;
1247 phys_addr_t end = start + reg->size;
1248 struct map_desc map;
1250 if (end > arm_lowmem_limit)
1251 end = arm_lowmem_limit;
1255 map.pfn = __phys_to_pfn(start);
1256 map.virtual = __phys_to_virt(start);
1257 map.length = end - start;
1258 map.type = MT_MEMORY;
1260 create_mapping(&map);
1265 * paging_init() sets up the page tables, initialises the zone memory
1266 * maps, and sets up the zero page, bad page and bad page tables.
1268 void __init paging_init(struct machine_desc *mdesc)
1272 memblock_set_current_limit(arm_lowmem_limit);
1274 build_mem_type_table();
1275 prepare_page_table();
1277 dma_contiguous_remap();
1278 devicemaps_init(mdesc);
1282 top_pmd = pmd_off_k(0xffff0000);
1284 /* allocate the zero page. */
1285 zero_page = early_alloc(PAGE_SIZE);
1289 empty_zero_page = virt_to_page(zero_page);
1290 __flush_dcache_page(NULL, empty_zero_page);