Pileus Git - ~andy/linux/blob - arch/arm/mach-ux500/board-mop500-pins.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * License terms: GNU General Public License (GPL) version 2
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/init.h>
   9 #include <linux/bug.h>
  10 #include <linux/string.h>
  11 #include <linux/pinctrl/machine.h>
  12 #include <linux/platform_data/pinctrl-nomadik.h>
  13
  14 #include <asm/mach-types.h>
  15
  16 #include <mach/hardware.h>
  17
  18 #include "pins-db8500.h"
  19 #include "board-mop500.h"
  20
  21 enum custom_pin_cfg_t {
  22         PINS_FOR_DEFAULT,
  23         PINS_FOR_U9500,
  24 };
  25
  26 static enum custom_pin_cfg_t pinsfor;
  27
  28 /* These simply sets bias for pins */
  29 #define BIAS(a,b) static unsigned long a[] = { b }
  30
  31 BIAS(pd, PIN_PULL_DOWN);
  32 BIAS(in_nopull, PIN_INPUT_NOPULL);
  33 BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
  34 BIAS(in_pu, PIN_INPUT_PULLUP);
  35 BIAS(in_pd, PIN_INPUT_PULLDOWN);
  36 BIAS(out_hi, PIN_OUTPUT_HIGH);
  37 BIAS(out_lo, PIN_OUTPUT_LOW);
  38 BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
  39 /* These also force them into GPIO mode */
  40 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
  41 BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
  42 BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
  43 BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
  44 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
  45 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
  46 /* Sleep modes */
  47 BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|
  48         PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
  49 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  50         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  51 BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  52         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  53 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
  54         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
  55 BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|
  56         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
  57 BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  58         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  59 BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
  60         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  61 BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  62         PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  63 BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
  64         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
  65 BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  66         PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  67 BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW|
  68         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  69 BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
  70         PIN_SLPM_PDIS_ENABLED);
  71 BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
  72         PIN_SLPM_PDIS_DISABLED);
  73 BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
  74         PIN_SLPM_PDIS_DISABLED);
  75
  76 /* We use these to define hog settings that are always done on boot */
  77 #define DB8500_MUX_HOG(group,func) \
  78         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
  79 #define DB8500_PIN_HOG(pin,conf) \
  80         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
  81 #define DB8500_PIN_SLEEP(pin, conf, dev) \
  82         PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
  83                             pin, conf)
  84
  85 /* These are default states associated with device and changed runtime */
  86 #define DB8500_MUX(group,func,dev) \
  87         PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
  88 #define DB8500_PIN(pin,conf,dev) \
  89         PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
  90 #define DB8500_PIN_IDLE(pin, conf, dev) \
  91         PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500",  \
  92                             pin, conf)
  93 #define DB8500_PIN_SLEEP(pin, conf, dev) \
  94         PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
  95                             pin, conf)
  96 #define DB8500_MUX_STATE(group, func, dev, state) \
  97         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
  98 #define DB8500_PIN_STATE(pin, conf, dev, state) \
  99         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
 100
 101 /* Pin control settings */
 102 static struct pinctrl_map __initdata mop500_family_pinmap[] = {
 103         /*
 104          * uMSP0, mux in 4 pins, regular placement of RX/TX
 105          * explicitly set the pins to no pull
 106          */
 107         DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
 108         DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
 109         DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
 110         DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
 111         DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
 112         DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
 113         /* MSP2 for HDMI, pull down TXD, TCK, TFS  */
 114         DB8500_MUX_HOG("msp2_a_1", "msp2"),
 115         DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
 116         DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
 117         DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
 118         DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
 119         /*
 120          * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
 121          * pull-up
 122          * TODO: is this really correct? Snowball doesn't have a LCD.
 123          */
 124         DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
 125         DB8500_PIN_HOG("GPIO68_E1", in_pu),
 126         DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
 127         /*
 128          * STMPE1601/tc35893 keypad IRQ GPIO 218
 129          * TODO: set for snowball and HREF really??
 130          */
 131         DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
 132         /*
 133          * UART0, we do not mux in u0 here.
 134          * uart-0 pins gpio configuration should be kept intact to prevent
 135          * a glitch in tx line when the tty dev is opened. Later these pins
 136          * are configured by uart driver
 137          */
 138         DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
 139         DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
 140         DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
 141         DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
 142         /*
 143          * Mux in UART2 on altfunction C and set pull-ups.
 144          * TODO: is this used on U8500 variants and Snowball really?
 145          * The setting on GPIO31 conflicts with magnetometer use on hrefv60
 146          */
 147         /* default state for UART2 */
 148         DB8500_MUX("u2rxtx_c_1", "u2", "uart2"),
 149         DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */
 150         DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */
 151         /* Sleep state for UART2 */
 152         DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"),
 153         DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"),
 154         /*
 155          * The following pin sets were known as "runtime pins" before being
 156          * converted to the pinctrl model. Here we model them as "default"
 157          * states.
 158          */
 159         /* Mux in UART0 after initialization */
 160         DB8500_MUX("u0_a_1", "u0", "uart0"),
 161         DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
 162         DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
 163         DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
 164         DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
 165         /* Sleep state for UART0 */
 166         DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
 167         DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
 168         DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
 169         DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
 170         /* Mux in UART1 after initialization */
 171         DB8500_MUX("u1rxtx_a_1", "u1", "uart1"),
 172         DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */
 173         DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */
 174         /* Sleep state for UART1 */
 175         DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
 176         DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
 177         /* MSP1 for ALSA codec */
 178         DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
 179         DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
 180         DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"),
 181         DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
 182         DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
 183         DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
 184         /* MSP1 sleep state */
 185         DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"),
 186         DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
 187         DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
 188         DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
 189         /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
 190         DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
 191         DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
 192         /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
 193         DB8500_MUX("lcdvsi1_a_1", "lcd", "0-0070"),
 194         DB8500_PIN("GPIO69_E2", in_pu, "0-0070"),
 195         /* LCD VSI1 sleep state */
 196         DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"),
 197         /* Mux in i2c0 block, default state */
 198         DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
 199         /* i2c0 sleep state */
 200         DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
 201         DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
 202         /* Mux in i2c1 block, default state  */
 203         DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
 204         /* i2c1 sleep state */
 205         DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
 206         DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
 207         /* Mux in i2c2 block, default state  */
 208         DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
 209         /* i2c2 sleep state */
 210         DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
 211         DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
 212         /* Mux in i2c3 block, default state  */
 213         DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
 214         /* i2c3 sleep state */
 215         DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
 216         DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
 217         /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
 218         DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
 219         DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
 220         DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
 221         DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
 222         DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
 223         DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
 224         DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
 225         DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
 226         DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
 227         DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
 228         DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
 229         /* SDI0 sleep state */
 230         DB8500_PIN_SLEEP("GPIO18_AC2", slpm_out_hi_wkup_pdis, "sdi0"),
 231         DB8500_PIN_SLEEP("GPIO19_AC1", slpm_out_hi_wkup_pdis, "sdi0"),
 232         DB8500_PIN_SLEEP("GPIO20_AB4", slpm_out_hi_wkup_pdis, "sdi0"),
 233         DB8500_PIN_SLEEP("GPIO22_AA3", slpm_in_wkup_pdis, "sdi0"),
 234         DB8500_PIN_SLEEP("GPIO23_AA4", slpm_out_lo_wkup_pdis, "sdi0"),
 235         DB8500_PIN_SLEEP("GPIO24_AB2", slpm_in_wkup_pdis, "sdi0"),
 236         DB8500_PIN_SLEEP("GPIO25_Y4", slpm_in_wkup_pdis, "sdi0"),
 237         DB8500_PIN_SLEEP("GPIO26_Y2", slpm_in_wkup_pdis, "sdi0"),
 238         DB8500_PIN_SLEEP("GPIO27_AA2", slpm_in_wkup_pdis, "sdi0"),
 239         DB8500_PIN_SLEEP("GPIO28_AA1", slpm_in_wkup_pdis, "sdi0"),
 240
 241         /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
 242         DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
 243         DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
 244         DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
 245         DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
 246         DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
 247         DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
 248         DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
 249         DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
 250         /* SDI1 sleep state */
 251         DB8500_PIN_SLEEP("GPIO208_AH16", slpm_out_lo_wkup_pdis, "sdi1"), /* CLK */
 252         DB8500_PIN_SLEEP("GPIO209_AG15", slpm_in_wkup_pdis, "sdi1"), /* FBCLK */
 253         DB8500_PIN_SLEEP("GPIO210_AJ15", slpm_in_wkup_pdis, "sdi1"), /* CMD */
 254         DB8500_PIN_SLEEP("GPIO211_AG14", slpm_in_wkup_pdis, "sdi1"), /* DAT0 */
 255         DB8500_PIN_SLEEP("GPIO212_AF13", slpm_in_wkup_pdis, "sdi1"), /* DAT1 */
 256         DB8500_PIN_SLEEP("GPIO213_AG13", slpm_in_wkup_pdis, "sdi1"), /* DAT2 */
 257         DB8500_PIN_SLEEP("GPIO214_AH15", slpm_in_wkup_pdis, "sdi1"), /* DAT3 */
 258
 259         /* Mux in SDI2 (here called MC2) used for for PoP eMMC */
 260         DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
 261         DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
 262         DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
 263         DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
 264         DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
 265         DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
 266         DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
 267         DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
 268         DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
 269         DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
 270         DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
 271         DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
 272         /* SDI2 sleep state */
 273         DB8500_PIN_SLEEP("GPIO128_A5", out_lo_wkup_pdis, "sdi2"), /* CLK */
 274         DB8500_PIN_SLEEP("GPIO129_B4", in_wkup_pdis_en, "sdi2"), /* CMD */
 275         DB8500_PIN_SLEEP("GPIO130_C8", in_wkup_pdis_en, "sdi2"), /* FBCLK */
 276         DB8500_PIN_SLEEP("GPIO131_A12", in_wkup_pdis, "sdi2"), /* DAT0 */
 277         DB8500_PIN_SLEEP("GPIO132_C10", in_wkup_pdis, "sdi2"), /* DAT1 */
 278         DB8500_PIN_SLEEP("GPIO133_B10", in_wkup_pdis, "sdi2"), /* DAT2 */
 279         DB8500_PIN_SLEEP("GPIO134_B9", in_wkup_pdis, "sdi2"), /* DAT3 */
 280         DB8500_PIN_SLEEP("GPIO135_A9", in_wkup_pdis, "sdi2"), /* DAT4 */
 281         DB8500_PIN_SLEEP("GPIO136_C7", in_wkup_pdis, "sdi2"), /* DAT5 */
 282         DB8500_PIN_SLEEP("GPIO137_A7", in_wkup_pdis, "sdi2"), /* DAT6 */
 283         DB8500_PIN_SLEEP("GPIO138_C5", in_wkup_pdis, "sdi2"), /* DAT7 */
 284
 285         /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
 286         DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
 287         DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
 288         DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
 289         DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
 290         DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
 291         DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
 292         DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
 293         DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
 294         DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
 295         DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
 296         DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
 297         DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
 298         /*SDI4 sleep state */
 299         DB8500_PIN_SLEEP("GPIO197_AH24", slpm_in_wkup_pdis, "sdi4"), /* DAT3 */
 300         DB8500_PIN_SLEEP("GPIO198_AG25", slpm_in_wkup_pdis, "sdi4"), /* DAT2 */
 301         DB8500_PIN_SLEEP("GPIO199_AH23", slpm_in_wkup_pdis, "sdi4"), /* DAT1 */
 302         DB8500_PIN_SLEEP("GPIO200_AH26", slpm_in_wkup_pdis, "sdi4"), /* DAT0 */
 303         DB8500_PIN_SLEEP("GPIO201_AF24", slpm_in_wkup_pdis, "sdi4"), /* CMD */
 304         DB8500_PIN_SLEEP("GPIO202_AF25", slpm_in_wkup_pdis, "sdi4"), /* FBCLK */
 305         DB8500_PIN_SLEEP("GPIO203_AE23", slpm_out_lo_wkup_pdis, "sdi4"), /* CLK */
 306         DB8500_PIN_SLEEP("GPIO204_AF23", slpm_in_wkup_pdis, "sdi4"), /* DAT7 */
 307         DB8500_PIN_SLEEP("GPIO205_AG23", slpm_in_wkup_pdis, "sdi4"), /* DAT6 */
 308         DB8500_PIN_SLEEP("GPIO206_AG24", slpm_in_wkup_pdis, "sdi4"), /* DAT5 */
 309         DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
 310
 311         /* Mux in USB pins, drive STP high */
 312         DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
 313         DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
 314         /* Mux in SPI2 pins on the "other C1" altfunction */
 315         DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
 316         DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
 317         DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
 318         DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
 319         DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
 320         /* SPI2 idle state */
 321         DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
 322         DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
 323         DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
 324         /* SPI2 sleep state */
 325         DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
 326         DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
 327         DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
 328         DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
 329
 330         /* ske default state */
 331         DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
 332         DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */
 333         DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */
 334         DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */
 335         DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */
 336         DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */
 337         DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */
 338         DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */
 339         DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */
 340         DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
 341         DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
 342         DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
 343         DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
 344         DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
 345         DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
 346         DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
 347         DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
 348         /* ske sleep state */
 349         DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
 350         DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
 351         DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
 352         DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
 353         DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
 354         DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
 355         DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
 356         DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
 357         DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
 358         DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
 359         DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
 360         DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
 361         DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
 362         DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
 363         DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
 364         DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
 365
 366         /* STM APE pins states */
 367         DB8500_MUX_STATE("stmape_c_1", "stmape",
 368                 "stm", "ape_mipi34"),
 369         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 370                 "stm", "ape_mipi34"), /* clk */
 371         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 372                 "stm", "ape_mipi34"), /* dat3 */
 373         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 374                 "stm", "ape_mipi34"), /* dat2 */
 375         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 376                 "stm", "ape_mipi34"), /* dat1 */
 377         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 378                 "stm", "ape_mipi34"), /* dat0 */
 379
 380         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 381                 "stm", "ape_mipi34_sleep"), /* clk */
 382         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 383                 "stm", "ape_mipi34_sleep"), /* dat3 */
 384         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 385                 "stm", "ape_mipi34_sleep"), /* dat2 */
 386         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 387                 "stm", "ape_mipi34_sleep"), /* dat1 */
 388         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 389                 "stm", "ape_mipi34_sleep"), /* dat0 */
 390
 391         DB8500_MUX_STATE("stmape_oc1_1", "stmape",
 392                 "stm", "ape_microsd"),
 393         DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
 394                 "stm", "ape_microsd"), /* clk */
 395         DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
 396                 "stm", "ape_microsd"), /* dat0 */
 397         DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
 398                 "stm", "ape_microsd"), /* dat1 */
 399         DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
 400                 "stm", "ape_microsd"), /* dat2 */
 401         DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
 402                 "stm", "ape_microsd"), /* dat3 */
 403
 404         DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
 405                 "stm", "ape_microsd_sleep"), /* clk */
 406         DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
 407                 "stm", "ape_microsd_sleep"), /* dat0 */
 408         DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
 409                 "stm", "ape_microsd_sleep"), /* dat1 */
 410         DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
 411                 "stm", "ape_microsd_sleep"), /* dat2 */
 412         DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
 413                 "stm", "ape_microsd_sleep"), /* dat3 */
 414
 415         /*  STM Modem pins states */
 416         DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
 417                 "stm", "mod_mipi34"),
 418         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 419                 "stm", "mod_mipi34"),
 420         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 421                 "stm", "mod_mipi34"),
 422         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 423                 "stm", "mod_mipi34"), /* clk */
 424         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 425                 "stm", "mod_mipi34"), /* dat3 */
 426         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 427                 "stm", "mod_mipi34"), /* dat2 */
 428         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 429                 "stm", "mod_mipi34"), /* dat1 */
 430         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 431                 "stm", "mod_mipi34"), /* dat0 */
 432         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 433                 "stm", "mod_mipi34"), /* uartmod rx */
 434         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 435                 "stm", "mod_mipi34"), /* uartmod tx */
 436
 437         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 438                 "stm", "mod_mipi34_sleep"), /* clk */
 439         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 440                 "stm", "mod_mipi34_sleep"), /* dat3 */
 441         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 442                 "stm", "mod_mipi34_sleep"), /* dat2 */
 443         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 444                 "stm", "mod_mipi34_sleep"), /* dat1 */
 445         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 446                 "stm", "mod_mipi34_sleep"), /* dat0 */
 447         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 448                 "stm", "mod_mipi34_sleep"), /* uartmod rx */
 449         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 450                 "stm", "mod_mipi34_sleep"), /* uartmod tx */
 451
 452         DB8500_MUX_STATE("stmmod_b_1", "stmmod",
 453                 "stm", "mod_microsd"),
 454         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 455                 "stm", "mod_microsd"),
 456         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 457                 "stm", "mod_microsd"),
 458         DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
 459                 "stm", "mod_microsd"), /* clk */
 460         DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
 461                 "stm", "mod_microsd"), /* dat0 */
 462         DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
 463                 "stm", "mod_microsd"), /* dat1 */
 464         DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
 465                 "stm", "mod_microsd"), /* dat2 */
 466         DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
 467                 "stm", "mod_microsd"), /* dat3 */
 468         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 469                 "stm", "mod_microsd"), /* uartmod rx */
 470         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 471                 "stm", "mod_microsd"), /* uartmod tx */
 472
 473         DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
 474                 "stm", "mod_microsd_sleep"), /* clk */
 475         DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
 476                 "stm", "mod_microsd_sleep"), /* dat0 */
 477         DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
 478                 "stm", "mod_microsd_sleep"), /* dat1 */
 479         DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
 480                 "stm", "mod_microsd_sleep"), /* dat2 */
 481         DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
 482                 "stm", "mod_microsd_sleep"), /* dat3 */
 483         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 484                 "stm", "mod_microsd_sleep"), /* uartmod rx */
 485         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 486                 "stm", "mod_microsd_sleep"), /* uartmod tx */
 487
 488         /*  STM dual Modem/APE pins state */
 489         DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
 490                 "stm", "mod_mipi34_ape_mipi60"),
 491         DB8500_MUX_STATE("stmape_c_2", "stmape",
 492                 "stm", "mod_mipi34_ape_mipi60"),
 493         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 494                 "stm", "mod_mipi34_ape_mipi60"),
 495         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 496                 "stm", "mod_mipi34_ape_mipi60"),
 497         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 498                 "stm", "mod_mipi34_ape_mipi60"), /* clk */
 499         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 500                 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
 501         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 502                 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
 503         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 504                 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
 505         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 506                 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
 507         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 508                 "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */
 509         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 510                 "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */
 511         DB8500_PIN_STATE("GPIO155_C19", in_nopull,
 512                 "stm", "mod_mipi34_ape_mipi60"), /* clk */
 513         DB8500_PIN_STATE("GPIO156_C17", in_nopull,
 514                 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
 515         DB8500_PIN_STATE("GPIO157_A18", in_nopull,
 516                 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
 517         DB8500_PIN_STATE("GPIO158_C18", in_nopull,
 518                 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
 519         DB8500_PIN_STATE("GPIO159_B19", in_nopull,
 520                 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
 521
 522         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 523                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
 524         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 525                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
 526         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 527                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
 528         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 529                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
 530         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 531                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
 532         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 533                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */
 534         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 535                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */
 536         DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis,
 537                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
 538         DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis,
 539                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
 540         DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis,
 541                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
 542         DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis,
 543                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
 544         DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis,
 545                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
 546 };
 547
 548 /*
 549  * These are specifically for the MOP500 and HREFP (pre-v60) version of the
 550  * board, which utilized a TC35892 GPIO expander instead of using a lot of
 551  * on-chip pins as the HREFv60 and later does.
 552  */
 553 static struct pinctrl_map __initdata mop500_pinmap[] = {
 554         /* Mux in SSP0, pull down RXD pin */
 555         DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
 556         DB8500_PIN_HOG("GPIO145_C13", pd),
 557         /*
 558          * XENON Flashgun on image processor GPIO (controlled from image
 559          * processor firmware), mux in these image processor GPIO lines 0
 560          * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
 561          * the pins.
 562          */
 563         DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
 564         DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
 565         DB8500_PIN_HOG("GPIO6_AF6", in_pu),
 566         DB8500_PIN_HOG("GPIO7_AG5", in_pu),
 567         /* TC35892 IRQ, pull up the line, let the driver mux in the pin */
 568         DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
 569         /* Mux in UART1 and set the pull-ups */
 570         DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
 571         DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
 572         DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
 573         /*
 574          * Runtime stuff: make it possible to mux in the SKE keypad
 575          * and bias the pins
 576          */
 577         /* ske default state */
 578         DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
 579         DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */
 580         DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */
 581         DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */
 582         DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */
 583         DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */
 584         DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */
 585         DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */
 586         DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */
 587         DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
 588         DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
 589         DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
 590         DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
 591         DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
 592         DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
 593         DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
 594         DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
 595         /* ske sleep state */
 596         DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
 597         DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
 598         DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
 599         DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
 600         DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
 601         DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
 602         DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
 603         DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
 604         DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
 605         DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
 606         DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
 607         DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
 608         DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
 609         DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
 610         DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
 611         DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
 612
 613         /* Mux in and drive the SDI0 DAT31DIR line high at runtime */
 614         DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
 615         DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
 616 };
 617
 618 /*
 619  * The HREFv60 series of platforms is using available pins on the DB8500
 620  * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
 621  * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
 622  */
 623 static struct pinctrl_map __initdata hrefv60_pinmap[] = {
 624         /* Drive WLAN_ENA low */
 625         DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
 626         /*
 627          * XENON Flashgun on image processor GPIO (controlled from image
 628          * processor firmware), mux in these image processor GPIO lines 0
 629          * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
 630          * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
 631          * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
 632          */
 633         DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
 634         DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
 635         DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
 636         DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
 637         DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
 638         DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
 639         DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
 640         /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
 641         DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
 642         DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
 643         /*
 644          * Display Interface 1 uses GPIO 65 for RST (reset).
 645          * Display Interface 2 uses GPIO 66 for RST (reset).
 646          * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
 647          */
 648         DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
 649         DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
 650         /*
 651          * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
 652          * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
 653          * reset signals low.
 654          */
 655         DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
 656         DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
 657         DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
 658         /*
 659          * Drive D19-D23 for the ETM PTM trace interface low,
 660          * (presumably pins are unconnected therefore grounded here,
 661          * the "other alt C1" setting enables these pins)
 662          */
 663         DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
 664         DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
 665         DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
 666         DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
 667         DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
 668         /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
 669         DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
 670         DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
 671         /* NFC ENA and RESET to low, pulldown IRQ line */
 672         DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
 673         DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
 674         DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
 675         /*
 676          * SKE keyboard partly on alt A and partly on "Other alt C1"
 677          * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
 678          * rows of 6 keys, then pull up force sensing interrup and
 679          * drive reset and force sensing WU low.
 680          */
 681         DB8500_MUX_HOG("kp_a_1", "kp"),
 682         DB8500_MUX_HOG("kp_oc1_1", "kp"),
 683         DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
 684         DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
 685         DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
 686         DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
 687         DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
 688         DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
 689         DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
 690         DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
 691         DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
 692         DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
 693         DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
 694         /* DiPro Sensor interrupt */
 695         DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
 696         /* Audio Amplifier HF enable */
 697         DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
 698         /* GBF interface, pull low to reset state */
 699         DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
 700         /* MSP : HDTV INTERFACE GPIO line */
 701         DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
 702         /* Accelerometer interrupt lines */
 703         DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
 704         DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
 705         /* SD card detect GPIO pin */
 706         DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
 707         /*
 708          * Runtime stuff
 709          * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
 710          * etc.
 711          */
 712         DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
 713         DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
 714         DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
 715 };
 716
 717 static struct pinctrl_map __initdata u9500_pinmap[] = {
 718         /* Mux in UART1 (just RX/TX) and set the pull-ups */
 719         DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
 720         DB8500_PIN_HOG("GPIO4_AH6", in_pu),
 721         DB8500_PIN_HOG("GPIO5_AG6", out_hi),
 722         /* WLAN_IRQ line */
 723         DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
 724         /* HSI */
 725         DB8500_MUX_HOG("hsir_a_1", "hsi"),
 726         DB8500_MUX_HOG("hsit_a_2", "hsi"),
 727         DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
 728         DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
 729         DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
 730         DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
 731         DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
 732         DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
 733         DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
 734         DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
 735 };
 736
 737 static struct pinctrl_map __initdata u8500_pinmap[] = {
 738         DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
 739         DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
 740 };
 741
 742 static struct pinctrl_map __initdata snowball_pinmap[] = {
 743         /* Mux in SSP0 connected to AB8500, pull down RXD pin */
 744         DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
 745         DB8500_PIN_HOG("GPIO145_C13", pd),
 746         /* Always drive the MC0 DAT31DIR line high on these boards */
 747         DB8500_PIN_HOG("GPIO21_AB3", out_hi),
 748         /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
 749         DB8500_MUX_HOG("sm_b_1", "sm"),
 750         /* Drive RSTn_LAN high */
 751         DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
 752         /*  Accelerometer/Magnetometer */
 753         DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
 754         DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
 755         DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
 756         /* WLAN/GBF */
 757         DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
 758         DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
 759         DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
 760         DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
 761 };
 762
 763 /*
 764  * passing "pinsfor=" in kernel cmdline allows for custom
 765  * configuration of GPIOs on u8500 derived boards.
 766  */
 767 static int __init early_pinsfor(char *p)
 768 {
 769         pinsfor = PINS_FOR_DEFAULT;
 770
 771         if (strcmp(p, "u9500-21") == 0)
 772                 pinsfor = PINS_FOR_U9500;
 773
 774         return 0;
 775 }
 776 early_param("pinsfor", early_pinsfor);
 777
 778 int pins_for_u9500(void)
 779 {
 780         if (pinsfor == PINS_FOR_U9500)
 781                 return 1;
 782
 783         return 0;
 784 }
 785
 786 static void __init mop500_href_family_pinmaps_init(void)
 787 {
 788         switch (pinsfor) {
 789         case PINS_FOR_U9500:
 790                 pinctrl_register_mappings(u9500_pinmap,
 791                                           ARRAY_SIZE(u9500_pinmap));
 792                 break;
 793         case PINS_FOR_DEFAULT:
 794                 pinctrl_register_mappings(u8500_pinmap,
 795                                           ARRAY_SIZE(u8500_pinmap));
 796         default:
 797                 break;
 798         }
 799 }
 800
 801 void __init mop500_pinmaps_init(void)
 802 {
 803         pinctrl_register_mappings(mop500_family_pinmap,
 804                                   ARRAY_SIZE(mop500_family_pinmap));
 805         pinctrl_register_mappings(mop500_pinmap,
 806                                   ARRAY_SIZE(mop500_pinmap));
 807         mop500_href_family_pinmaps_init();
 808 }
 809
 810 void __init snowball_pinmaps_init(void)
 811 {
 812         pinctrl_register_mappings(mop500_family_pinmap,
 813                                   ARRAY_SIZE(mop500_family_pinmap));
 814         pinctrl_register_mappings(snowball_pinmap,
 815                                   ARRAY_SIZE(snowball_pinmap));
 816         pinctrl_register_mappings(u8500_pinmap,
 817                                   ARRAY_SIZE(u8500_pinmap));
 818 }
 819
 820 void __init hrefv60_pinmaps_init(void)
 821 {
 822         pinctrl_register_mappings(mop500_family_pinmap,
 823                                   ARRAY_SIZE(mop500_family_pinmap));
 824         pinctrl_register_mappings(hrefv60_pinmap,
 825                                   ARRAY_SIZE(hrefv60_pinmap));
 826         mop500_href_family_pinmaps_init();
 827 }