Pileus Git - ~andy/linux/blob - arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2010 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/amba/serial.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/gpio.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/mtd/nand.h>
  27 #include <linux/mtd/fsmc.h>
  28 #include <linux/pinctrl/machine.h>
  29 #include <linux/pinctrl/consumer.h>
  30 #include <linux/pinctrl/pinconf-generic.h>
  31 #include <linux/dma-mapping.h>
  32
  33 #include <asm/types.h>
  34 #include <asm/setup.h>
  35 #include <asm/memory.h>
  36 #include <asm/hardware/vic.h>
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/irq.h>
  39
  40 #include <mach/coh901318.h>
  41 #include <mach/hardware.h>
  42 #include <mach/syscon.h>
  43 #include <mach/dma_channels.h>
  44 #include <mach/gpio-u300.h>
  45
  46 #include "clock.h"
  47 #include "mmc.h"
  48 #include "spi.h"
  49 #include "i2c.h"
  50
  51 /*
  52  * Static I/O mappings that are needed for booting the U300 platforms. The
  53  * only things we need are the areas where we find the timer, syscon and
  54  * intcon, since the remaining device drivers will map their own memory
  55  * physical to virtual as the need arise.
  56  */
  57 static struct map_desc u300_io_desc[] __initdata = {
  58         {
  59                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  60                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  61                 .length         = SZ_64K,
  62                 .type           = MT_DEVICE,
  63         },
  64         {
  65                 .virtual        = U300_AHB_PER_VIRT_BASE,
  66                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  67                 .length         = SZ_32K,
  68                 .type           = MT_DEVICE,
  69         },
  70         {
  71                 .virtual        = U300_FAST_PER_VIRT_BASE,
  72                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  73                 .length         = SZ_32K,
  74                 .type           = MT_DEVICE,
  75         },
  76 };
  77
  78 void __init u300_map_io(void)
  79 {
  80         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  81         /* We enable a real big DMA buffer if need be. */
  82         init_consistent_dma_size(SZ_4M);
  83 }
  84
  85 /*
  86  * Declaration of devices found on the U300 board and
  87  * their respective memory locations.
  88  */
  89
  90 static struct amba_pl011_data uart0_plat_data = {
  91 #ifdef CONFIG_COH901318
  92         .dma_filter = coh901318_filter_id,
  93         .dma_rx_param = (void *) U300_DMA_UART0_RX,
  94         .dma_tx_param = (void *) U300_DMA_UART0_TX,
  95 #endif
  96 };
  97
  98 /* Slow device at 0x3000 offset */
  99 static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
 100         { IRQ_U300_UART0 }, &uart0_plat_data);
 101
 102 /* The U335 have an additional UART1 on the APP CPU */
 103 #ifdef CONFIG_MACH_U300_BS335
 104 static struct amba_pl011_data uart1_plat_data = {
 105 #ifdef CONFIG_COH901318
 106         .dma_filter = coh901318_filter_id,
 107         .dma_rx_param = (void *) U300_DMA_UART1_RX,
 108         .dma_tx_param = (void *) U300_DMA_UART1_TX,
 109 #endif
 110 };
 111
 112 /* Fast device at 0x7000 offset */
 113 static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
 114         { IRQ_U300_UART1 }, &uart1_plat_data);
 115 #endif
 116
 117 /* AHB device at 0x4000 offset */
 118 static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
 119
 120
 121 /*
 122  * Everything within this next ifdef deals with external devices connected to
 123  * the APP SPI bus.
 124  */
 125 /* Fast device at 0x6000 offset */
 126 static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
 127         { IRQ_U300_SPI }, NULL);
 128
 129 /* Fast device at 0x1000 offset */
 130 #define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
 131
 132 static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
 133         U300_MMCSD_IRQS, NULL);
 134
 135 /*
 136  * The order of device declaration may be important, since some devices
 137  * have dependencies on other devices being initialized first.
 138  */
 139 static struct amba_device *amba_devs[] __initdata = {
 140         &uart0_device,
 141 #ifdef CONFIG_MACH_U300_BS335
 142         &uart1_device,
 143 #endif
 144         &pl022_device,
 145         &pl172_device,
 146         &mmcsd_device,
 147 };
 148
 149 /* Here follows a list of all hw resources that the platform devices
 150  * allocate. Note, clock dependencies are not included
 151  */
 152
 153 static struct resource gpio_resources[] = {
 154         {
 155                 .start = U300_GPIO_BASE,
 156                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 157                 .flags = IORESOURCE_MEM,
 158         },
 159         {
 160                 .name  = "gpio0",
 161                 .start = IRQ_U300_GPIO_PORT0,
 162                 .end   = IRQ_U300_GPIO_PORT0,
 163                 .flags = IORESOURCE_IRQ,
 164         },
 165         {
 166                 .name  = "gpio1",
 167                 .start = IRQ_U300_GPIO_PORT1,
 168                 .end   = IRQ_U300_GPIO_PORT1,
 169                 .flags = IORESOURCE_IRQ,
 170         },
 171         {
 172                 .name  = "gpio2",
 173                 .start = IRQ_U300_GPIO_PORT2,
 174                 .end   = IRQ_U300_GPIO_PORT2,
 175                 .flags = IORESOURCE_IRQ,
 176         },
 177 #if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
 178         {
 179                 .name  = "gpio3",
 180                 .start = IRQ_U300_GPIO_PORT3,
 181                 .end   = IRQ_U300_GPIO_PORT3,
 182                 .flags = IORESOURCE_IRQ,
 183         },
 184         {
 185                 .name  = "gpio4",
 186                 .start = IRQ_U300_GPIO_PORT4,
 187                 .end   = IRQ_U300_GPIO_PORT4,
 188                 .flags = IORESOURCE_IRQ,
 189         },
 190 #endif
 191 #ifdef CONFIG_MACH_U300_BS335
 192         {
 193                 .name  = "gpio5",
 194                 .start = IRQ_U300_GPIO_PORT5,
 195                 .end   = IRQ_U300_GPIO_PORT5,
 196                 .flags = IORESOURCE_IRQ,
 197         },
 198         {
 199                 .name  = "gpio6",
 200                 .start = IRQ_U300_GPIO_PORT6,
 201                 .end   = IRQ_U300_GPIO_PORT6,
 202                 .flags = IORESOURCE_IRQ,
 203         },
 204 #endif /* CONFIG_MACH_U300_BS335 */
 205 };
 206
 207 static struct resource keypad_resources[] = {
 208         {
 209                 .start = U300_KEYPAD_BASE,
 210                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 211                 .flags = IORESOURCE_MEM,
 212         },
 213         {
 214                 .name  = "coh901461-press",
 215                 .start = IRQ_U300_KEYPAD_KEYBF,
 216                 .end   = IRQ_U300_KEYPAD_KEYBF,
 217                 .flags = IORESOURCE_IRQ,
 218         },
 219         {
 220                 .name  = "coh901461-release",
 221                 .start = IRQ_U300_KEYPAD_KEYBR,
 222                 .end   = IRQ_U300_KEYPAD_KEYBR,
 223                 .flags = IORESOURCE_IRQ,
 224         },
 225 };
 226
 227 static struct resource rtc_resources[] = {
 228         {
 229                 .start = U300_RTC_BASE,
 230                 .end   = U300_RTC_BASE + SZ_4K - 1,
 231                 .flags = IORESOURCE_MEM,
 232         },
 233         {
 234                 .start = IRQ_U300_RTC,
 235                 .end   = IRQ_U300_RTC,
 236                 .flags = IORESOURCE_IRQ,
 237         },
 238 };
 239
 240 /*
 241  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 242  * but these are not yet used by the driver.
 243  */
 244 static struct resource fsmc_resources[] = {
 245         {
 246                 .name  = "nand_data",
 247                 .start = U300_NAND_CS0_PHYS_BASE,
 248                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
 249                 .flags = IORESOURCE_MEM,
 250         },
 251         {
 252                 .name  = "fsmc_regs",
 253                 .start = U300_NAND_IF_PHYS_BASE,
 254                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 255                 .flags = IORESOURCE_MEM,
 256         },
 257 };
 258
 259 static struct resource i2c0_resources[] = {
 260         {
 261                 .start = U300_I2C0_BASE,
 262                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 263                 .flags = IORESOURCE_MEM,
 264         },
 265         {
 266                 .start = IRQ_U300_I2C0,
 267                 .end   = IRQ_U300_I2C0,
 268                 .flags = IORESOURCE_IRQ,
 269         },
 270 };
 271
 272 static struct resource i2c1_resources[] = {
 273         {
 274                 .start = U300_I2C1_BASE,
 275                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 276                 .flags = IORESOURCE_MEM,
 277         },
 278         {
 279                 .start = IRQ_U300_I2C1,
 280                 .end   = IRQ_U300_I2C1,
 281                 .flags = IORESOURCE_IRQ,
 282         },
 283
 284 };
 285
 286 static struct resource wdog_resources[] = {
 287         {
 288                 .start = U300_WDOG_BASE,
 289                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 290                 .flags = IORESOURCE_MEM,
 291         },
 292         {
 293                 .start = IRQ_U300_WDOG,
 294                 .end   = IRQ_U300_WDOG,
 295                 .flags = IORESOURCE_IRQ,
 296         }
 297 };
 298
 299 static struct resource dma_resource[] = {
 300         {
 301                 .start = U300_DMAC_BASE,
 302                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 303                 .flags =  IORESOURCE_MEM,
 304         },
 305         {
 306                 .start = IRQ_U300_DMA,
 307                 .end = IRQ_U300_DMA,
 308                 .flags =  IORESOURCE_IRQ,
 309         }
 310 };
 311
 312 #ifdef CONFIG_MACH_U300_BS335
 313 /* points out all dma slave channels.
 314  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 315  * Select all channels from A to B, end of list is marked with -1,-1
 316  */
 317 static int dma_slave_channels[] = {
 318         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 319         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 320
 321 /* points out all dma memcpy channels. */
 322 static int dma_memcpy_channels[] = {
 323         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 324
 325 #else /* CONFIG_MACH_U300_BS335 */
 326
 327 static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
 328 static int dma_memcpy_channels[] = {
 329         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
 330
 331 #endif
 332
 333 /** register dma for memory access
 334  *
 335  * active  1 means dma intends to access memory
 336  *         0 means dma wont access memory
 337  */
 338 static void coh901318_access_memory_state(struct device *dev, bool active)
 339 {
 340 }
 341
 342 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 343                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 344                         COH901318_CX_CFG_LCR_DISABLE | \
 345                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 346                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 347 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 348                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 349                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 350                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 351                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 352                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 353                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 354                         COH901318_CX_CTRL_TCP_DISABLE | \
 355                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 356                         COH901318_CX_CTRL_HSP_DISABLE | \
 357                         COH901318_CX_CTRL_HSS_DISABLE | \
 358                         COH901318_CX_CTRL_DDMA_LEGACY | \
 359                         COH901318_CX_CTRL_PRDD_SOURCE)
 360 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 361                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 362                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 363                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 364                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 365                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 366                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 367                         COH901318_CX_CTRL_TCP_DISABLE | \
 368                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 369                         COH901318_CX_CTRL_HSP_DISABLE | \
 370                         COH901318_CX_CTRL_HSS_DISABLE | \
 371                         COH901318_CX_CTRL_DDMA_LEGACY | \
 372                         COH901318_CX_CTRL_PRDD_SOURCE)
 373 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 374                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 375                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 376                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 377                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 378                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 379                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 380                         COH901318_CX_CTRL_TCP_DISABLE | \
 381                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 382                         COH901318_CX_CTRL_HSP_DISABLE | \
 383                         COH901318_CX_CTRL_HSS_DISABLE | \
 384                         COH901318_CX_CTRL_DDMA_LEGACY | \
 385                         COH901318_CX_CTRL_PRDD_SOURCE)
 386
 387 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 388         {
 389                 .number = U300_DMA_MSL_TX_0,
 390                 .name = "MSL TX 0",
 391                 .priority_high = 0,
 392                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 393         },
 394         {
 395                 .number = U300_DMA_MSL_TX_1,
 396                 .name = "MSL TX 1",
 397                 .priority_high = 0,
 398                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 399                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 400                                 COH901318_CX_CFG_LCR_DISABLE |
 401                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 402                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 403                 .param.ctrl_lli_chained = 0 |
 404                                 COH901318_CX_CTRL_TC_ENABLE |
 405                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 406                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 407                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 408                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 409                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 410                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 411                                 COH901318_CX_CTRL_TCP_DISABLE |
 412                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 413                                 COH901318_CX_CTRL_HSP_ENABLE |
 414                                 COH901318_CX_CTRL_HSS_DISABLE |
 415                                 COH901318_CX_CTRL_DDMA_LEGACY |
 416                                 COH901318_CX_CTRL_PRDD_SOURCE,
 417                 .param.ctrl_lli = 0 |
 418                                 COH901318_CX_CTRL_TC_ENABLE |
 419                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 420                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 421                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 422                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 423                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 424                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 425                                 COH901318_CX_CTRL_TCP_ENABLE |
 426                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 427                                 COH901318_CX_CTRL_HSP_ENABLE |
 428                                 COH901318_CX_CTRL_HSS_DISABLE |
 429                                 COH901318_CX_CTRL_DDMA_LEGACY |
 430                                 COH901318_CX_CTRL_PRDD_SOURCE,
 431                 .param.ctrl_lli_last = 0 |
 432                                 COH901318_CX_CTRL_TC_ENABLE |
 433                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 434                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 435                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 436                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 437                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 438                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 439                                 COH901318_CX_CTRL_TCP_ENABLE |
 440                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 441                                 COH901318_CX_CTRL_HSP_ENABLE |
 442                                 COH901318_CX_CTRL_HSS_DISABLE |
 443                                 COH901318_CX_CTRL_DDMA_LEGACY |
 444                                 COH901318_CX_CTRL_PRDD_SOURCE,
 445         },
 446         {
 447                 .number = U300_DMA_MSL_TX_2,
 448                 .name = "MSL TX 2",
 449                 .priority_high = 0,
 450                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 451                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 452                                 COH901318_CX_CFG_LCR_DISABLE |
 453                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 454                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 455                 .param.ctrl_lli_chained = 0 |
 456                                 COH901318_CX_CTRL_TC_ENABLE |
 457                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 458                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 459                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 460                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 461                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 462                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 463                                 COH901318_CX_CTRL_TCP_DISABLE |
 464                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 465                                 COH901318_CX_CTRL_HSP_ENABLE |
 466                                 COH901318_CX_CTRL_HSS_DISABLE |
 467                                 COH901318_CX_CTRL_DDMA_LEGACY |
 468                                 COH901318_CX_CTRL_PRDD_SOURCE,
 469                 .param.ctrl_lli = 0 |
 470                                 COH901318_CX_CTRL_TC_ENABLE |
 471                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 472                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 473                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 474                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 475                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 476                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 477                                 COH901318_CX_CTRL_TCP_ENABLE |
 478                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 479                                 COH901318_CX_CTRL_HSP_ENABLE |
 480                                 COH901318_CX_CTRL_HSS_DISABLE |
 481                                 COH901318_CX_CTRL_DDMA_LEGACY |
 482                                 COH901318_CX_CTRL_PRDD_SOURCE,
 483                 .param.ctrl_lli_last = 0 |
 484                                 COH901318_CX_CTRL_TC_ENABLE |
 485                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 486                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 487                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 488                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 489                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 490                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 491                                 COH901318_CX_CTRL_TCP_ENABLE |
 492                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 493                                 COH901318_CX_CTRL_HSP_ENABLE |
 494                                 COH901318_CX_CTRL_HSS_DISABLE |
 495                                 COH901318_CX_CTRL_DDMA_LEGACY |
 496                                 COH901318_CX_CTRL_PRDD_SOURCE,
 497                 .desc_nbr_max = 10,
 498         },
 499         {
 500                 .number = U300_DMA_MSL_TX_3,
 501                 .name = "MSL TX 3",
 502                 .priority_high = 0,
 503                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 504                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 505                                 COH901318_CX_CFG_LCR_DISABLE |
 506                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 507                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 508                 .param.ctrl_lli_chained = 0 |
 509                                 COH901318_CX_CTRL_TC_ENABLE |
 510                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 511                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 512                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 513                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 514                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 515                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 516                                 COH901318_CX_CTRL_TCP_DISABLE |
 517                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 518                                 COH901318_CX_CTRL_HSP_ENABLE |
 519                                 COH901318_CX_CTRL_HSS_DISABLE |
 520                                 COH901318_CX_CTRL_DDMA_LEGACY |
 521                                 COH901318_CX_CTRL_PRDD_SOURCE,
 522                 .param.ctrl_lli = 0 |
 523                                 COH901318_CX_CTRL_TC_ENABLE |
 524                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 525                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 526                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 527                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 528                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 529                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 530                                 COH901318_CX_CTRL_TCP_ENABLE |
 531                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 532                                 COH901318_CX_CTRL_HSP_ENABLE |
 533                                 COH901318_CX_CTRL_HSS_DISABLE |
 534                                 COH901318_CX_CTRL_DDMA_LEGACY |
 535                                 COH901318_CX_CTRL_PRDD_SOURCE,
 536                 .param.ctrl_lli_last = 0 |
 537                                 COH901318_CX_CTRL_TC_ENABLE |
 538                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 539                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 540                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 541                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 542                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 543                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 544                                 COH901318_CX_CTRL_TCP_ENABLE |
 545                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 546                                 COH901318_CX_CTRL_HSP_ENABLE |
 547                                 COH901318_CX_CTRL_HSS_DISABLE |
 548                                 COH901318_CX_CTRL_DDMA_LEGACY |
 549                                 COH901318_CX_CTRL_PRDD_SOURCE,
 550         },
 551         {
 552                 .number = U300_DMA_MSL_TX_4,
 553                 .name = "MSL TX 4",
 554                 .priority_high = 0,
 555                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 556                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 557                                 COH901318_CX_CFG_LCR_DISABLE |
 558                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 559                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 560                 .param.ctrl_lli_chained = 0 |
 561                                 COH901318_CX_CTRL_TC_ENABLE |
 562                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 563                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 564                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 565                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 566                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 567                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 568                                 COH901318_CX_CTRL_TCP_DISABLE |
 569                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 570                                 COH901318_CX_CTRL_HSP_ENABLE |
 571                                 COH901318_CX_CTRL_HSS_DISABLE |
 572                                 COH901318_CX_CTRL_DDMA_LEGACY |
 573                                 COH901318_CX_CTRL_PRDD_SOURCE,
 574                 .param.ctrl_lli = 0 |
 575                                 COH901318_CX_CTRL_TC_ENABLE |
 576                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 577                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 578                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 579                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 580                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 581                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 582                                 COH901318_CX_CTRL_TCP_ENABLE |
 583                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 584                                 COH901318_CX_CTRL_HSP_ENABLE |
 585                                 COH901318_CX_CTRL_HSS_DISABLE |
 586                                 COH901318_CX_CTRL_DDMA_LEGACY |
 587                                 COH901318_CX_CTRL_PRDD_SOURCE,
 588                 .param.ctrl_lli_last = 0 |
 589                                 COH901318_CX_CTRL_TC_ENABLE |
 590                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 591                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 592                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 593                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 594                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 595                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 596                                 COH901318_CX_CTRL_TCP_ENABLE |
 597                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 598                                 COH901318_CX_CTRL_HSP_ENABLE |
 599                                 COH901318_CX_CTRL_HSS_DISABLE |
 600                                 COH901318_CX_CTRL_DDMA_LEGACY |
 601                                 COH901318_CX_CTRL_PRDD_SOURCE,
 602         },
 603         {
 604                 .number = U300_DMA_MSL_TX_5,
 605                 .name = "MSL TX 5",
 606                 .priority_high = 0,
 607                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 608         },
 609         {
 610                 .number = U300_DMA_MSL_TX_6,
 611                 .name = "MSL TX 6",
 612                 .priority_high = 0,
 613                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 614         },
 615         {
 616                 .number = U300_DMA_MSL_RX_0,
 617                 .name = "MSL RX 0",
 618                 .priority_high = 0,
 619                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 620         },
 621         {
 622                 .number = U300_DMA_MSL_RX_1,
 623                 .name = "MSL RX 1",
 624                 .priority_high = 0,
 625                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 626                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 627                                 COH901318_CX_CFG_LCR_DISABLE |
 628                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 629                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 630                 .param.ctrl_lli_chained = 0 |
 631                                 COH901318_CX_CTRL_TC_ENABLE |
 632                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 633                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 634                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 635                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 636                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 637                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 638                                 COH901318_CX_CTRL_TCP_DISABLE |
 639                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 640                                 COH901318_CX_CTRL_HSP_ENABLE |
 641                                 COH901318_CX_CTRL_HSS_DISABLE |
 642                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 643                                 COH901318_CX_CTRL_PRDD_DEST,
 644                 .param.ctrl_lli = 0,
 645                 .param.ctrl_lli_last = 0 |
 646                                 COH901318_CX_CTRL_TC_ENABLE |
 647                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 648                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 649                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 650                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 651                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 652                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 653                                 COH901318_CX_CTRL_TCP_DISABLE |
 654                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 655                                 COH901318_CX_CTRL_HSP_ENABLE |
 656                                 COH901318_CX_CTRL_HSS_DISABLE |
 657                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 658                                 COH901318_CX_CTRL_PRDD_DEST,
 659         },
 660         {
 661                 .number = U300_DMA_MSL_RX_2,
 662                 .name = "MSL RX 2",
 663                 .priority_high = 0,
 664                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 665                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 666                                 COH901318_CX_CFG_LCR_DISABLE |
 667                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 668                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 669                 .param.ctrl_lli_chained = 0 |
 670                                 COH901318_CX_CTRL_TC_ENABLE |
 671                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 672                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 673                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 674                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 675                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 676                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 677                                 COH901318_CX_CTRL_TCP_DISABLE |
 678                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 679                                 COH901318_CX_CTRL_HSP_ENABLE |
 680                                 COH901318_CX_CTRL_HSS_DISABLE |
 681                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 682                                 COH901318_CX_CTRL_PRDD_DEST,
 683                 .param.ctrl_lli = 0 |
 684                                 COH901318_CX_CTRL_TC_ENABLE |
 685                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 686                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 687                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 688                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 689                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 690                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 691                                 COH901318_CX_CTRL_TCP_DISABLE |
 692                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 693                                 COH901318_CX_CTRL_HSP_ENABLE |
 694                                 COH901318_CX_CTRL_HSS_DISABLE |
 695                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 696                                 COH901318_CX_CTRL_PRDD_DEST,
 697                 .param.ctrl_lli_last = 0 |
 698                                 COH901318_CX_CTRL_TC_ENABLE |
 699                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 700                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 701                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 702                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 703                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 704                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 705                                 COH901318_CX_CTRL_TCP_DISABLE |
 706                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 707                                 COH901318_CX_CTRL_HSP_ENABLE |
 708                                 COH901318_CX_CTRL_HSS_DISABLE |
 709                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 710                                 COH901318_CX_CTRL_PRDD_DEST,
 711         },
 712         {
 713                 .number = U300_DMA_MSL_RX_3,
 714                 .name = "MSL RX 3",
 715                 .priority_high = 0,
 716                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 717                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 718                                 COH901318_CX_CFG_LCR_DISABLE |
 719                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 720                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 721                 .param.ctrl_lli_chained = 0 |
 722                                 COH901318_CX_CTRL_TC_ENABLE |
 723                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 724                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 725                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 726                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 727                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 728                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 729                                 COH901318_CX_CTRL_TCP_DISABLE |
 730                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 731                                 COH901318_CX_CTRL_HSP_ENABLE |
 732                                 COH901318_CX_CTRL_HSS_DISABLE |
 733                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 734                                 COH901318_CX_CTRL_PRDD_DEST,
 735                 .param.ctrl_lli = 0 |
 736                                 COH901318_CX_CTRL_TC_ENABLE |
 737                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 738                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 739                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 740                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 741                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 742                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 743                                 COH901318_CX_CTRL_TCP_DISABLE |
 744                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 745                                 COH901318_CX_CTRL_HSP_ENABLE |
 746                                 COH901318_CX_CTRL_HSS_DISABLE |
 747                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 748                                 COH901318_CX_CTRL_PRDD_DEST,
 749                 .param.ctrl_lli_last = 0 |
 750                                 COH901318_CX_CTRL_TC_ENABLE |
 751                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 752                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 753                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 754                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 755                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 756                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 757                                 COH901318_CX_CTRL_TCP_DISABLE |
 758                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 759                                 COH901318_CX_CTRL_HSP_ENABLE |
 760                                 COH901318_CX_CTRL_HSS_DISABLE |
 761                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 762                                 COH901318_CX_CTRL_PRDD_DEST,
 763         },
 764         {
 765                 .number = U300_DMA_MSL_RX_4,
 766                 .name = "MSL RX 4",
 767                 .priority_high = 0,
 768                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 769                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 770                                 COH901318_CX_CFG_LCR_DISABLE |
 771                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 772                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 773                 .param.ctrl_lli_chained = 0 |
 774                                 COH901318_CX_CTRL_TC_ENABLE |
 775                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 776                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 777                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 778                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 779                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 780                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 781                                 COH901318_CX_CTRL_TCP_DISABLE |
 782                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 783                                 COH901318_CX_CTRL_HSP_ENABLE |
 784                                 COH901318_CX_CTRL_HSS_DISABLE |
 785                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 786                                 COH901318_CX_CTRL_PRDD_DEST,
 787                 .param.ctrl_lli = 0 |
 788                                 COH901318_CX_CTRL_TC_ENABLE |
 789                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 790                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 791                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 792                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 793                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 794                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 795                                 COH901318_CX_CTRL_TCP_DISABLE |
 796                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 797                                 COH901318_CX_CTRL_HSP_ENABLE |
 798                                 COH901318_CX_CTRL_HSS_DISABLE |
 799                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 800                                 COH901318_CX_CTRL_PRDD_DEST,
 801                 .param.ctrl_lli_last = 0 |
 802                                 COH901318_CX_CTRL_TC_ENABLE |
 803                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 804                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 805                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 806                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 807                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 808                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 809                                 COH901318_CX_CTRL_TCP_DISABLE |
 810                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 811                                 COH901318_CX_CTRL_HSP_ENABLE |
 812                                 COH901318_CX_CTRL_HSS_DISABLE |
 813                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 814                                 COH901318_CX_CTRL_PRDD_DEST,
 815         },
 816         {
 817                 .number = U300_DMA_MSL_RX_5,
 818                 .name = "MSL RX 5",
 819                 .priority_high = 0,
 820                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 821                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 822                                 COH901318_CX_CFG_LCR_DISABLE |
 823                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 824                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 825                 .param.ctrl_lli_chained = 0 |
 826                                 COH901318_CX_CTRL_TC_ENABLE |
 827                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 828                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 829                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 830                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 831                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 832                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 833                                 COH901318_CX_CTRL_TCP_DISABLE |
 834                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 835                                 COH901318_CX_CTRL_HSP_ENABLE |
 836                                 COH901318_CX_CTRL_HSS_DISABLE |
 837                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 838                                 COH901318_CX_CTRL_PRDD_DEST,
 839                 .param.ctrl_lli = 0 |
 840                                 COH901318_CX_CTRL_TC_ENABLE |
 841                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 842                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 843                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 844                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 845                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 846                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 847                                 COH901318_CX_CTRL_TCP_DISABLE |
 848                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 849                                 COH901318_CX_CTRL_HSP_ENABLE |
 850                                 COH901318_CX_CTRL_HSS_DISABLE |
 851                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 852                                 COH901318_CX_CTRL_PRDD_DEST,
 853                 .param.ctrl_lli_last = 0 |
 854                                 COH901318_CX_CTRL_TC_ENABLE |
 855                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 856                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 857                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 858                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 859                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 860                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 861                                 COH901318_CX_CTRL_TCP_DISABLE |
 862                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 863                                 COH901318_CX_CTRL_HSP_ENABLE |
 864                                 COH901318_CX_CTRL_HSS_DISABLE |
 865                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 866                                 COH901318_CX_CTRL_PRDD_DEST,
 867         },
 868         {
 869                 .number = U300_DMA_MSL_RX_6,
 870                 .name = "MSL RX 6",
 871                 .priority_high = 0,
 872                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 873         },
 874         /*
 875          * Don't set up device address, burst count or size of src
 876          * or dst bus for this peripheral - handled by PrimeCell
 877          * DMA extension.
 878          */
 879         {
 880                 .number = U300_DMA_MMCSD_RX_TX,
 881                 .name = "MMCSD RX TX",
 882                 .priority_high = 0,
 883                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 884                                 COH901318_CX_CFG_LCR_DISABLE |
 885                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 886                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 887                 .param.ctrl_lli_chained = 0 |
 888                                 COH901318_CX_CTRL_TC_ENABLE |
 889                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 890                                 COH901318_CX_CTRL_TCP_ENABLE |
 891                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 892                                 COH901318_CX_CTRL_HSP_ENABLE |
 893                                 COH901318_CX_CTRL_HSS_DISABLE |
 894                                 COH901318_CX_CTRL_DDMA_LEGACY,
 895                 .param.ctrl_lli = 0 |
 896                                 COH901318_CX_CTRL_TC_ENABLE |
 897                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 898                                 COH901318_CX_CTRL_TCP_ENABLE |
 899                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 900                                 COH901318_CX_CTRL_HSP_ENABLE |
 901                                 COH901318_CX_CTRL_HSS_DISABLE |
 902                                 COH901318_CX_CTRL_DDMA_LEGACY,
 903                 .param.ctrl_lli_last = 0 |
 904                                 COH901318_CX_CTRL_TC_ENABLE |
 905                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 906                                 COH901318_CX_CTRL_TCP_DISABLE |
 907                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 908                                 COH901318_CX_CTRL_HSP_ENABLE |
 909                                 COH901318_CX_CTRL_HSS_DISABLE |
 910                                 COH901318_CX_CTRL_DDMA_LEGACY,
 911
 912         },
 913         {
 914                 .number = U300_DMA_MSPRO_TX,
 915                 .name = "MSPRO TX",
 916                 .priority_high = 0,
 917         },
 918         {
 919                 .number = U300_DMA_MSPRO_RX,
 920                 .name = "MSPRO RX",
 921                 .priority_high = 0,
 922         },
 923         /*
 924          * Don't set up device address, burst count or size of src
 925          * or dst bus for this peripheral - handled by PrimeCell
 926          * DMA extension.
 927          */
 928         {
 929                 .number = U300_DMA_UART0_TX,
 930                 .name = "UART0 TX",
 931                 .priority_high = 0,
 932                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 933                                 COH901318_CX_CFG_LCR_DISABLE |
 934                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 935                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 936                 .param.ctrl_lli_chained = 0 |
 937                                 COH901318_CX_CTRL_TC_ENABLE |
 938                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 939                                 COH901318_CX_CTRL_TCP_ENABLE |
 940                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 941                                 COH901318_CX_CTRL_HSP_ENABLE |
 942                                 COH901318_CX_CTRL_HSS_DISABLE |
 943                                 COH901318_CX_CTRL_DDMA_LEGACY,
 944                 .param.ctrl_lli = 0 |
 945                                 COH901318_CX_CTRL_TC_ENABLE |
 946                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 947                                 COH901318_CX_CTRL_TCP_ENABLE |
 948                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 949                                 COH901318_CX_CTRL_HSP_ENABLE |
 950                                 COH901318_CX_CTRL_HSS_DISABLE |
 951                                 COH901318_CX_CTRL_DDMA_LEGACY,
 952                 .param.ctrl_lli_last = 0 |
 953                                 COH901318_CX_CTRL_TC_ENABLE |
 954                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 955                                 COH901318_CX_CTRL_TCP_ENABLE |
 956                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 957                                 COH901318_CX_CTRL_HSP_ENABLE |
 958                                 COH901318_CX_CTRL_HSS_DISABLE |
 959                                 COH901318_CX_CTRL_DDMA_LEGACY,
 960         },
 961         {
 962                 .number = U300_DMA_UART0_RX,
 963                 .name = "UART0 RX",
 964                 .priority_high = 0,
 965                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 966                                 COH901318_CX_CFG_LCR_DISABLE |
 967                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 968                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 969                 .param.ctrl_lli_chained = 0 |
 970                                 COH901318_CX_CTRL_TC_ENABLE |
 971                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 972                                 COH901318_CX_CTRL_TCP_ENABLE |
 973                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 974                                 COH901318_CX_CTRL_HSP_ENABLE |
 975                                 COH901318_CX_CTRL_HSS_DISABLE |
 976                                 COH901318_CX_CTRL_DDMA_LEGACY,
 977                 .param.ctrl_lli = 0 |
 978                                 COH901318_CX_CTRL_TC_ENABLE |
 979                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 980                                 COH901318_CX_CTRL_TCP_ENABLE |
 981                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 982                                 COH901318_CX_CTRL_HSP_ENABLE |
 983                                 COH901318_CX_CTRL_HSS_DISABLE |
 984                                 COH901318_CX_CTRL_DDMA_LEGACY,
 985                 .param.ctrl_lli_last = 0 |
 986                                 COH901318_CX_CTRL_TC_ENABLE |
 987                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 988                                 COH901318_CX_CTRL_TCP_ENABLE |
 989                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 990                                 COH901318_CX_CTRL_HSP_ENABLE |
 991                                 COH901318_CX_CTRL_HSS_DISABLE |
 992                                 COH901318_CX_CTRL_DDMA_LEGACY,
 993         },
 994         {
 995                 .number = U300_DMA_APEX_TX,
 996                 .name = "APEX TX",
 997                 .priority_high = 0,
 998         },
 999         {
1000                 .number = U300_DMA_APEX_RX,
1001                 .name = "APEX RX",
1002                 .priority_high = 0,
1003         },
1004         {
1005                 .number = U300_DMA_PCM_I2S0_TX,
1006                 .name = "PCM I2S0 TX",
1007                 .priority_high = 1,
1008                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1009                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1010                                 COH901318_CX_CFG_LCR_DISABLE |
1011                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1012                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1013                 .param.ctrl_lli_chained = 0 |
1014                                 COH901318_CX_CTRL_TC_ENABLE |
1015                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1016                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1017                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1018                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1019                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1020                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1021                                 COH901318_CX_CTRL_TCP_DISABLE |
1022                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1023                                 COH901318_CX_CTRL_HSP_ENABLE |
1024                                 COH901318_CX_CTRL_HSS_DISABLE |
1025                                 COH901318_CX_CTRL_DDMA_LEGACY |
1026                                 COH901318_CX_CTRL_PRDD_SOURCE,
1027                 .param.ctrl_lli = 0 |
1028                                 COH901318_CX_CTRL_TC_ENABLE |
1029                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1030                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1031                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1032                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1033                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1034                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1035                                 COH901318_CX_CTRL_TCP_ENABLE |
1036                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1037                                 COH901318_CX_CTRL_HSP_ENABLE |
1038                                 COH901318_CX_CTRL_HSS_DISABLE |
1039                                 COH901318_CX_CTRL_DDMA_LEGACY |
1040                                 COH901318_CX_CTRL_PRDD_SOURCE,
1041                 .param.ctrl_lli_last = 0 |
1042                                 COH901318_CX_CTRL_TC_ENABLE |
1043                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1044                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1045                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1046                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1047                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1048                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1049                                 COH901318_CX_CTRL_TCP_ENABLE |
1050                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1051                                 COH901318_CX_CTRL_HSP_ENABLE |
1052                                 COH901318_CX_CTRL_HSS_DISABLE |
1053                                 COH901318_CX_CTRL_DDMA_LEGACY |
1054                                 COH901318_CX_CTRL_PRDD_SOURCE,
1055         },
1056         {
1057                 .number = U300_DMA_PCM_I2S0_RX,
1058                 .name = "PCM I2S0 RX",
1059                 .priority_high = 1,
1060                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1061                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1062                                 COH901318_CX_CFG_LCR_DISABLE |
1063                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1064                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1065                 .param.ctrl_lli_chained = 0 |
1066                                 COH901318_CX_CTRL_TC_ENABLE |
1067                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1068                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1069                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1070                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1071                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1072                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1073                                 COH901318_CX_CTRL_TCP_DISABLE |
1074                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1075                                 COH901318_CX_CTRL_HSP_ENABLE |
1076                                 COH901318_CX_CTRL_HSS_DISABLE |
1077                                 COH901318_CX_CTRL_DDMA_LEGACY |
1078                                 COH901318_CX_CTRL_PRDD_DEST,
1079                 .param.ctrl_lli = 0 |
1080                                 COH901318_CX_CTRL_TC_ENABLE |
1081                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1082                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1083                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1084                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1085                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1086                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1087                                 COH901318_CX_CTRL_TCP_ENABLE |
1088                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1089                                 COH901318_CX_CTRL_HSP_ENABLE |
1090                                 COH901318_CX_CTRL_HSS_DISABLE |
1091                                 COH901318_CX_CTRL_DDMA_LEGACY |
1092                                 COH901318_CX_CTRL_PRDD_DEST,
1093                 .param.ctrl_lli_last = 0 |
1094                                 COH901318_CX_CTRL_TC_ENABLE |
1095                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1096                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1097                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1098                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1099                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1100                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1101                                 COH901318_CX_CTRL_TCP_ENABLE |
1102                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1103                                 COH901318_CX_CTRL_HSP_ENABLE |
1104                                 COH901318_CX_CTRL_HSS_DISABLE |
1105                                 COH901318_CX_CTRL_DDMA_LEGACY |
1106                                 COH901318_CX_CTRL_PRDD_DEST,
1107         },
1108         {
1109                 .number = U300_DMA_PCM_I2S1_TX,
1110                 .name = "PCM I2S1 TX",
1111                 .priority_high = 1,
1112                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1113                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1114                                 COH901318_CX_CFG_LCR_DISABLE |
1115                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1116                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1117                 .param.ctrl_lli_chained = 0 |
1118                                 COH901318_CX_CTRL_TC_ENABLE |
1119                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1120                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1121                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1122                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1123                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1124                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1125                                 COH901318_CX_CTRL_TCP_DISABLE |
1126                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1127                                 COH901318_CX_CTRL_HSP_ENABLE |
1128                                 COH901318_CX_CTRL_HSS_DISABLE |
1129                                 COH901318_CX_CTRL_DDMA_LEGACY |
1130                                 COH901318_CX_CTRL_PRDD_SOURCE,
1131                 .param.ctrl_lli = 0 |
1132                                 COH901318_CX_CTRL_TC_ENABLE |
1133                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1134                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1135                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1136                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1137                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1138                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1139                                 COH901318_CX_CTRL_TCP_ENABLE |
1140                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1141                                 COH901318_CX_CTRL_HSP_ENABLE |
1142                                 COH901318_CX_CTRL_HSS_DISABLE |
1143                                 COH901318_CX_CTRL_DDMA_LEGACY |
1144                                 COH901318_CX_CTRL_PRDD_SOURCE,
1145                 .param.ctrl_lli_last = 0 |
1146                                 COH901318_CX_CTRL_TC_ENABLE |
1147                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1148                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1149                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1150                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1151                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1152                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1153                                 COH901318_CX_CTRL_TCP_ENABLE |
1154                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1155                                 COH901318_CX_CTRL_HSP_ENABLE |
1156                                 COH901318_CX_CTRL_HSS_DISABLE |
1157                                 COH901318_CX_CTRL_DDMA_LEGACY |
1158                                 COH901318_CX_CTRL_PRDD_SOURCE,
1159         },
1160         {
1161                 .number = U300_DMA_PCM_I2S1_RX,
1162                 .name = "PCM I2S1 RX",
1163                 .priority_high = 1,
1164                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1165                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1166                                 COH901318_CX_CFG_LCR_DISABLE |
1167                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1168                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1169                 .param.ctrl_lli_chained = 0 |
1170                                 COH901318_CX_CTRL_TC_ENABLE |
1171                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1172                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1173                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1174                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1175                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1176                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1177                                 COH901318_CX_CTRL_TCP_DISABLE |
1178                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1179                                 COH901318_CX_CTRL_HSP_ENABLE |
1180                                 COH901318_CX_CTRL_HSS_DISABLE |
1181                                 COH901318_CX_CTRL_DDMA_LEGACY |
1182                                 COH901318_CX_CTRL_PRDD_DEST,
1183                 .param.ctrl_lli = 0 |
1184                                 COH901318_CX_CTRL_TC_ENABLE |
1185                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1186                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1187                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1188                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1189                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1190                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1191                                 COH901318_CX_CTRL_TCP_ENABLE |
1192                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1193                                 COH901318_CX_CTRL_HSP_ENABLE |
1194                                 COH901318_CX_CTRL_HSS_DISABLE |
1195                                 COH901318_CX_CTRL_DDMA_LEGACY |
1196                                 COH901318_CX_CTRL_PRDD_DEST,
1197                 .param.ctrl_lli_last = 0 |
1198                                 COH901318_CX_CTRL_TC_ENABLE |
1199                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1200                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1201                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1202                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1203                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1204                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1205                                 COH901318_CX_CTRL_TCP_ENABLE |
1206                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1207                                 COH901318_CX_CTRL_HSP_ENABLE |
1208                                 COH901318_CX_CTRL_HSS_DISABLE |
1209                                 COH901318_CX_CTRL_DDMA_LEGACY |
1210                                 COH901318_CX_CTRL_PRDD_DEST,
1211         },
1212         {
1213                 .number = U300_DMA_XGAM_CDI,
1214                 .name = "XGAM CDI",
1215                 .priority_high = 0,
1216         },
1217         {
1218                 .number = U300_DMA_XGAM_PDI,
1219                 .name = "XGAM PDI",
1220                 .priority_high = 0,
1221         },
1222         /*
1223          * Don't set up device address, burst count or size of src
1224          * or dst bus for this peripheral - handled by PrimeCell
1225          * DMA extension.
1226          */
1227         {
1228                 .number = U300_DMA_SPI_TX,
1229                 .name = "SPI TX",
1230                 .priority_high = 0,
1231                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1232                                 COH901318_CX_CFG_LCR_DISABLE |
1233                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1234                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1235                 .param.ctrl_lli_chained = 0 |
1236                                 COH901318_CX_CTRL_TC_ENABLE |
1237                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1238                                 COH901318_CX_CTRL_TCP_DISABLE |
1239                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1240                                 COH901318_CX_CTRL_HSP_ENABLE |
1241                                 COH901318_CX_CTRL_HSS_DISABLE |
1242                                 COH901318_CX_CTRL_DDMA_LEGACY,
1243                 .param.ctrl_lli = 0 |
1244                                 COH901318_CX_CTRL_TC_ENABLE |
1245                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1246                                 COH901318_CX_CTRL_TCP_DISABLE |
1247                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1248                                 COH901318_CX_CTRL_HSP_ENABLE |
1249                                 COH901318_CX_CTRL_HSS_DISABLE |
1250                                 COH901318_CX_CTRL_DDMA_LEGACY,
1251                 .param.ctrl_lli_last = 0 |
1252                                 COH901318_CX_CTRL_TC_ENABLE |
1253                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1254                                 COH901318_CX_CTRL_TCP_DISABLE |
1255                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1256                                 COH901318_CX_CTRL_HSP_ENABLE |
1257                                 COH901318_CX_CTRL_HSS_DISABLE |
1258                                 COH901318_CX_CTRL_DDMA_LEGACY,
1259         },
1260         {
1261                 .number = U300_DMA_SPI_RX,
1262                 .name = "SPI RX",
1263                 .priority_high = 0,
1264                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1265                                 COH901318_CX_CFG_LCR_DISABLE |
1266                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1267                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1268                 .param.ctrl_lli_chained = 0 |
1269                                 COH901318_CX_CTRL_TC_ENABLE |
1270                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1271                                 COH901318_CX_CTRL_TCP_DISABLE |
1272                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1273                                 COH901318_CX_CTRL_HSP_ENABLE |
1274                                 COH901318_CX_CTRL_HSS_DISABLE |
1275                                 COH901318_CX_CTRL_DDMA_LEGACY,
1276                 .param.ctrl_lli = 0 |
1277                                 COH901318_CX_CTRL_TC_ENABLE |
1278                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1279                                 COH901318_CX_CTRL_TCP_DISABLE |
1280                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1281                                 COH901318_CX_CTRL_HSP_ENABLE |
1282                                 COH901318_CX_CTRL_HSS_DISABLE |
1283                                 COH901318_CX_CTRL_DDMA_LEGACY,
1284                 .param.ctrl_lli_last = 0 |
1285                                 COH901318_CX_CTRL_TC_ENABLE |
1286                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1287                                 COH901318_CX_CTRL_TCP_DISABLE |
1288                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1289                                 COH901318_CX_CTRL_HSP_ENABLE |
1290                                 COH901318_CX_CTRL_HSS_DISABLE |
1291                                 COH901318_CX_CTRL_DDMA_LEGACY,
1292
1293         },
1294         {
1295                 .number = U300_DMA_GENERAL_PURPOSE_0,
1296                 .name = "GENERAL 00",
1297                 .priority_high = 0,
1298
1299                 .param.config = flags_memcpy_config,
1300                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1301                 .param.ctrl_lli = flags_memcpy_lli,
1302                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1303         },
1304         {
1305                 .number = U300_DMA_GENERAL_PURPOSE_1,
1306                 .name = "GENERAL 01",
1307                 .priority_high = 0,
1308
1309                 .param.config = flags_memcpy_config,
1310                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1311                 .param.ctrl_lli = flags_memcpy_lli,
1312                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1313         },
1314         {
1315                 .number = U300_DMA_GENERAL_PURPOSE_2,
1316                 .name = "GENERAL 02",
1317                 .priority_high = 0,
1318
1319                 .param.config = flags_memcpy_config,
1320                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1321                 .param.ctrl_lli = flags_memcpy_lli,
1322                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1323         },
1324         {
1325                 .number = U300_DMA_GENERAL_PURPOSE_3,
1326                 .name = "GENERAL 03",
1327                 .priority_high = 0,
1328
1329                 .param.config = flags_memcpy_config,
1330                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1331                 .param.ctrl_lli = flags_memcpy_lli,
1332                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1333         },
1334         {
1335                 .number = U300_DMA_GENERAL_PURPOSE_4,
1336                 .name = "GENERAL 04",
1337                 .priority_high = 0,
1338
1339                 .param.config = flags_memcpy_config,
1340                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1341                 .param.ctrl_lli = flags_memcpy_lli,
1342                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1343         },
1344         {
1345                 .number = U300_DMA_GENERAL_PURPOSE_5,
1346                 .name = "GENERAL 05",
1347                 .priority_high = 0,
1348
1349                 .param.config = flags_memcpy_config,
1350                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1351                 .param.ctrl_lli = flags_memcpy_lli,
1352                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1353         },
1354         {
1355                 .number = U300_DMA_GENERAL_PURPOSE_6,
1356                 .name = "GENERAL 06",
1357                 .priority_high = 0,
1358
1359                 .param.config = flags_memcpy_config,
1360                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1361                 .param.ctrl_lli = flags_memcpy_lli,
1362                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1363         },
1364         {
1365                 .number = U300_DMA_GENERAL_PURPOSE_7,
1366                 .name = "GENERAL 07",
1367                 .priority_high = 0,
1368
1369                 .param.config = flags_memcpy_config,
1370                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1371                 .param.ctrl_lli = flags_memcpy_lli,
1372                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1373         },
1374         {
1375                 .number = U300_DMA_GENERAL_PURPOSE_8,
1376                 .name = "GENERAL 08",
1377                 .priority_high = 0,
1378
1379                 .param.config = flags_memcpy_config,
1380                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1381                 .param.ctrl_lli = flags_memcpy_lli,
1382                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1383         },
1384 #ifdef CONFIG_MACH_U300_BS335
1385         {
1386                 .number = U300_DMA_UART1_TX,
1387                 .name = "UART1 TX",
1388                 .priority_high = 0,
1389         },
1390         {
1391                 .number = U300_DMA_UART1_RX,
1392                 .name = "UART1 RX",
1393                 .priority_high = 0,
1394         }
1395 #else
1396         {
1397                 .number = U300_DMA_GENERAL_PURPOSE_9,
1398                 .name = "GENERAL 09",
1399                 .priority_high = 0,
1400
1401                 .param.config = flags_memcpy_config,
1402                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1403                 .param.ctrl_lli = flags_memcpy_lli,
1404                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1405         },
1406         {
1407                 .number = U300_DMA_GENERAL_PURPOSE_10,
1408                 .name = "GENERAL 10",
1409                 .priority_high = 0,
1410
1411                 .param.config = flags_memcpy_config,
1412                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1413                 .param.ctrl_lli = flags_memcpy_lli,
1414                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1415         }
1416 #endif
1417 };
1418
1419
1420 static struct coh901318_platform coh901318_platform = {
1421         .chans_slave = dma_slave_channels,
1422         .chans_memcpy = dma_memcpy_channels,
1423         .access_memory_state = coh901318_access_memory_state,
1424         .chan_conf = chan_config,
1425         .max_channels = U300_DMA_CHANNELS,
1426 };
1427
1428 static struct resource pinctrl_resources[] = {
1429         {
1430                 .start = U300_SYSCON_BASE,
1431                 .end   = U300_SYSCON_BASE + SZ_4K - 1,
1432                 .flags = IORESOURCE_MEM,
1433         },
1434 };
1435
1436 static struct platform_device wdog_device = {
1437         .name = "coh901327_wdog",
1438         .id = -1,
1439         .num_resources = ARRAY_SIZE(wdog_resources),
1440         .resource = wdog_resources,
1441 };
1442
1443 static struct platform_device i2c0_device = {
1444         .name = "stu300",
1445         .id = 0,
1446         .num_resources = ARRAY_SIZE(i2c0_resources),
1447         .resource = i2c0_resources,
1448 };
1449
1450 static struct platform_device i2c1_device = {
1451         .name = "stu300",
1452         .id = 1,
1453         .num_resources = ARRAY_SIZE(i2c1_resources),
1454         .resource = i2c1_resources,
1455 };
1456
1457 static struct platform_device pinctrl_device = {
1458         .name = "pinctrl-u300",
1459         .id = -1,
1460         .num_resources = ARRAY_SIZE(pinctrl_resources),
1461         .resource = pinctrl_resources,
1462 };
1463
1464 /*
1465  * The different variants have a few different versions of the
1466  * GPIO block, with different number of ports.
1467  */
1468 static struct u300_gpio_platform u300_gpio_plat = {
1469 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
1470         .variant = U300_GPIO_COH901335,
1471         .ports = 3,
1472 #endif
1473 #ifdef CONFIG_MACH_U300_BS335
1474         .variant = U300_GPIO_COH901571_3_BS335,
1475         .ports = 7,
1476 #endif
1477 #ifdef CONFIG_MACH_U300_BS365
1478         .variant = U300_GPIO_COH901571_3_BS365,
1479         .ports = 5,
1480 #endif
1481         .gpio_base = 0,
1482         .gpio_irq_base = IRQ_U300_GPIO_BASE,
1483         .pinctrl_device = &pinctrl_device,
1484 };
1485
1486 static struct platform_device gpio_device = {
1487         .name = "u300-gpio",
1488         .id = -1,
1489         .num_resources = ARRAY_SIZE(gpio_resources),
1490         .resource = gpio_resources,
1491         .dev = {
1492                 .platform_data = &u300_gpio_plat,
1493         },
1494 };
1495
1496 static struct platform_device keypad_device = {
1497         .name = "keypad",
1498         .id = -1,
1499         .num_resources = ARRAY_SIZE(keypad_resources),
1500         .resource = keypad_resources,
1501 };
1502
1503 static struct platform_device rtc_device = {
1504         .name = "rtc-coh901331",
1505         .id = -1,
1506         .num_resources = ARRAY_SIZE(rtc_resources),
1507         .resource = rtc_resources,
1508 };
1509
1510 static struct mtd_partition u300_partitions[] = {
1511         {
1512                 .name = "bootrecords",
1513                 .offset = 0,
1514                 .size = SZ_128K,
1515         },
1516         {
1517                 .name = "free",
1518                 .offset = SZ_128K,
1519                 .size = 8064 * SZ_1K,
1520         },
1521         {
1522                 .name = "platform",
1523                 .offset = 8192 * SZ_1K,
1524                 .size = 253952 * SZ_1K,
1525         },
1526 };
1527
1528 static struct fsmc_nand_platform_data nand_platform_data = {
1529         .partitions = u300_partitions,
1530         .nr_partitions = ARRAY_SIZE(u300_partitions),
1531         .options = NAND_SKIP_BBTSCAN,
1532         .width = FSMC_NAND_BW8,
1533 };
1534
1535 static struct platform_device nand_device = {
1536         .name = "fsmc-nand",
1537         .id = -1,
1538         .resource = fsmc_resources,
1539         .num_resources = ARRAY_SIZE(fsmc_resources),
1540         .dev = {
1541                 .platform_data = &nand_platform_data,
1542         },
1543 };
1544
1545 static struct platform_device dma_device = {
1546         .name           = "coh901318",
1547         .id             = -1,
1548         .resource       = dma_resource,
1549         .num_resources  = ARRAY_SIZE(dma_resource),
1550         .dev = {
1551                 .platform_data = &coh901318_platform,
1552                 .coherent_dma_mask = ~0,
1553         },
1554 };
1555
1556 static unsigned long pin_pullup_conf[] = {
1557         PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
1558 };
1559
1560 static unsigned long pin_highz_conf[] = {
1561         PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
1562 };
1563
1564 /* Pin control settings */
1565 static struct pinctrl_map __initdata u300_pinmux_map[] = {
1566         /* anonymous maps for chip power and EMIFs */
1567         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
1568         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
1569         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
1570         /* per-device maps for MMC/SD, SPI and UART */
1571         PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
1572         PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
1573         PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
1574         /* This pin is used for clock return rather than GPIO */
1575         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
1576                                     pin_pullup_conf),
1577         /* This pin is used for card detect */
1578         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
1579                                     pin_highz_conf),
1580 };
1581
1582 struct u300_mux_hog {
1583         struct device *dev;
1584         struct pinctrl *p;
1585 };
1586
1587 static struct u300_mux_hog u300_mux_hogs[] = {
1588         {
1589                 .dev = &uart0_device.dev,
1590         },
1591         {
1592                 .dev = &pl022_device.dev,
1593         },
1594         {
1595                 .dev = &mmcsd_device.dev,
1596         },
1597 };
1598
1599 static int __init u300_pinctrl_fetch(void)
1600 {
1601         int i;
1602
1603         for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
1604                 struct pinctrl *p;
1605
1606                 p = pinctrl_get_select_default(u300_mux_hogs[i].dev);
1607                 if (IS_ERR(p)) {
1608                         pr_err("u300: could not get pinmux hog for dev %s\n",
1609                                dev_name(u300_mux_hogs[i].dev));
1610                         continue;
1611                 }
1612                 u300_mux_hogs[i].p = p;
1613         }
1614         return 0;
1615 }
1616 subsys_initcall(u300_pinctrl_fetch);
1617
1618 /*
1619  * Notice that AMBA devices are initialized before platform devices.
1620  *
1621  */
1622 static struct platform_device *platform_devs[] __initdata = {
1623         &dma_device,
1624         &i2c0_device,
1625         &i2c1_device,
1626         &keypad_device,
1627         &rtc_device,
1628         &gpio_device,
1629         &nand_device,
1630         &wdog_device,
1631 };
1632
1633 /*
1634  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1635  * together so some interrupts are connected to the first one and some
1636  * to the second one.
1637  */
1638 void __init u300_init_irq(void)
1639 {
1640         u32 mask[2] = {0, 0};
1641         struct clk *clk;
1642         int i;
1643
1644         /* initialize clocking early, we want to clock the INTCON */
1645         u300_clock_init();
1646
1647         /* Clock the interrupt controller */
1648         clk = clk_get_sys("intcon", NULL);
1649         BUG_ON(IS_ERR(clk));
1650         clk_enable(clk);
1651
1652         for (i = 0; i < U300_VIC_IRQS_END; i++)
1653                 set_bit(i, (unsigned long *) &mask[0]);
1654         vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1655         vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
1656 }
1657
1658
1659 /*
1660  * U300 platforms peripheral handling
1661  */
1662 struct db_chip {
1663         u16 chipid;
1664         const char *name;
1665 };
1666
1667 /*
1668  * This is a list of the Digital Baseband chips used in the U300 platform.
1669  */
1670 static struct db_chip db_chips[] __initdata = {
1671         {
1672                 .chipid = 0xb800,
1673                 .name = "DB3000",
1674         },
1675         {
1676                 .chipid = 0xc000,
1677                 .name = "DB3100",
1678         },
1679         {
1680                 .chipid = 0xc800,
1681                 .name = "DB3150",
1682         },
1683         {
1684                 .chipid = 0xd800,
1685                 .name = "DB3200",
1686         },
1687         {
1688                 .chipid = 0xe000,
1689                 .name = "DB3250",
1690         },
1691         {
1692                 .chipid = 0xe800,
1693                 .name = "DB3210",
1694         },
1695         {
1696                 .chipid = 0xf000,
1697                 .name = "DB3350 P1x",
1698         },
1699         {
1700                 .chipid = 0xf100,
1701                 .name = "DB3350 P2x",
1702         },
1703         {
1704                 .chipid = 0x0000, /* List terminator */
1705                 .name = NULL,
1706         }
1707 };
1708
1709 static void __init u300_init_check_chip(void)
1710 {
1711
1712         u16 val;
1713         struct db_chip *chip;
1714         const char *chipname;
1715         const char unknown[] = "UNKNOWN";
1716
1717         /* Read out and print chip ID */
1718         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1719         /* This is in funky bigendian order... */
1720         val = (val & 0xFFU) << 8 | (val >> 8);
1721         chip = db_chips;
1722         chipname = unknown;
1723
1724         for ( ; chip->chipid; chip++) {
1725                 if (chip->chipid == (val & 0xFF00U)) {
1726                         chipname = chip->name;
1727                         break;
1728                 }
1729         }
1730         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1731                "(chip ID 0x%04x)\n", chipname, val);
1732
1733 #ifdef CONFIG_MACH_U300_BS330
1734         if ((val & 0xFF00U) != 0xd800) {
1735                 printk(KERN_ERR "Platform configured for BS330 " \
1736                        "with DB3200 but %s detected, expect problems!",
1737                        chipname);
1738         }
1739 #endif
1740 #ifdef CONFIG_MACH_U300_BS335
1741         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1742                 printk(KERN_ERR "Platform configured for BS335 " \
1743                        " with DB3350 but %s detected, expect problems!",
1744                        chipname);
1745         }
1746 #endif
1747 #ifdef CONFIG_MACH_U300_BS365
1748         if ((val & 0xFF00U) != 0xe800) {
1749                 printk(KERN_ERR "Platform configured for BS365 " \
1750                        "with DB3210 but %s detected, expect problems!",
1751                        chipname);
1752         }
1753 #endif
1754
1755
1756 }
1757
1758 /*
1759  * Some devices and their resources require reserved physical memory from
1760  * the end of the available RAM. This function traverses the list of devices
1761  * and assigns actual addresses to these.
1762  */
1763 static void __init u300_assign_physmem(void)
1764 {
1765         unsigned long curr_start = __pa(high_memory);
1766         int i, j;
1767
1768         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1769                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1770                         struct resource *const res =
1771                           &platform_devs[i]->resource[j];
1772
1773                         if (IORESOURCE_MEM == res->flags &&
1774                                      0 == res->start) {
1775                                 res->start  = curr_start;
1776                                 res->end   += curr_start;
1777                                 curr_start += resource_size(res);
1778
1779                                 printk(KERN_INFO "core.c: Mapping RAM " \
1780                                        "%#x-%#x to device %s:%s\n",
1781                                         res->start, res->end,
1782                                        platform_devs[i]->name, res->name);
1783                         }
1784                 }
1785         }
1786 }
1787
1788 void __init u300_init_devices(void)
1789 {
1790         int i;
1791         u16 val;
1792
1793         /* Check what platform we run and print some status information */
1794         u300_init_check_chip();
1795
1796         /* Set system to run at PLL208, max performance, a known state. */
1797         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1798         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1799         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1800         /* Wait for the PLL208 to lock if not locked in yet */
1801         while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1802                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1803         /* Initialize SPI device with some board specifics */
1804         u300_spi_init(&pl022_device);
1805
1806         /* Register the AMBA devices in the AMBA bus abstraction layer */
1807         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1808                 struct amba_device *d = amba_devs[i];
1809                 amba_device_register(d, &iomem_resource);
1810         }
1811
1812         u300_assign_physmem();
1813
1814         /* Initialize pinmuxing */
1815         pinctrl_register_mappings(u300_pinmux_map,
1816                                   ARRAY_SIZE(u300_pinmux_map));
1817
1818         /* Register subdevices on the I2C buses */
1819         u300_i2c_register_board_devices();
1820
1821         /* Register the platform devices */
1822         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1823
1824         /* Register subdevices on the SPI bus */
1825         u300_spi_register_board_devices();
1826
1827         /* Enable SEMI self refresh */
1828         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1829                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1830         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1831 }
1832
1833 static int core_module_init(void)
1834 {
1835         /*
1836          * This needs to be initialized later: it needs the input framework
1837          * to be initialized first.
1838          */
1839         return mmc_init(&mmcsd_device);
1840 }
1841 module_init(core_module_init);
1842
1843 /* Forward declare this function from the watchdog */
1844 void coh901327_watchdog_reset(void);
1845
1846 void u300_restart(char mode, const char *cmd)
1847 {
1848         switch (mode) {
1849         case 's':
1850         case 'h':
1851 #ifdef CONFIG_COH901327_WATCHDOG
1852                 coh901327_watchdog_reset();
1853 #endif
1854                 break;
1855         default:
1856                 /* Do nothing */
1857                 break;
1858         }
1859         /* Wait for system do die/reset. */
1860         while (1);
1861 }