Pileus Git - ~andy/linux/blob - arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2010 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/amba/serial.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/gpio.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/mtd/nand.h>
  27 #include <linux/mtd/fsmc.h>
  28 #include <linux/pinctrl/machine.h>
  29 #include <linux/pinctrl/consumer.h>
  30 #include <linux/pinctrl/pinconf-generic.h>
  31 #include <linux/dma-mapping.h>
  32
  33 #include <asm/types.h>
  34 #include <asm/setup.h>
  35 #include <asm/memory.h>
  36 #include <asm/hardware/vic.h>
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/irq.h>
  39
  40 #include <mach/coh901318.h>
  41 #include <mach/hardware.h>
  42 #include <mach/syscon.h>
  43 #include <mach/dma_channels.h>
  44 #include <mach/gpio-u300.h>
  45
  46 #include "clock.h"
  47 #include "mmc.h"
  48 #include "spi.h"
  49 #include "i2c.h"
  50
  51 /*
  52  * Static I/O mappings that are needed for booting the U300 platforms. The
  53  * only things we need are the areas where we find the timer, syscon and
  54  * intcon, since the remaining device drivers will map their own memory
  55  * physical to virtual as the need arise.
  56  */
  57 static struct map_desc u300_io_desc[] __initdata = {
  58         {
  59                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  60                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  61                 .length         = SZ_64K,
  62                 .type           = MT_DEVICE,
  63         },
  64         {
  65                 .virtual        = U300_AHB_PER_VIRT_BASE,
  66                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  67                 .length         = SZ_32K,
  68                 .type           = MT_DEVICE,
  69         },
  70         {
  71                 .virtual        = U300_FAST_PER_VIRT_BASE,
  72                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  73                 .length         = SZ_32K,
  74                 .type           = MT_DEVICE,
  75         },
  76 };
  77
  78 void __init u300_map_io(void)
  79 {
  80         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  81         /* We enable a real big DMA buffer if need be. */
  82         init_consistent_dma_size(SZ_4M);
  83 }
  84
  85 /*
  86  * Declaration of devices found on the U300 board and
  87  * their respective memory locations.
  88  */
  89
  90 static struct amba_pl011_data uart0_plat_data = {
  91 #ifdef CONFIG_COH901318
  92         .dma_filter = coh901318_filter_id,
  93         .dma_rx_param = (void *) U300_DMA_UART0_RX,
  94         .dma_tx_param = (void *) U300_DMA_UART0_TX,
  95 #endif
  96 };
  97
  98 static struct amba_device uart0_device = {
  99         .dev = {
 100                 .coherent_dma_mask = ~0,
 101                 .init_name = "uart0", /* Slow device at 0x3000 offset */
 102                 .platform_data = &uart0_plat_data,
 103         },
 104         .res = {
 105                 .start = U300_UART0_BASE,
 106                 .end   = U300_UART0_BASE + SZ_4K - 1,
 107                 .flags = IORESOURCE_MEM,
 108         },
 109         .irq = { IRQ_U300_UART0, NO_IRQ },
 110 };
 111
 112 /* The U335 have an additional UART1 on the APP CPU */
 113 #ifdef CONFIG_MACH_U300_BS335
 114 static struct amba_pl011_data uart1_plat_data = {
 115 #ifdef CONFIG_COH901318
 116         .dma_filter = coh901318_filter_id,
 117         .dma_rx_param = (void *) U300_DMA_UART1_RX,
 118         .dma_tx_param = (void *) U300_DMA_UART1_TX,
 119 #endif
 120 };
 121
 122 static struct amba_device uart1_device = {
 123         .dev = {
 124                 .coherent_dma_mask = ~0,
 125                 .init_name = "uart1", /* Fast device at 0x7000 offset */
 126                 .platform_data = &uart1_plat_data,
 127         },
 128         .res = {
 129                 .start = U300_UART1_BASE,
 130                 .end   = U300_UART1_BASE + SZ_4K - 1,
 131                 .flags = IORESOURCE_MEM,
 132         },
 133         .irq = { IRQ_U300_UART1, NO_IRQ },
 134 };
 135 #endif
 136
 137 static struct amba_device pl172_device = {
 138         .dev = {
 139                 .init_name = "pl172", /* AHB device at 0x4000 offset */
 140                 .platform_data = NULL,
 141         },
 142         .res = {
 143                 .start = U300_EMIF_CFG_BASE,
 144                 .end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
 145                 .flags = IORESOURCE_MEM,
 146         },
 147 };
 148
 149
 150 /*
 151  * Everything within this next ifdef deals with external devices connected to
 152  * the APP SPI bus.
 153  */
 154 static struct amba_device pl022_device = {
 155         .dev = {
 156                 .coherent_dma_mask = ~0,
 157                 .init_name = "pl022", /* Fast device at 0x6000 offset */
 158         },
 159         .res = {
 160                 .start = U300_SPI_BASE,
 161                 .end   = U300_SPI_BASE + SZ_4K - 1,
 162                 .flags = IORESOURCE_MEM,
 163         },
 164         .irq = {IRQ_U300_SPI, NO_IRQ },
 165         /*
 166          * This device has a DMA channel but the Linux driver does not use
 167          * it currently.
 168          */
 169 };
 170
 171 static struct amba_device mmcsd_device = {
 172         .dev = {
 173                 .init_name = "mmci", /* Fast device at 0x1000 offset */
 174                 .platform_data = NULL, /* Added later */
 175         },
 176         .res = {
 177                 .start = U300_MMCSD_BASE,
 178                 .end   = U300_MMCSD_BASE + SZ_4K - 1,
 179                 .flags = IORESOURCE_MEM,
 180         },
 181         .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
 182         /*
 183          * This device has a DMA channel but the Linux driver does not use
 184          * it currently.
 185          */
 186 };
 187
 188 /*
 189  * The order of device declaration may be important, since some devices
 190  * have dependencies on other devices being initialized first.
 191  */
 192 static struct amba_device *amba_devs[] __initdata = {
 193         &uart0_device,
 194 #ifdef CONFIG_MACH_U300_BS335
 195         &uart1_device,
 196 #endif
 197         &pl022_device,
 198         &pl172_device,
 199         &mmcsd_device,
 200 };
 201
 202 /* Here follows a list of all hw resources that the platform devices
 203  * allocate. Note, clock dependencies are not included
 204  */
 205
 206 static struct resource gpio_resources[] = {
 207         {
 208                 .start = U300_GPIO_BASE,
 209                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 210                 .flags = IORESOURCE_MEM,
 211         },
 212         {
 213                 .name  = "gpio0",
 214                 .start = IRQ_U300_GPIO_PORT0,
 215                 .end   = IRQ_U300_GPIO_PORT0,
 216                 .flags = IORESOURCE_IRQ,
 217         },
 218         {
 219                 .name  = "gpio1",
 220                 .start = IRQ_U300_GPIO_PORT1,
 221                 .end   = IRQ_U300_GPIO_PORT1,
 222                 .flags = IORESOURCE_IRQ,
 223         },
 224         {
 225                 .name  = "gpio2",
 226                 .start = IRQ_U300_GPIO_PORT2,
 227                 .end   = IRQ_U300_GPIO_PORT2,
 228                 .flags = IORESOURCE_IRQ,
 229         },
 230 #if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
 231         {
 232                 .name  = "gpio3",
 233                 .start = IRQ_U300_GPIO_PORT3,
 234                 .end   = IRQ_U300_GPIO_PORT3,
 235                 .flags = IORESOURCE_IRQ,
 236         },
 237         {
 238                 .name  = "gpio4",
 239                 .start = IRQ_U300_GPIO_PORT4,
 240                 .end   = IRQ_U300_GPIO_PORT4,
 241                 .flags = IORESOURCE_IRQ,
 242         },
 243 #endif
 244 #ifdef CONFIG_MACH_U300_BS335
 245         {
 246                 .name  = "gpio5",
 247                 .start = IRQ_U300_GPIO_PORT5,
 248                 .end   = IRQ_U300_GPIO_PORT5,
 249                 .flags = IORESOURCE_IRQ,
 250         },
 251         {
 252                 .name  = "gpio6",
 253                 .start = IRQ_U300_GPIO_PORT6,
 254                 .end   = IRQ_U300_GPIO_PORT6,
 255                 .flags = IORESOURCE_IRQ,
 256         },
 257 #endif /* CONFIG_MACH_U300_BS335 */
 258 };
 259
 260 static struct resource keypad_resources[] = {
 261         {
 262                 .start = U300_KEYPAD_BASE,
 263                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 264                 .flags = IORESOURCE_MEM,
 265         },
 266         {
 267                 .name  = "coh901461-press",
 268                 .start = IRQ_U300_KEYPAD_KEYBF,
 269                 .end   = IRQ_U300_KEYPAD_KEYBF,
 270                 .flags = IORESOURCE_IRQ,
 271         },
 272         {
 273                 .name  = "coh901461-release",
 274                 .start = IRQ_U300_KEYPAD_KEYBR,
 275                 .end   = IRQ_U300_KEYPAD_KEYBR,
 276                 .flags = IORESOURCE_IRQ,
 277         },
 278 };
 279
 280 static struct resource rtc_resources[] = {
 281         {
 282                 .start = U300_RTC_BASE,
 283                 .end   = U300_RTC_BASE + SZ_4K - 1,
 284                 .flags = IORESOURCE_MEM,
 285         },
 286         {
 287                 .start = IRQ_U300_RTC,
 288                 .end   = IRQ_U300_RTC,
 289                 .flags = IORESOURCE_IRQ,
 290         },
 291 };
 292
 293 /*
 294  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 295  * but these are not yet used by the driver.
 296  */
 297 static struct resource fsmc_resources[] = {
 298         {
 299                 .name  = "nand_data",
 300                 .start = U300_NAND_CS0_PHYS_BASE,
 301                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
 302                 .flags = IORESOURCE_MEM,
 303         },
 304         {
 305                 .name  = "fsmc_regs",
 306                 .start = U300_NAND_IF_PHYS_BASE,
 307                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 308                 .flags = IORESOURCE_MEM,
 309         },
 310 };
 311
 312 static struct resource i2c0_resources[] = {
 313         {
 314                 .start = U300_I2C0_BASE,
 315                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 316                 .flags = IORESOURCE_MEM,
 317         },
 318         {
 319                 .start = IRQ_U300_I2C0,
 320                 .end   = IRQ_U300_I2C0,
 321                 .flags = IORESOURCE_IRQ,
 322         },
 323 };
 324
 325 static struct resource i2c1_resources[] = {
 326         {
 327                 .start = U300_I2C1_BASE,
 328                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 329                 .flags = IORESOURCE_MEM,
 330         },
 331         {
 332                 .start = IRQ_U300_I2C1,
 333                 .end   = IRQ_U300_I2C1,
 334                 .flags = IORESOURCE_IRQ,
 335         },
 336
 337 };
 338
 339 static struct resource wdog_resources[] = {
 340         {
 341                 .start = U300_WDOG_BASE,
 342                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 343                 .flags = IORESOURCE_MEM,
 344         },
 345         {
 346                 .start = IRQ_U300_WDOG,
 347                 .end   = IRQ_U300_WDOG,
 348                 .flags = IORESOURCE_IRQ,
 349         }
 350 };
 351
 352 static struct resource dma_resource[] = {
 353         {
 354                 .start = U300_DMAC_BASE,
 355                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 356                 .flags =  IORESOURCE_MEM,
 357         },
 358         {
 359                 .start = IRQ_U300_DMA,
 360                 .end = IRQ_U300_DMA,
 361                 .flags =  IORESOURCE_IRQ,
 362         }
 363 };
 364
 365 #ifdef CONFIG_MACH_U300_BS335
 366 /* points out all dma slave channels.
 367  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 368  * Select all channels from A to B, end of list is marked with -1,-1
 369  */
 370 static int dma_slave_channels[] = {
 371         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 372         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 373
 374 /* points out all dma memcpy channels. */
 375 static int dma_memcpy_channels[] = {
 376         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 377
 378 #else /* CONFIG_MACH_U300_BS335 */
 379
 380 static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
 381 static int dma_memcpy_channels[] = {
 382         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
 383
 384 #endif
 385
 386 /** register dma for memory access
 387  *
 388  * active  1 means dma intends to access memory
 389  *         0 means dma wont access memory
 390  */
 391 static void coh901318_access_memory_state(struct device *dev, bool active)
 392 {
 393 }
 394
 395 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 396                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 397                         COH901318_CX_CFG_LCR_DISABLE | \
 398                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 399                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 400 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 401                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 402                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 403                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 404                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 405                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 406                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 407                         COH901318_CX_CTRL_TCP_DISABLE | \
 408                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 409                         COH901318_CX_CTRL_HSP_DISABLE | \
 410                         COH901318_CX_CTRL_HSS_DISABLE | \
 411                         COH901318_CX_CTRL_DDMA_LEGACY | \
 412                         COH901318_CX_CTRL_PRDD_SOURCE)
 413 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 414                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 415                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 416                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 417                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 418                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 419                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 420                         COH901318_CX_CTRL_TCP_DISABLE | \
 421                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 422                         COH901318_CX_CTRL_HSP_DISABLE | \
 423                         COH901318_CX_CTRL_HSS_DISABLE | \
 424                         COH901318_CX_CTRL_DDMA_LEGACY | \
 425                         COH901318_CX_CTRL_PRDD_SOURCE)
 426 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 427                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 428                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 429                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 430                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 431                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 432                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 433                         COH901318_CX_CTRL_TCP_DISABLE | \
 434                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 435                         COH901318_CX_CTRL_HSP_DISABLE | \
 436                         COH901318_CX_CTRL_HSS_DISABLE | \
 437                         COH901318_CX_CTRL_DDMA_LEGACY | \
 438                         COH901318_CX_CTRL_PRDD_SOURCE)
 439
 440 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 441         {
 442                 .number = U300_DMA_MSL_TX_0,
 443                 .name = "MSL TX 0",
 444                 .priority_high = 0,
 445                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 446         },
 447         {
 448                 .number = U300_DMA_MSL_TX_1,
 449                 .name = "MSL TX 1",
 450                 .priority_high = 0,
 451                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 452                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 453                                 COH901318_CX_CFG_LCR_DISABLE |
 454                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 455                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 456                 .param.ctrl_lli_chained = 0 |
 457                                 COH901318_CX_CTRL_TC_ENABLE |
 458                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 459                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 460                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 461                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 462                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 463                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 464                                 COH901318_CX_CTRL_TCP_DISABLE |
 465                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 466                                 COH901318_CX_CTRL_HSP_ENABLE |
 467                                 COH901318_CX_CTRL_HSS_DISABLE |
 468                                 COH901318_CX_CTRL_DDMA_LEGACY |
 469                                 COH901318_CX_CTRL_PRDD_SOURCE,
 470                 .param.ctrl_lli = 0 |
 471                                 COH901318_CX_CTRL_TC_ENABLE |
 472                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 473                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 474                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 475                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 476                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 477                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 478                                 COH901318_CX_CTRL_TCP_ENABLE |
 479                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 480                                 COH901318_CX_CTRL_HSP_ENABLE |
 481                                 COH901318_CX_CTRL_HSS_DISABLE |
 482                                 COH901318_CX_CTRL_DDMA_LEGACY |
 483                                 COH901318_CX_CTRL_PRDD_SOURCE,
 484                 .param.ctrl_lli_last = 0 |
 485                                 COH901318_CX_CTRL_TC_ENABLE |
 486                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 487                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 488                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 489                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 490                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 491                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 492                                 COH901318_CX_CTRL_TCP_ENABLE |
 493                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 494                                 COH901318_CX_CTRL_HSP_ENABLE |
 495                                 COH901318_CX_CTRL_HSS_DISABLE |
 496                                 COH901318_CX_CTRL_DDMA_LEGACY |
 497                                 COH901318_CX_CTRL_PRDD_SOURCE,
 498         },
 499         {
 500                 .number = U300_DMA_MSL_TX_2,
 501                 .name = "MSL TX 2",
 502                 .priority_high = 0,
 503                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 504                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 505                                 COH901318_CX_CFG_LCR_DISABLE |
 506                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 507                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 508                 .param.ctrl_lli_chained = 0 |
 509                                 COH901318_CX_CTRL_TC_ENABLE |
 510                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 511                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 512                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 513                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 514                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 515                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 516                                 COH901318_CX_CTRL_TCP_DISABLE |
 517                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 518                                 COH901318_CX_CTRL_HSP_ENABLE |
 519                                 COH901318_CX_CTRL_HSS_DISABLE |
 520                                 COH901318_CX_CTRL_DDMA_LEGACY |
 521                                 COH901318_CX_CTRL_PRDD_SOURCE,
 522                 .param.ctrl_lli = 0 |
 523                                 COH901318_CX_CTRL_TC_ENABLE |
 524                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 525                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 526                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 527                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 528                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 529                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 530                                 COH901318_CX_CTRL_TCP_ENABLE |
 531                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 532                                 COH901318_CX_CTRL_HSP_ENABLE |
 533                                 COH901318_CX_CTRL_HSS_DISABLE |
 534                                 COH901318_CX_CTRL_DDMA_LEGACY |
 535                                 COH901318_CX_CTRL_PRDD_SOURCE,
 536                 .param.ctrl_lli_last = 0 |
 537                                 COH901318_CX_CTRL_TC_ENABLE |
 538                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 539                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 540                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 541                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 542                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 543                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 544                                 COH901318_CX_CTRL_TCP_ENABLE |
 545                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 546                                 COH901318_CX_CTRL_HSP_ENABLE |
 547                                 COH901318_CX_CTRL_HSS_DISABLE |
 548                                 COH901318_CX_CTRL_DDMA_LEGACY |
 549                                 COH901318_CX_CTRL_PRDD_SOURCE,
 550                 .desc_nbr_max = 10,
 551         },
 552         {
 553                 .number = U300_DMA_MSL_TX_3,
 554                 .name = "MSL TX 3",
 555                 .priority_high = 0,
 556                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 557                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 558                                 COH901318_CX_CFG_LCR_DISABLE |
 559                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 560                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 561                 .param.ctrl_lli_chained = 0 |
 562                                 COH901318_CX_CTRL_TC_ENABLE |
 563                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 564                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 565                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 566                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 567                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 568                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 569                                 COH901318_CX_CTRL_TCP_DISABLE |
 570                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 571                                 COH901318_CX_CTRL_HSP_ENABLE |
 572                                 COH901318_CX_CTRL_HSS_DISABLE |
 573                                 COH901318_CX_CTRL_DDMA_LEGACY |
 574                                 COH901318_CX_CTRL_PRDD_SOURCE,
 575                 .param.ctrl_lli = 0 |
 576                                 COH901318_CX_CTRL_TC_ENABLE |
 577                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 578                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 579                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 580                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 581                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 582                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 583                                 COH901318_CX_CTRL_TCP_ENABLE |
 584                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 585                                 COH901318_CX_CTRL_HSP_ENABLE |
 586                                 COH901318_CX_CTRL_HSS_DISABLE |
 587                                 COH901318_CX_CTRL_DDMA_LEGACY |
 588                                 COH901318_CX_CTRL_PRDD_SOURCE,
 589                 .param.ctrl_lli_last = 0 |
 590                                 COH901318_CX_CTRL_TC_ENABLE |
 591                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 592                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 593                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 594                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 595                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 596                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 597                                 COH901318_CX_CTRL_TCP_ENABLE |
 598                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 599                                 COH901318_CX_CTRL_HSP_ENABLE |
 600                                 COH901318_CX_CTRL_HSS_DISABLE |
 601                                 COH901318_CX_CTRL_DDMA_LEGACY |
 602                                 COH901318_CX_CTRL_PRDD_SOURCE,
 603         },
 604         {
 605                 .number = U300_DMA_MSL_TX_4,
 606                 .name = "MSL TX 4",
 607                 .priority_high = 0,
 608                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 609                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 610                                 COH901318_CX_CFG_LCR_DISABLE |
 611                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 612                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 613                 .param.ctrl_lli_chained = 0 |
 614                                 COH901318_CX_CTRL_TC_ENABLE |
 615                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 616                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 617                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 618                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 619                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 620                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 621                                 COH901318_CX_CTRL_TCP_DISABLE |
 622                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 623                                 COH901318_CX_CTRL_HSP_ENABLE |
 624                                 COH901318_CX_CTRL_HSS_DISABLE |
 625                                 COH901318_CX_CTRL_DDMA_LEGACY |
 626                                 COH901318_CX_CTRL_PRDD_SOURCE,
 627                 .param.ctrl_lli = 0 |
 628                                 COH901318_CX_CTRL_TC_ENABLE |
 629                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 630                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 631                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 632                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 633                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 634                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 635                                 COH901318_CX_CTRL_TCP_ENABLE |
 636                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 637                                 COH901318_CX_CTRL_HSP_ENABLE |
 638                                 COH901318_CX_CTRL_HSS_DISABLE |
 639                                 COH901318_CX_CTRL_DDMA_LEGACY |
 640                                 COH901318_CX_CTRL_PRDD_SOURCE,
 641                 .param.ctrl_lli_last = 0 |
 642                                 COH901318_CX_CTRL_TC_ENABLE |
 643                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 644                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 645                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 646                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 647                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 648                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 649                                 COH901318_CX_CTRL_TCP_ENABLE |
 650                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 651                                 COH901318_CX_CTRL_HSP_ENABLE |
 652                                 COH901318_CX_CTRL_HSS_DISABLE |
 653                                 COH901318_CX_CTRL_DDMA_LEGACY |
 654                                 COH901318_CX_CTRL_PRDD_SOURCE,
 655         },
 656         {
 657                 .number = U300_DMA_MSL_TX_5,
 658                 .name = "MSL TX 5",
 659                 .priority_high = 0,
 660                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 661         },
 662         {
 663                 .number = U300_DMA_MSL_TX_6,
 664                 .name = "MSL TX 6",
 665                 .priority_high = 0,
 666                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 667         },
 668         {
 669                 .number = U300_DMA_MSL_RX_0,
 670                 .name = "MSL RX 0",
 671                 .priority_high = 0,
 672                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 673         },
 674         {
 675                 .number = U300_DMA_MSL_RX_1,
 676                 .name = "MSL RX 1",
 677                 .priority_high = 0,
 678                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 679                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 680                                 COH901318_CX_CFG_LCR_DISABLE |
 681                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 682                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 683                 .param.ctrl_lli_chained = 0 |
 684                                 COH901318_CX_CTRL_TC_ENABLE |
 685                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 686                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 687                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 688                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 689                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 690                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 691                                 COH901318_CX_CTRL_TCP_DISABLE |
 692                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 693                                 COH901318_CX_CTRL_HSP_ENABLE |
 694                                 COH901318_CX_CTRL_HSS_DISABLE |
 695                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 696                                 COH901318_CX_CTRL_PRDD_DEST,
 697                 .param.ctrl_lli = 0,
 698                 .param.ctrl_lli_last = 0 |
 699                                 COH901318_CX_CTRL_TC_ENABLE |
 700                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 701                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 702                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 703                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 704                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 705                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 706                                 COH901318_CX_CTRL_TCP_DISABLE |
 707                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 708                                 COH901318_CX_CTRL_HSP_ENABLE |
 709                                 COH901318_CX_CTRL_HSS_DISABLE |
 710                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 711                                 COH901318_CX_CTRL_PRDD_DEST,
 712         },
 713         {
 714                 .number = U300_DMA_MSL_RX_2,
 715                 .name = "MSL RX 2",
 716                 .priority_high = 0,
 717                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 718                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 719                                 COH901318_CX_CFG_LCR_DISABLE |
 720                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 721                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 722                 .param.ctrl_lli_chained = 0 |
 723                                 COH901318_CX_CTRL_TC_ENABLE |
 724                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 725                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 726                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 727                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 728                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 729                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 730                                 COH901318_CX_CTRL_TCP_DISABLE |
 731                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 732                                 COH901318_CX_CTRL_HSP_ENABLE |
 733                                 COH901318_CX_CTRL_HSS_DISABLE |
 734                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 735                                 COH901318_CX_CTRL_PRDD_DEST,
 736                 .param.ctrl_lli = 0 |
 737                                 COH901318_CX_CTRL_TC_ENABLE |
 738                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 739                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 740                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 741                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 742                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 743                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 744                                 COH901318_CX_CTRL_TCP_DISABLE |
 745                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 746                                 COH901318_CX_CTRL_HSP_ENABLE |
 747                                 COH901318_CX_CTRL_HSS_DISABLE |
 748                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 749                                 COH901318_CX_CTRL_PRDD_DEST,
 750                 .param.ctrl_lli_last = 0 |
 751                                 COH901318_CX_CTRL_TC_ENABLE |
 752                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 753                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 754                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 755                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 756                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 757                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 758                                 COH901318_CX_CTRL_TCP_DISABLE |
 759                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 760                                 COH901318_CX_CTRL_HSP_ENABLE |
 761                                 COH901318_CX_CTRL_HSS_DISABLE |
 762                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 763                                 COH901318_CX_CTRL_PRDD_DEST,
 764         },
 765         {
 766                 .number = U300_DMA_MSL_RX_3,
 767                 .name = "MSL RX 3",
 768                 .priority_high = 0,
 769                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 770                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 771                                 COH901318_CX_CFG_LCR_DISABLE |
 772                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 773                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 774                 .param.ctrl_lli_chained = 0 |
 775                                 COH901318_CX_CTRL_TC_ENABLE |
 776                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 777                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 778                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 779                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 780                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 781                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 782                                 COH901318_CX_CTRL_TCP_DISABLE |
 783                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 784                                 COH901318_CX_CTRL_HSP_ENABLE |
 785                                 COH901318_CX_CTRL_HSS_DISABLE |
 786                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 787                                 COH901318_CX_CTRL_PRDD_DEST,
 788                 .param.ctrl_lli = 0 |
 789                                 COH901318_CX_CTRL_TC_ENABLE |
 790                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 791                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 792                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 793                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 794                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 795                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 796                                 COH901318_CX_CTRL_TCP_DISABLE |
 797                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 798                                 COH901318_CX_CTRL_HSP_ENABLE |
 799                                 COH901318_CX_CTRL_HSS_DISABLE |
 800                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 801                                 COH901318_CX_CTRL_PRDD_DEST,
 802                 .param.ctrl_lli_last = 0 |
 803                                 COH901318_CX_CTRL_TC_ENABLE |
 804                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 805                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 806                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 807                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 808                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 809                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 810                                 COH901318_CX_CTRL_TCP_DISABLE |
 811                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 812                                 COH901318_CX_CTRL_HSP_ENABLE |
 813                                 COH901318_CX_CTRL_HSS_DISABLE |
 814                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 815                                 COH901318_CX_CTRL_PRDD_DEST,
 816         },
 817         {
 818                 .number = U300_DMA_MSL_RX_4,
 819                 .name = "MSL RX 4",
 820                 .priority_high = 0,
 821                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 822                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 823                                 COH901318_CX_CFG_LCR_DISABLE |
 824                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 825                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 826                 .param.ctrl_lli_chained = 0 |
 827                                 COH901318_CX_CTRL_TC_ENABLE |
 828                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 829                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 830                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 831                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 832                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 833                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 834                                 COH901318_CX_CTRL_TCP_DISABLE |
 835                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 836                                 COH901318_CX_CTRL_HSP_ENABLE |
 837                                 COH901318_CX_CTRL_HSS_DISABLE |
 838                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 839                                 COH901318_CX_CTRL_PRDD_DEST,
 840                 .param.ctrl_lli = 0 |
 841                                 COH901318_CX_CTRL_TC_ENABLE |
 842                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 843                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 844                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 845                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 846                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 847                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 848                                 COH901318_CX_CTRL_TCP_DISABLE |
 849                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 850                                 COH901318_CX_CTRL_HSP_ENABLE |
 851                                 COH901318_CX_CTRL_HSS_DISABLE |
 852                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 853                                 COH901318_CX_CTRL_PRDD_DEST,
 854                 .param.ctrl_lli_last = 0 |
 855                                 COH901318_CX_CTRL_TC_ENABLE |
 856                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 857                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 858                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 859                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 860                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 861                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 862                                 COH901318_CX_CTRL_TCP_DISABLE |
 863                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 864                                 COH901318_CX_CTRL_HSP_ENABLE |
 865                                 COH901318_CX_CTRL_HSS_DISABLE |
 866                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 867                                 COH901318_CX_CTRL_PRDD_DEST,
 868         },
 869         {
 870                 .number = U300_DMA_MSL_RX_5,
 871                 .name = "MSL RX 5",
 872                 .priority_high = 0,
 873                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 874                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 875                                 COH901318_CX_CFG_LCR_DISABLE |
 876                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 877                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 878                 .param.ctrl_lli_chained = 0 |
 879                                 COH901318_CX_CTRL_TC_ENABLE |
 880                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 881                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 882                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 883                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 884                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 885                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 886                                 COH901318_CX_CTRL_TCP_DISABLE |
 887                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 888                                 COH901318_CX_CTRL_HSP_ENABLE |
 889                                 COH901318_CX_CTRL_HSS_DISABLE |
 890                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 891                                 COH901318_CX_CTRL_PRDD_DEST,
 892                 .param.ctrl_lli = 0 |
 893                                 COH901318_CX_CTRL_TC_ENABLE |
 894                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 895                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 896                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 897                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 898                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 899                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 900                                 COH901318_CX_CTRL_TCP_DISABLE |
 901                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 902                                 COH901318_CX_CTRL_HSP_ENABLE |
 903                                 COH901318_CX_CTRL_HSS_DISABLE |
 904                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 905                                 COH901318_CX_CTRL_PRDD_DEST,
 906                 .param.ctrl_lli_last = 0 |
 907                                 COH901318_CX_CTRL_TC_ENABLE |
 908                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 909                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 910                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 911                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 912                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 913                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 914                                 COH901318_CX_CTRL_TCP_DISABLE |
 915                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 916                                 COH901318_CX_CTRL_HSP_ENABLE |
 917                                 COH901318_CX_CTRL_HSS_DISABLE |
 918                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 919                                 COH901318_CX_CTRL_PRDD_DEST,
 920         },
 921         {
 922                 .number = U300_DMA_MSL_RX_6,
 923                 .name = "MSL RX 6",
 924                 .priority_high = 0,
 925                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 926         },
 927         /*
 928          * Don't set up device address, burst count or size of src
 929          * or dst bus for this peripheral - handled by PrimeCell
 930          * DMA extension.
 931          */
 932         {
 933                 .number = U300_DMA_MMCSD_RX_TX,
 934                 .name = "MMCSD RX TX",
 935                 .priority_high = 0,
 936                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 937                                 COH901318_CX_CFG_LCR_DISABLE |
 938                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 939                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 940                 .param.ctrl_lli_chained = 0 |
 941                                 COH901318_CX_CTRL_TC_ENABLE |
 942                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 943                                 COH901318_CX_CTRL_TCP_ENABLE |
 944                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 945                                 COH901318_CX_CTRL_HSP_ENABLE |
 946                                 COH901318_CX_CTRL_HSS_DISABLE |
 947                                 COH901318_CX_CTRL_DDMA_LEGACY,
 948                 .param.ctrl_lli = 0 |
 949                                 COH901318_CX_CTRL_TC_ENABLE |
 950                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 951                                 COH901318_CX_CTRL_TCP_ENABLE |
 952                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 953                                 COH901318_CX_CTRL_HSP_ENABLE |
 954                                 COH901318_CX_CTRL_HSS_DISABLE |
 955                                 COH901318_CX_CTRL_DDMA_LEGACY,
 956                 .param.ctrl_lli_last = 0 |
 957                                 COH901318_CX_CTRL_TC_ENABLE |
 958                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 959                                 COH901318_CX_CTRL_TCP_DISABLE |
 960                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 961                                 COH901318_CX_CTRL_HSP_ENABLE |
 962                                 COH901318_CX_CTRL_HSS_DISABLE |
 963                                 COH901318_CX_CTRL_DDMA_LEGACY,
 964
 965         },
 966         {
 967                 .number = U300_DMA_MSPRO_TX,
 968                 .name = "MSPRO TX",
 969                 .priority_high = 0,
 970         },
 971         {
 972                 .number = U300_DMA_MSPRO_RX,
 973                 .name = "MSPRO RX",
 974                 .priority_high = 0,
 975         },
 976         /*
 977          * Don't set up device address, burst count or size of src
 978          * or dst bus for this peripheral - handled by PrimeCell
 979          * DMA extension.
 980          */
 981         {
 982                 .number = U300_DMA_UART0_TX,
 983                 .name = "UART0 TX",
 984                 .priority_high = 0,
 985                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 986                                 COH901318_CX_CFG_LCR_DISABLE |
 987                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 988                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 989                 .param.ctrl_lli_chained = 0 |
 990                                 COH901318_CX_CTRL_TC_ENABLE |
 991                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 992                                 COH901318_CX_CTRL_TCP_ENABLE |
 993                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 994                                 COH901318_CX_CTRL_HSP_ENABLE |
 995                                 COH901318_CX_CTRL_HSS_DISABLE |
 996                                 COH901318_CX_CTRL_DDMA_LEGACY,
 997                 .param.ctrl_lli = 0 |
 998                                 COH901318_CX_CTRL_TC_ENABLE |
 999                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1000                                 COH901318_CX_CTRL_TCP_ENABLE |
1001                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1002                                 COH901318_CX_CTRL_HSP_ENABLE |
1003                                 COH901318_CX_CTRL_HSS_DISABLE |
1004                                 COH901318_CX_CTRL_DDMA_LEGACY,
1005                 .param.ctrl_lli_last = 0 |
1006                                 COH901318_CX_CTRL_TC_ENABLE |
1007                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1008                                 COH901318_CX_CTRL_TCP_ENABLE |
1009                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1010                                 COH901318_CX_CTRL_HSP_ENABLE |
1011                                 COH901318_CX_CTRL_HSS_DISABLE |
1012                                 COH901318_CX_CTRL_DDMA_LEGACY,
1013         },
1014         {
1015                 .number = U300_DMA_UART0_RX,
1016                 .name = "UART0 RX",
1017                 .priority_high = 0,
1018                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1019                                 COH901318_CX_CFG_LCR_DISABLE |
1020                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1021                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1022                 .param.ctrl_lli_chained = 0 |
1023                                 COH901318_CX_CTRL_TC_ENABLE |
1024                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1025                                 COH901318_CX_CTRL_TCP_ENABLE |
1026                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1027                                 COH901318_CX_CTRL_HSP_ENABLE |
1028                                 COH901318_CX_CTRL_HSS_DISABLE |
1029                                 COH901318_CX_CTRL_DDMA_LEGACY,
1030                 .param.ctrl_lli = 0 |
1031                                 COH901318_CX_CTRL_TC_ENABLE |
1032                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1033                                 COH901318_CX_CTRL_TCP_ENABLE |
1034                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1035                                 COH901318_CX_CTRL_HSP_ENABLE |
1036                                 COH901318_CX_CTRL_HSS_DISABLE |
1037                                 COH901318_CX_CTRL_DDMA_LEGACY,
1038                 .param.ctrl_lli_last = 0 |
1039                                 COH901318_CX_CTRL_TC_ENABLE |
1040                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1041                                 COH901318_CX_CTRL_TCP_ENABLE |
1042                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1043                                 COH901318_CX_CTRL_HSP_ENABLE |
1044                                 COH901318_CX_CTRL_HSS_DISABLE |
1045                                 COH901318_CX_CTRL_DDMA_LEGACY,
1046         },
1047         {
1048                 .number = U300_DMA_APEX_TX,
1049                 .name = "APEX TX",
1050                 .priority_high = 0,
1051         },
1052         {
1053                 .number = U300_DMA_APEX_RX,
1054                 .name = "APEX RX",
1055                 .priority_high = 0,
1056         },
1057         {
1058                 .number = U300_DMA_PCM_I2S0_TX,
1059                 .name = "PCM I2S0 TX",
1060                 .priority_high = 1,
1061                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1062                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1063                                 COH901318_CX_CFG_LCR_DISABLE |
1064                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1065                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1066                 .param.ctrl_lli_chained = 0 |
1067                                 COH901318_CX_CTRL_TC_ENABLE |
1068                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1069                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1070                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1071                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1072                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1073                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1074                                 COH901318_CX_CTRL_TCP_DISABLE |
1075                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1076                                 COH901318_CX_CTRL_HSP_ENABLE |
1077                                 COH901318_CX_CTRL_HSS_DISABLE |
1078                                 COH901318_CX_CTRL_DDMA_LEGACY |
1079                                 COH901318_CX_CTRL_PRDD_SOURCE,
1080                 .param.ctrl_lli = 0 |
1081                                 COH901318_CX_CTRL_TC_ENABLE |
1082                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1083                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1084                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1085                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1086                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1087                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1088                                 COH901318_CX_CTRL_TCP_ENABLE |
1089                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1090                                 COH901318_CX_CTRL_HSP_ENABLE |
1091                                 COH901318_CX_CTRL_HSS_DISABLE |
1092                                 COH901318_CX_CTRL_DDMA_LEGACY |
1093                                 COH901318_CX_CTRL_PRDD_SOURCE,
1094                 .param.ctrl_lli_last = 0 |
1095                                 COH901318_CX_CTRL_TC_ENABLE |
1096                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1097                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1098                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1099                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1100                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1101                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1102                                 COH901318_CX_CTRL_TCP_ENABLE |
1103                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1104                                 COH901318_CX_CTRL_HSP_ENABLE |
1105                                 COH901318_CX_CTRL_HSS_DISABLE |
1106                                 COH901318_CX_CTRL_DDMA_LEGACY |
1107                                 COH901318_CX_CTRL_PRDD_SOURCE,
1108         },
1109         {
1110                 .number = U300_DMA_PCM_I2S0_RX,
1111                 .name = "PCM I2S0 RX",
1112                 .priority_high = 1,
1113                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1114                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1115                                 COH901318_CX_CFG_LCR_DISABLE |
1116                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1117                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1118                 .param.ctrl_lli_chained = 0 |
1119                                 COH901318_CX_CTRL_TC_ENABLE |
1120                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1121                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1122                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1123                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1124                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1125                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1126                                 COH901318_CX_CTRL_TCP_DISABLE |
1127                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1128                                 COH901318_CX_CTRL_HSP_ENABLE |
1129                                 COH901318_CX_CTRL_HSS_DISABLE |
1130                                 COH901318_CX_CTRL_DDMA_LEGACY |
1131                                 COH901318_CX_CTRL_PRDD_DEST,
1132                 .param.ctrl_lli = 0 |
1133                                 COH901318_CX_CTRL_TC_ENABLE |
1134                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1135                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1136                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1137                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1138                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1139                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1140                                 COH901318_CX_CTRL_TCP_ENABLE |
1141                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1142                                 COH901318_CX_CTRL_HSP_ENABLE |
1143                                 COH901318_CX_CTRL_HSS_DISABLE |
1144                                 COH901318_CX_CTRL_DDMA_LEGACY |
1145                                 COH901318_CX_CTRL_PRDD_DEST,
1146                 .param.ctrl_lli_last = 0 |
1147                                 COH901318_CX_CTRL_TC_ENABLE |
1148                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1149                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1150                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1151                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1152                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1153                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1154                                 COH901318_CX_CTRL_TCP_ENABLE |
1155                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1156                                 COH901318_CX_CTRL_HSP_ENABLE |
1157                                 COH901318_CX_CTRL_HSS_DISABLE |
1158                                 COH901318_CX_CTRL_DDMA_LEGACY |
1159                                 COH901318_CX_CTRL_PRDD_DEST,
1160         },
1161         {
1162                 .number = U300_DMA_PCM_I2S1_TX,
1163                 .name = "PCM I2S1 TX",
1164                 .priority_high = 1,
1165                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1166                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1167                                 COH901318_CX_CFG_LCR_DISABLE |
1168                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1169                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1170                 .param.ctrl_lli_chained = 0 |
1171                                 COH901318_CX_CTRL_TC_ENABLE |
1172                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1173                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1174                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1175                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1176                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1177                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1178                                 COH901318_CX_CTRL_TCP_DISABLE |
1179                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1180                                 COH901318_CX_CTRL_HSP_ENABLE |
1181                                 COH901318_CX_CTRL_HSS_DISABLE |
1182                                 COH901318_CX_CTRL_DDMA_LEGACY |
1183                                 COH901318_CX_CTRL_PRDD_SOURCE,
1184                 .param.ctrl_lli = 0 |
1185                                 COH901318_CX_CTRL_TC_ENABLE |
1186                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1187                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1188                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1189                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1190                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1191                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1192                                 COH901318_CX_CTRL_TCP_ENABLE |
1193                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1194                                 COH901318_CX_CTRL_HSP_ENABLE |
1195                                 COH901318_CX_CTRL_HSS_DISABLE |
1196                                 COH901318_CX_CTRL_DDMA_LEGACY |
1197                                 COH901318_CX_CTRL_PRDD_SOURCE,
1198                 .param.ctrl_lli_last = 0 |
1199                                 COH901318_CX_CTRL_TC_ENABLE |
1200                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1201                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1202                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1203                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1204                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1205                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1206                                 COH901318_CX_CTRL_TCP_ENABLE |
1207                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1208                                 COH901318_CX_CTRL_HSP_ENABLE |
1209                                 COH901318_CX_CTRL_HSS_DISABLE |
1210                                 COH901318_CX_CTRL_DDMA_LEGACY |
1211                                 COH901318_CX_CTRL_PRDD_SOURCE,
1212         },
1213         {
1214                 .number = U300_DMA_PCM_I2S1_RX,
1215                 .name = "PCM I2S1 RX",
1216                 .priority_high = 1,
1217                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1218                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1219                                 COH901318_CX_CFG_LCR_DISABLE |
1220                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1221                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1222                 .param.ctrl_lli_chained = 0 |
1223                                 COH901318_CX_CTRL_TC_ENABLE |
1224                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1225                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1226                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1227                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1228                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1229                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1230                                 COH901318_CX_CTRL_TCP_DISABLE |
1231                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1232                                 COH901318_CX_CTRL_HSP_ENABLE |
1233                                 COH901318_CX_CTRL_HSS_DISABLE |
1234                                 COH901318_CX_CTRL_DDMA_LEGACY |
1235                                 COH901318_CX_CTRL_PRDD_DEST,
1236                 .param.ctrl_lli = 0 |
1237                                 COH901318_CX_CTRL_TC_ENABLE |
1238                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1239                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1240                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1241                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1242                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1243                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1244                                 COH901318_CX_CTRL_TCP_ENABLE |
1245                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1246                                 COH901318_CX_CTRL_HSP_ENABLE |
1247                                 COH901318_CX_CTRL_HSS_DISABLE |
1248                                 COH901318_CX_CTRL_DDMA_LEGACY |
1249                                 COH901318_CX_CTRL_PRDD_DEST,
1250                 .param.ctrl_lli_last = 0 |
1251                                 COH901318_CX_CTRL_TC_ENABLE |
1252                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1253                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1254                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1255                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1256                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1257                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1258                                 COH901318_CX_CTRL_TCP_ENABLE |
1259                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1260                                 COH901318_CX_CTRL_HSP_ENABLE |
1261                                 COH901318_CX_CTRL_HSS_DISABLE |
1262                                 COH901318_CX_CTRL_DDMA_LEGACY |
1263                                 COH901318_CX_CTRL_PRDD_DEST,
1264         },
1265         {
1266                 .number = U300_DMA_XGAM_CDI,
1267                 .name = "XGAM CDI",
1268                 .priority_high = 0,
1269         },
1270         {
1271                 .number = U300_DMA_XGAM_PDI,
1272                 .name = "XGAM PDI",
1273                 .priority_high = 0,
1274         },
1275         /*
1276          * Don't set up device address, burst count or size of src
1277          * or dst bus for this peripheral - handled by PrimeCell
1278          * DMA extension.
1279          */
1280         {
1281                 .number = U300_DMA_SPI_TX,
1282                 .name = "SPI TX",
1283                 .priority_high = 0,
1284                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1285                                 COH901318_CX_CFG_LCR_DISABLE |
1286                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1287                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1288                 .param.ctrl_lli_chained = 0 |
1289                                 COH901318_CX_CTRL_TC_ENABLE |
1290                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1291                                 COH901318_CX_CTRL_TCP_DISABLE |
1292                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1293                                 COH901318_CX_CTRL_HSP_ENABLE |
1294                                 COH901318_CX_CTRL_HSS_DISABLE |
1295                                 COH901318_CX_CTRL_DDMA_LEGACY,
1296                 .param.ctrl_lli = 0 |
1297                                 COH901318_CX_CTRL_TC_ENABLE |
1298                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1299                                 COH901318_CX_CTRL_TCP_DISABLE |
1300                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1301                                 COH901318_CX_CTRL_HSP_ENABLE |
1302                                 COH901318_CX_CTRL_HSS_DISABLE |
1303                                 COH901318_CX_CTRL_DDMA_LEGACY,
1304                 .param.ctrl_lli_last = 0 |
1305                                 COH901318_CX_CTRL_TC_ENABLE |
1306                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1307                                 COH901318_CX_CTRL_TCP_DISABLE |
1308                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1309                                 COH901318_CX_CTRL_HSP_ENABLE |
1310                                 COH901318_CX_CTRL_HSS_DISABLE |
1311                                 COH901318_CX_CTRL_DDMA_LEGACY,
1312         },
1313         {
1314                 .number = U300_DMA_SPI_RX,
1315                 .name = "SPI RX",
1316                 .priority_high = 0,
1317                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1318                                 COH901318_CX_CFG_LCR_DISABLE |
1319                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1320                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1321                 .param.ctrl_lli_chained = 0 |
1322                                 COH901318_CX_CTRL_TC_ENABLE |
1323                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1324                                 COH901318_CX_CTRL_TCP_DISABLE |
1325                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1326                                 COH901318_CX_CTRL_HSP_ENABLE |
1327                                 COH901318_CX_CTRL_HSS_DISABLE |
1328                                 COH901318_CX_CTRL_DDMA_LEGACY,
1329                 .param.ctrl_lli = 0 |
1330                                 COH901318_CX_CTRL_TC_ENABLE |
1331                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1332                                 COH901318_CX_CTRL_TCP_DISABLE |
1333                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1334                                 COH901318_CX_CTRL_HSP_ENABLE |
1335                                 COH901318_CX_CTRL_HSS_DISABLE |
1336                                 COH901318_CX_CTRL_DDMA_LEGACY,
1337                 .param.ctrl_lli_last = 0 |
1338                                 COH901318_CX_CTRL_TC_ENABLE |
1339                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1340                                 COH901318_CX_CTRL_TCP_DISABLE |
1341                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1342                                 COH901318_CX_CTRL_HSP_ENABLE |
1343                                 COH901318_CX_CTRL_HSS_DISABLE |
1344                                 COH901318_CX_CTRL_DDMA_LEGACY,
1345
1346         },
1347         {
1348                 .number = U300_DMA_GENERAL_PURPOSE_0,
1349                 .name = "GENERAL 00",
1350                 .priority_high = 0,
1351
1352                 .param.config = flags_memcpy_config,
1353                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1354                 .param.ctrl_lli = flags_memcpy_lli,
1355                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1356         },
1357         {
1358                 .number = U300_DMA_GENERAL_PURPOSE_1,
1359                 .name = "GENERAL 01",
1360                 .priority_high = 0,
1361
1362                 .param.config = flags_memcpy_config,
1363                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1364                 .param.ctrl_lli = flags_memcpy_lli,
1365                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1366         },
1367         {
1368                 .number = U300_DMA_GENERAL_PURPOSE_2,
1369                 .name = "GENERAL 02",
1370                 .priority_high = 0,
1371
1372                 .param.config = flags_memcpy_config,
1373                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1374                 .param.ctrl_lli = flags_memcpy_lli,
1375                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1376         },
1377         {
1378                 .number = U300_DMA_GENERAL_PURPOSE_3,
1379                 .name = "GENERAL 03",
1380                 .priority_high = 0,
1381
1382                 .param.config = flags_memcpy_config,
1383                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1384                 .param.ctrl_lli = flags_memcpy_lli,
1385                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1386         },
1387         {
1388                 .number = U300_DMA_GENERAL_PURPOSE_4,
1389                 .name = "GENERAL 04",
1390                 .priority_high = 0,
1391
1392                 .param.config = flags_memcpy_config,
1393                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1394                 .param.ctrl_lli = flags_memcpy_lli,
1395                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1396         },
1397         {
1398                 .number = U300_DMA_GENERAL_PURPOSE_5,
1399                 .name = "GENERAL 05",
1400                 .priority_high = 0,
1401
1402                 .param.config = flags_memcpy_config,
1403                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1404                 .param.ctrl_lli = flags_memcpy_lli,
1405                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1406         },
1407         {
1408                 .number = U300_DMA_GENERAL_PURPOSE_6,
1409                 .name = "GENERAL 06",
1410                 .priority_high = 0,
1411
1412                 .param.config = flags_memcpy_config,
1413                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1414                 .param.ctrl_lli = flags_memcpy_lli,
1415                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1416         },
1417         {
1418                 .number = U300_DMA_GENERAL_PURPOSE_7,
1419                 .name = "GENERAL 07",
1420                 .priority_high = 0,
1421
1422                 .param.config = flags_memcpy_config,
1423                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1424                 .param.ctrl_lli = flags_memcpy_lli,
1425                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1426         },
1427         {
1428                 .number = U300_DMA_GENERAL_PURPOSE_8,
1429                 .name = "GENERAL 08",
1430                 .priority_high = 0,
1431
1432                 .param.config = flags_memcpy_config,
1433                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1434                 .param.ctrl_lli = flags_memcpy_lli,
1435                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1436         },
1437 #ifdef CONFIG_MACH_U300_BS335
1438         {
1439                 .number = U300_DMA_UART1_TX,
1440                 .name = "UART1 TX",
1441                 .priority_high = 0,
1442         },
1443         {
1444                 .number = U300_DMA_UART1_RX,
1445                 .name = "UART1 RX",
1446                 .priority_high = 0,
1447         }
1448 #else
1449         {
1450                 .number = U300_DMA_GENERAL_PURPOSE_9,
1451                 .name = "GENERAL 09",
1452                 .priority_high = 0,
1453
1454                 .param.config = flags_memcpy_config,
1455                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1456                 .param.ctrl_lli = flags_memcpy_lli,
1457                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1458         },
1459         {
1460                 .number = U300_DMA_GENERAL_PURPOSE_10,
1461                 .name = "GENERAL 10",
1462                 .priority_high = 0,
1463
1464                 .param.config = flags_memcpy_config,
1465                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1466                 .param.ctrl_lli = flags_memcpy_lli,
1467                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1468         }
1469 #endif
1470 };
1471
1472
1473 static struct coh901318_platform coh901318_platform = {
1474         .chans_slave = dma_slave_channels,
1475         .chans_memcpy = dma_memcpy_channels,
1476         .access_memory_state = coh901318_access_memory_state,
1477         .chan_conf = chan_config,
1478         .max_channels = U300_DMA_CHANNELS,
1479 };
1480
1481 static struct resource pinctrl_resources[] = {
1482         {
1483                 .start = U300_SYSCON_BASE,
1484                 .end   = U300_SYSCON_BASE + SZ_4K - 1,
1485                 .flags = IORESOURCE_MEM,
1486         },
1487 };
1488
1489 static struct platform_device wdog_device = {
1490         .name = "coh901327_wdog",
1491         .id = -1,
1492         .num_resources = ARRAY_SIZE(wdog_resources),
1493         .resource = wdog_resources,
1494 };
1495
1496 static struct platform_device i2c0_device = {
1497         .name = "stu300",
1498         .id = 0,
1499         .num_resources = ARRAY_SIZE(i2c0_resources),
1500         .resource = i2c0_resources,
1501 };
1502
1503 static struct platform_device i2c1_device = {
1504         .name = "stu300",
1505         .id = 1,
1506         .num_resources = ARRAY_SIZE(i2c1_resources),
1507         .resource = i2c1_resources,
1508 };
1509
1510 static struct platform_device pinctrl_device = {
1511         .name = "pinctrl-u300",
1512         .id = -1,
1513         .num_resources = ARRAY_SIZE(pinctrl_resources),
1514         .resource = pinctrl_resources,
1515 };
1516
1517 /*
1518  * The different variants have a few different versions of the
1519  * GPIO block, with different number of ports.
1520  */
1521 static struct u300_gpio_platform u300_gpio_plat = {
1522 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
1523         .variant = U300_GPIO_COH901335,
1524         .ports = 3,
1525 #endif
1526 #ifdef CONFIG_MACH_U300_BS335
1527         .variant = U300_GPIO_COH901571_3_BS335,
1528         .ports = 7,
1529 #endif
1530 #ifdef CONFIG_MACH_U300_BS365
1531         .variant = U300_GPIO_COH901571_3_BS365,
1532         .ports = 5,
1533 #endif
1534         .gpio_base = 0,
1535         .gpio_irq_base = IRQ_U300_GPIO_BASE,
1536         .pinctrl_device = &pinctrl_device,
1537 };
1538
1539 static struct platform_device gpio_device = {
1540         .name = "u300-gpio",
1541         .id = -1,
1542         .num_resources = ARRAY_SIZE(gpio_resources),
1543         .resource = gpio_resources,
1544         .dev = {
1545                 .platform_data = &u300_gpio_plat,
1546         },
1547 };
1548
1549 static struct platform_device keypad_device = {
1550         .name = "keypad",
1551         .id = -1,
1552         .num_resources = ARRAY_SIZE(keypad_resources),
1553         .resource = keypad_resources,
1554 };
1555
1556 static struct platform_device rtc_device = {
1557         .name = "rtc-coh901331",
1558         .id = -1,
1559         .num_resources = ARRAY_SIZE(rtc_resources),
1560         .resource = rtc_resources,
1561 };
1562
1563 static struct mtd_partition u300_partitions[] = {
1564         {
1565                 .name = "bootrecords",
1566                 .offset = 0,
1567                 .size = SZ_128K,
1568         },
1569         {
1570                 .name = "free",
1571                 .offset = SZ_128K,
1572                 .size = 8064 * SZ_1K,
1573         },
1574         {
1575                 .name = "platform",
1576                 .offset = 8192 * SZ_1K,
1577                 .size = 253952 * SZ_1K,
1578         },
1579 };
1580
1581 static struct fsmc_nand_platform_data nand_platform_data = {
1582         .partitions = u300_partitions,
1583         .nr_partitions = ARRAY_SIZE(u300_partitions),
1584         .options = NAND_SKIP_BBTSCAN,
1585         .width = FSMC_NAND_BW8,
1586 };
1587
1588 static struct platform_device nand_device = {
1589         .name = "fsmc-nand",
1590         .id = -1,
1591         .resource = fsmc_resources,
1592         .num_resources = ARRAY_SIZE(fsmc_resources),
1593         .dev = {
1594                 .platform_data = &nand_platform_data,
1595         },
1596 };
1597
1598 static struct platform_device dma_device = {
1599         .name           = "coh901318",
1600         .id             = -1,
1601         .resource       = dma_resource,
1602         .num_resources  = ARRAY_SIZE(dma_resource),
1603         .dev = {
1604                 .platform_data = &coh901318_platform,
1605                 .coherent_dma_mask = ~0,
1606         },
1607 };
1608
1609 static unsigned long pin_pullup_conf[] = {
1610         PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
1611 };
1612
1613 static unsigned long pin_highz_conf[] = {
1614         PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
1615 };
1616
1617 /* Pin control settings */
1618 static struct pinctrl_map __initdata u300_pinmux_map[] = {
1619         /* anonymous maps for chip power and EMIFs */
1620         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
1621         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
1622         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
1623         /* per-device maps for MMC/SD, SPI and UART */
1624         PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
1625         PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
1626         PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
1627         /* This pin is used for clock return rather than GPIO */
1628         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
1629                                     pin_pullup_conf),
1630         /* This pin is used for card detect */
1631         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
1632                                     pin_highz_conf),
1633 };
1634
1635 struct u300_mux_hog {
1636         struct device *dev;
1637         struct pinctrl *p;
1638 };
1639
1640 static struct u300_mux_hog u300_mux_hogs[] = {
1641         {
1642                 .dev = &uart0_device.dev,
1643         },
1644         {
1645                 .dev = &pl022_device.dev,
1646         },
1647         {
1648                 .dev = &mmcsd_device.dev,
1649         },
1650 };
1651
1652 static int __init u300_pinctrl_fetch(void)
1653 {
1654         int i;
1655
1656         for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
1657                 struct pinctrl *p;
1658
1659                 p = pinctrl_get_select_default(u300_mux_hogs[i].dev);
1660                 if (IS_ERR(p)) {
1661                         pr_err("u300: could not get pinmux hog for dev %s\n",
1662                                dev_name(u300_mux_hogs[i].dev));
1663                         continue;
1664                 }
1665                 u300_mux_hogs[i].p = p;
1666         }
1667         return 0;
1668 }
1669 subsys_initcall(u300_pinctrl_fetch);
1670
1671 /*
1672  * Notice that AMBA devices are initialized before platform devices.
1673  *
1674  */
1675 static struct platform_device *platform_devs[] __initdata = {
1676         &dma_device,
1677         &i2c0_device,
1678         &i2c1_device,
1679         &keypad_device,
1680         &rtc_device,
1681         &gpio_device,
1682         &nand_device,
1683         &wdog_device,
1684 };
1685
1686 /*
1687  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1688  * together so some interrupts are connected to the first one and some
1689  * to the second one.
1690  */
1691 void __init u300_init_irq(void)
1692 {
1693         u32 mask[2] = {0, 0};
1694         struct clk *clk;
1695         int i;
1696
1697         /* initialize clocking early, we want to clock the INTCON */
1698         u300_clock_init();
1699
1700         /* Clock the interrupt controller */
1701         clk = clk_get_sys("intcon", NULL);
1702         BUG_ON(IS_ERR(clk));
1703         clk_enable(clk);
1704
1705         for (i = 0; i < U300_VIC_IRQS_END; i++)
1706                 set_bit(i, (unsigned long *) &mask[0]);
1707         vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1708         vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
1709 }
1710
1711
1712 /*
1713  * U300 platforms peripheral handling
1714  */
1715 struct db_chip {
1716         u16 chipid;
1717         const char *name;
1718 };
1719
1720 /*
1721  * This is a list of the Digital Baseband chips used in the U300 platform.
1722  */
1723 static struct db_chip db_chips[] __initdata = {
1724         {
1725                 .chipid = 0xb800,
1726                 .name = "DB3000",
1727         },
1728         {
1729                 .chipid = 0xc000,
1730                 .name = "DB3100",
1731         },
1732         {
1733                 .chipid = 0xc800,
1734                 .name = "DB3150",
1735         },
1736         {
1737                 .chipid = 0xd800,
1738                 .name = "DB3200",
1739         },
1740         {
1741                 .chipid = 0xe000,
1742                 .name = "DB3250",
1743         },
1744         {
1745                 .chipid = 0xe800,
1746                 .name = "DB3210",
1747         },
1748         {
1749                 .chipid = 0xf000,
1750                 .name = "DB3350 P1x",
1751         },
1752         {
1753                 .chipid = 0xf100,
1754                 .name = "DB3350 P2x",
1755         },
1756         {
1757                 .chipid = 0x0000, /* List terminator */
1758                 .name = NULL,
1759         }
1760 };
1761
1762 static void __init u300_init_check_chip(void)
1763 {
1764
1765         u16 val;
1766         struct db_chip *chip;
1767         const char *chipname;
1768         const char unknown[] = "UNKNOWN";
1769
1770         /* Read out and print chip ID */
1771         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1772         /* This is in funky bigendian order... */
1773         val = (val & 0xFFU) << 8 | (val >> 8);
1774         chip = db_chips;
1775         chipname = unknown;
1776
1777         for ( ; chip->chipid; chip++) {
1778                 if (chip->chipid == (val & 0xFF00U)) {
1779                         chipname = chip->name;
1780                         break;
1781                 }
1782         }
1783         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1784                "(chip ID 0x%04x)\n", chipname, val);
1785
1786 #ifdef CONFIG_MACH_U300_BS330
1787         if ((val & 0xFF00U) != 0xd800) {
1788                 printk(KERN_ERR "Platform configured for BS330 " \
1789                        "with DB3200 but %s detected, expect problems!",
1790                        chipname);
1791         }
1792 #endif
1793 #ifdef CONFIG_MACH_U300_BS335
1794         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1795                 printk(KERN_ERR "Platform configured for BS335 " \
1796                        " with DB3350 but %s detected, expect problems!",
1797                        chipname);
1798         }
1799 #endif
1800 #ifdef CONFIG_MACH_U300_BS365
1801         if ((val & 0xFF00U) != 0xe800) {
1802                 printk(KERN_ERR "Platform configured for BS365 " \
1803                        "with DB3210 but %s detected, expect problems!",
1804                        chipname);
1805         }
1806 #endif
1807
1808
1809 }
1810
1811 /*
1812  * Some devices and their resources require reserved physical memory from
1813  * the end of the available RAM. This function traverses the list of devices
1814  * and assigns actual addresses to these.
1815  */
1816 static void __init u300_assign_physmem(void)
1817 {
1818         unsigned long curr_start = __pa(high_memory);
1819         int i, j;
1820
1821         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1822                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1823                         struct resource *const res =
1824                           &platform_devs[i]->resource[j];
1825
1826                         if (IORESOURCE_MEM == res->flags &&
1827                                      0 == res->start) {
1828                                 res->start  = curr_start;
1829                                 res->end   += curr_start;
1830                                 curr_start += resource_size(res);
1831
1832                                 printk(KERN_INFO "core.c: Mapping RAM " \
1833                                        "%#x-%#x to device %s:%s\n",
1834                                         res->start, res->end,
1835                                        platform_devs[i]->name, res->name);
1836                         }
1837                 }
1838         }
1839 }
1840
1841 void __init u300_init_devices(void)
1842 {
1843         int i;
1844         u16 val;
1845
1846         /* Check what platform we run and print some status information */
1847         u300_init_check_chip();
1848
1849         /* Set system to run at PLL208, max performance, a known state. */
1850         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1851         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1852         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1853         /* Wait for the PLL208 to lock if not locked in yet */
1854         while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1855                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1856         /* Initialize SPI device with some board specifics */
1857         u300_spi_init(&pl022_device);
1858
1859         /* Register the AMBA devices in the AMBA bus abstraction layer */
1860         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1861                 struct amba_device *d = amba_devs[i];
1862                 amba_device_register(d, &iomem_resource);
1863         }
1864
1865         u300_assign_physmem();
1866
1867         /* Initialize pinmuxing */
1868         pinctrl_register_mappings(u300_pinmux_map,
1869                                   ARRAY_SIZE(u300_pinmux_map));
1870
1871         /* Register subdevices on the I2C buses */
1872         u300_i2c_register_board_devices();
1873
1874         /* Register the platform devices */
1875         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1876
1877         /* Register subdevices on the SPI bus */
1878         u300_spi_register_board_devices();
1879
1880         /* Enable SEMI self refresh */
1881         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1882                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1883         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1884 }
1885
1886 static int core_module_init(void)
1887 {
1888         /*
1889          * This needs to be initialized later: it needs the input framework
1890          * to be initialized first.
1891          */
1892         return mmc_init(&mmcsd_device);
1893 }
1894 module_init(core_module_init);
1895
1896 /* Forward declare this function from the watchdog */
1897 void coh901327_watchdog_reset(void);
1898
1899 void u300_restart(char mode, const char *cmd)
1900 {
1901         switch (mode) {
1902         case 's':
1903         case 'h':
1904 #ifdef CONFIG_COH901327_WATCHDOG
1905                 coh901327_watchdog_reset();
1906 #endif
1907                 break;
1908         default:
1909                 /* Do nothing */
1910                 break;
1911         }
1912         /* Wait for system do die/reset. */
1913         while (1);
1914 }