]> Pileus Git - ~andy/linux/blob - arch/arm/mach-tegra/tegra114_speedo.c
Merge branch 'exynos/pwm-clocksource' into late/multiplatform
[~andy/linux] / arch / arm / mach-tegra / tegra114_speedo.c
1 /*
2  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16
17 #include <linux/kernel.h>
18 #include <linux/bug.h>
19
20 #include "fuse.h"
21
22 #define CORE_PROCESS_CORNERS_NUM        2
23 #define CPU_PROCESS_CORNERS_NUM         2
24
25 enum {
26         THRESHOLD_INDEX_0,
27         THRESHOLD_INDEX_1,
28         THRESHOLD_INDEX_COUNT,
29 };
30
31 static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
32         {1123,     UINT_MAX},
33         {0,        UINT_MAX},
34 };
35
36 static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
37         {1695,     UINT_MAX},
38         {0,        UINT_MAX},
39 };
40
41 static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold)
42 {
43         u32 tmp;
44
45         switch (sku) {
46         case 0x00:
47         case 0x10:
48         case 0x05:
49         case 0x06:
50                 tegra_cpu_speedo_id = 1;
51                 tegra_soc_speedo_id = 0;
52                 *threshold = THRESHOLD_INDEX_0;
53                 break;
54
55         case 0x03:
56         case 0x04:
57                 tegra_cpu_speedo_id = 2;
58                 tegra_soc_speedo_id = 1;
59                 *threshold = THRESHOLD_INDEX_1;
60                 break;
61
62         default:
63                 pr_err("Tegra114 Unknown SKU %d\n", sku);
64                 tegra_cpu_speedo_id = 0;
65                 tegra_soc_speedo_id = 0;
66                 *threshold = THRESHOLD_INDEX_0;
67                 break;
68         }
69
70         if (rev == TEGRA_REVISION_A01) {
71                 tmp = tegra_fuse_readl(0x270) << 1;
72                 tmp |= tegra_fuse_readl(0x26c);
73                 if (!tmp)
74                         tegra_cpu_speedo_id = 0;
75         }
76 }
77
78 void tegra114_init_speedo_data(void)
79 {
80         u32 cpu_speedo_val;
81         u32 core_speedo_val;
82         int threshold;
83         int i;
84
85         BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
86                         THRESHOLD_INDEX_COUNT);
87         BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
88                         THRESHOLD_INDEX_COUNT);
89
90         rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold);
91
92         cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024;
93         core_speedo_val = tegra_fuse_readl(0x134);
94
95         for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++)
96                 if (cpu_speedo_val < cpu_process_speedos[threshold][i])
97                         break;
98         tegra_cpu_process_id = i;
99
100         for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++)
101                 if (core_speedo_val < core_process_speedos[threshold][i])
102                         break;
103         tegra_core_process_id = i;
104 }