2 * NVIDIA Tegra SoC device tree board support
4 * Copyright (C) 2011, 2013, NVIDIA Corporation
5 * Copyright (C) 2010 Secret Lab Technologies, Ltd.
6 * Copyright (C) 2010 Google, Inc.
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/clocksource.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial_8250.h>
24 #include <linux/clk.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irqdomain.h>
28 #include <linux/of_address.h>
29 #include <linux/of_fdt.h>
30 #include <linux/of_platform.h>
31 #include <linux/pda_power.h>
33 #include <linux/slab.h>
34 #include <linux/sys_soc.h>
35 #include <linux/usb/tegra_usb_phy.h>
36 #include <linux/clk-provider.h>
37 #include <linux/clk/tegra.h>
38 #include <linux/irqchip.h>
40 #include <asm/hardware/cache-l2x0.h>
41 #include <asm/mach-types.h>
42 #include <asm/mach/arch.h>
43 #include <asm/mach/time.h>
44 #include <asm/setup.h>
59 * Storage for debug-macro.S's state.
61 * This must be in .data not .bss so that it gets initialized each time the
62 * kernel is loaded. The data is declared here rather than debug-macro.S so
63 * that multiple inclusions of debug-macro.S point at the same data.
65 u32 tegra_uart_config[4] = {
66 /* Debug UART initialization required */
68 /* Debug UART physical address */
70 /* Debug UART virtual address */
72 /* Scratch space for debug macro */
76 static void __init tegra_init_cache(void)
78 #ifdef CONFIG_CACHE_L2X0
80 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
81 u32 aux_ctrl, cache_type;
83 cache_type = readl(p + L2X0_CACHE_TYPE);
84 aux_ctrl = (cache_type & 0x700) << (17-8);
85 aux_ctrl |= 0x7C400001;
87 ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
89 l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
93 static void __init tegra_init_early(void)
95 tegra_cpu_reset_handler_init();
99 tegra_powergate_init();
100 tegra_hotplug_init();
103 static void __init tegra_dt_init_irq(void)
105 tegra_pmc_init_irq();
108 tegra_legacy_irq_syscore_init();
111 static void __init tegra_dt_init(void)
113 struct soc_device_attribute *soc_dev_attr;
114 struct soc_device *soc_dev;
115 struct device *parent = NULL;
119 tegra_clocks_apply_init_table();
121 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
125 soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra");
126 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision);
127 soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id);
129 soc_dev = soc_device_register(soc_dev_attr);
130 if (IS_ERR(soc_dev)) {
131 kfree(soc_dev_attr->family);
132 kfree(soc_dev_attr->revision);
133 kfree(soc_dev_attr->soc_id);
138 parent = soc_device_to_device(soc_dev);
141 * Finished with the static registrations now; fill in the missing
145 of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
148 static void __init tegra_dt_init_time(void)
151 clocksource_of_init();
154 static void __init paz00_init(void)
156 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
157 tegra_paz00_wifikill_init();
163 } board_init_funcs[] = {
164 { "compal,paz00", paz00_init },
167 static void __init tegra_dt_init_late(void)
171 tegra_init_suspend();
172 tegra_cpuidle_init();
173 tegra_powergate_debugfs_init();
175 for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
176 if (of_machine_is_compatible(board_init_funcs[i].machine)) {
177 board_init_funcs[i].init();
183 static const char * const tegra_dt_board_compat[] = {
191 DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
192 .map_io = tegra_map_common_io,
193 .smp = smp_ops(tegra_smp_ops),
194 .init_early = tegra_init_early,
195 .init_irq = tegra_dt_init_irq,
196 .init_time = tegra_dt_init_time,
197 .init_machine = tegra_dt_init,
198 .init_late = tegra_dt_init_late,
199 .restart = tegra_pmc_restart,
200 .dt_compat = tegra_dt_board_compat,